JPS58186631U - frequency synthesizer receiver - Google Patents

frequency synthesizer receiver

Info

Publication number
JPS58186631U
JPS58186631U JP8351182U JP8351182U JPS58186631U JP S58186631 U JPS58186631 U JP S58186631U JP 8351182 U JP8351182 U JP 8351182U JP 8351182 U JP8351182 U JP 8351182U JP S58186631 U JPS58186631 U JP S58186631U
Authority
JP
Japan
Prior art keywords
display board
name display
station name
preset
station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8351182U
Other languages
Japanese (ja)
Other versions
JPH0115232Y2 (en
Inventor
山田 恒雄
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP8351182U priority Critical patent/JPS58186631U/en
Publication of JPS58186631U publication Critical patent/JPS58186631U/en
Application granted granted Critical
Publication of JPH0115232Y2 publication Critical patent/JPH0115232Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aおよびbは局名表示板の挿入が可能に構成され
た周波数シンセサイザ受信機の正面図および側面図。第
2図は本考案の一実施例における周波数シンセサイザ受
信機の一部を示すブロック図。第3図aおよびbは本考
案の一実施例に使用される局名表示板の表面図および裏
面図。第4図および第5図は局名表示板識別回路の構成
説明図であって、第4図aおよびbは局名表示板の表面
を正面として挿入した場合における平面断面図および正
面図であり、第5図aおよびbは局名表糸板の裏面を正
面として挿入した場合における平面図および正面図。第
6図aおよibは本考案の他の実施例に使用される第1
のおよび第2の局名表示板の表面図。第7図aは本考案
の他の実施例の主要部を示すブロック図。第7図すは第
7図aに示した本考案の他の実施例における局名表示板
識別回路を構成する検出回路の説明図。第8図aおよび
bは本考案の一実施例に使用される他の局名表示板の表
面図および裏面図。 A・・・周波数シンセサイザ、3. 3A、  3B、
・・・3F・・・プリセット局選択スイッチ、12・・
・可変分周器、15−1.15−2.・・・15−6・
・・メモリ、16および16A・・・局名表示板識別回
路、17および17A・・・スイッチ回路、18.18
Aおよび18B・・・局名表示板。 第6図 第7図
FIGS. 1a and 1b are a front view and a side view of a frequency synthesizer receiver configured to allow insertion of a station name display board. FIG. 2 is a block diagram showing a part of a frequency synthesizer receiver in an embodiment of the present invention. FIGS. 3a and 3b are front and back views of a station name display board used in an embodiment of the present invention. 4 and 5 are explanatory diagrams of the configuration of the station name display board identification circuit, and FIGS. 4a and 4b are a plan sectional view and a front view when inserted with the surface of the station name display board as the front. , FIGS. 5a and 5b are a plan view and a front view when the front thread plate is inserted with the back side facing the front. Figures 6a and ib are the first diagrams used in other embodiments of the present invention.
and a surface view of a second station name display board. FIG. 7a is a block diagram showing the main parts of another embodiment of the present invention. FIG. 7 is an explanatory diagram of a detection circuit constituting the station name display board identification circuit in another embodiment of the present invention shown in FIG. 7a. FIGS. 8a and 8b are front and back views of another station name display board used in one embodiment of the present invention. A...Frequency synthesizer, 3. 3A, 3B,
...3F...Preset station selection switch, 12...
- Variable frequency divider, 15-1.15-2. ...15-6・
...Memory, 16 and 16A...Station name display board identification circuit, 17 and 17A...Switch circuit, 18.18
A and 18B... Station name display board. Figure 6 Figure 7

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の異なるプリセット局名がそれぞれ表面および裏面
に記載されたプリセット局名表示のための局名表示板が
挿入可能に構成され、かつ前記局名表示板の一方の面に
記載されたプリセット局数と同数のプリセット局選択ス
イッチと、前記局名表示板の一方の面に記載されたプリ
セット局に対する分周比データをそれぞれ前記プリセッ
ト局選択スイッチに対応させた番地に記憶させである第
1の記憶装置と、前記局名表示板の他方の面に記載され
たプリセット局に対する分周比データをそれぞれ前記プ
リセット局選択スイッチに対応させた番地に記憶させで
ある第2の記憶装置と、挿入された局名表示板の表裏を
識別する局名表示板識別回路と、該局名表示板識別回路
の出力により前記第1の記憶装置から出力された分周比
データと前記第2の記憶装置からなる出力された分周比
データとを選択して周波数シンセサイザの可変分周器に
供給するスイッチ回路とを少なくとも備えてなる五とを
特徴とする周波数シンセサイザ受信機。
A station name display board for displaying a preset station name, in which a plurality of different preset station names are written on the front and back sides, respectively, is configured to be insertable, and the number of preset stations is written on one side of the station name display board. and a first memory storing the same number of preset station selection switches and frequency division ratio data for the preset stations written on one side of the station name display board at addresses corresponding to the preset station selection switches, respectively. and a second storage device for storing frequency division ratio data for the preset stations written on the other side of the station name display board at addresses respectively corresponding to the preset station selection switches; A station name display board identification circuit that identifies the front and back sides of a station name display board, frequency division ratio data output from the first storage device based on the output of the station name display board identification circuit, and the second storage device. 5. A frequency synthesizer receiver comprising at least a switch circuit that selects the output frequency division ratio data and supplies the selected frequency division ratio data to the variable frequency divider of the frequency synthesizer.
JP8351182U 1982-06-07 1982-06-07 frequency synthesizer receiver Granted JPS58186631U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8351182U JPS58186631U (en) 1982-06-07 1982-06-07 frequency synthesizer receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8351182U JPS58186631U (en) 1982-06-07 1982-06-07 frequency synthesizer receiver

Publications (2)

Publication Number Publication Date
JPS58186631U true JPS58186631U (en) 1983-12-12
JPH0115232Y2 JPH0115232Y2 (en) 1989-05-08

Family

ID=30092518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8351182U Granted JPS58186631U (en) 1982-06-07 1982-06-07 frequency synthesizer receiver

Country Status (1)

Country Link
JP (1) JPS58186631U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010483A (en) * 1973-06-05 1975-02-03
JPS5539471A (en) * 1978-09-14 1980-03-19 Sharp Corp Electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010483A (en) * 1973-06-05 1975-02-03
JPS5539471A (en) * 1978-09-14 1980-03-19 Sharp Corp Electronic device

Also Published As

Publication number Publication date
JPH0115232Y2 (en) 1989-05-08

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