JPS58184902U - RF choke circuit using stripline - Google Patents

RF choke circuit using stripline

Info

Publication number
JPS58184902U
JPS58184902U JP8059782U JP8059782U JPS58184902U JP S58184902 U JPS58184902 U JP S58184902U JP 8059782 U JP8059782 U JP 8059782U JP 8059782 U JP8059782 U JP 8059782U JP S58184902 U JPS58184902 U JP S58184902U
Authority
JP
Japan
Prior art keywords
stripline
choke circuit
choke
strip lines
low impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8059782U
Other languages
Japanese (ja)
Inventor
八尋 哲治
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP8059782U priority Critical patent/JPS58184902U/en
Publication of JPS58184902U publication Critical patent/JPS58184902U/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Motors That Do Not Use Commutators (AREA)
  • Waveguide Connection Structure (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のRFチョークの構成図、第2図は本考案
のRFチョークの構成図である。 1:信号入力端子、2:信号出力端子、3:バイアス供
給端子、4:信号伝送の50Ωライン、5゜8%波長の
高インピーダンスのストリップライン、6’ 、9:1
ハ波長でない低インピーダンスのストリップライン、7
 二FET。
FIG. 1 is a block diagram of a conventional RF choke, and FIG. 2 is a block diagram of an RF choke according to the present invention. 1: Signal input terminal, 2: Signal output terminal, 3: Bias supply terminal, 4: Signal transmission 50Ω line, 5°8% wavelength high impedance strip line, 6', 9:1
Low impedance strip line with no wavelength, 7
Two FETs.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高インピーダンスと低インピーダンスのストリップライ
ンの組合せによって構成されるRFチョーク回路を2つ
重ねた2段RFチョーク回路において、伝送信号の中心
周波数に対応する波長をλとした場合2つの低インピー
ダンスのストリップラインのパターン長を一方をλ/2
より長く、他方をλ/2より短くして、減衰できる周波
数を広帯域にし、減衰量を多くとることを特徴とするス
トリップラインによるRFチョーク回路。
In a two-stage RF choke circuit consisting of two stacked RF choke circuits configured by a combination of high impedance and low impedance strip lines, where λ is the wavelength corresponding to the center frequency of the transmission signal, two low impedance strip lines The pattern length of one side is λ/2
An RF choke circuit using a stripline, which is characterized by making one longer and the other shorter than λ/2, widening the frequency range that can be attenuated, and increasing the amount of attenuation.
JP8059782U 1982-06-02 1982-06-02 RF choke circuit using stripline Pending JPS58184902U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8059782U JPS58184902U (en) 1982-06-02 1982-06-02 RF choke circuit using stripline

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8059782U JPS58184902U (en) 1982-06-02 1982-06-02 RF choke circuit using stripline

Publications (1)

Publication Number Publication Date
JPS58184902U true JPS58184902U (en) 1983-12-08

Family

ID=30089736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8059782U Pending JPS58184902U (en) 1982-06-02 1982-06-02 RF choke circuit using stripline

Country Status (1)

Country Link
JP (1) JPS58184902U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303165A (en) * 2008-06-17 2009-12-24 Fujitsu Ltd Single-layer adaptive plane array antenna and variable reactance circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303165A (en) * 2008-06-17 2009-12-24 Fujitsu Ltd Single-layer adaptive plane array antenna and variable reactance circuit

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