JPS58182381A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To attain image pickup of one screen's share of picture element at one photodetector, by providing a channel stopper region at a part of each photodetector in the same direction to a channel, and separating each photodetector and the channel. CONSTITUTION:Wide sections 2'- of channel stopper regions 2- contact either one side of left and right four sides of each square photodetector P- and key- shaped auxiliary channel stopper regions 21- contact the other side and the upper side. Thus, the other three sides of each photodetector P are separated from a channel 3. The lower one side of the P contacts a gate region 7 comprising a P region formed at the upper side location. That is, the meandered channel 3 is sectioned with the channel stopper region 2 and the gate region 7 and linked with the P via the gate region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CCD (charge-coupled device) II solid-state imaging device, and particularly to an a-sgate type solid-state imaging device having upper and lower layer electrodes that intersect and are insulated from each other.

This type of cross-gate type solid-state imaging device is generally shown in Figure 1.

Figure (1) is a plan view, Figure (b) is the l-
A cross-sectional view of 10,000 Dou, the same figure (e) is a cross-sectional view of 111 direction in (a), and the same figure (the phrase is 11v!J of 111 direction in (&) .In these l!iiiI, 11
) is a semiconductor substrate such as P-type 1 silicon, (21
...The semiconductor substrate is provided in parallel along the surface of the instep, so that several chips are formed by diffusion of impurity tubes, such as P impurity tubes. In addition, this channel stopper area (the middle wide part 1i1 of 21 is located alternately in the stoppers 121 (2) adjacent to each other.+3)...the channel stopper area (2
) separated by a meandering shape I! lvC, a shallow channel, +41ri an insulating film of transparent silicon dioxide or the like formed on the semiconductor substrate 11+. (5
)...a said isolation@(4+the channel stopper area on the instep) A plurality of upper layers t4i< arranged in a direction perpendicular to the direction of 21..., and are insulated and held. Both electrodes (5)..., +61...a are made of aluminum, etc.Here, the F layer, the bottom @electrode (6).
I will now explain the shape of...,;51... in a little more detail.
Add. The upper floor electrode (6)... has the upper channel horn region 1 set to the same width as the above electrode. Also, the lower mt pole (51... has the channel horn region (2))
It is located in a section that straddles the middle and wide sections, which are located alternately.

As a result, the upper layer electrode (6)..., the lower layer electrode'#i, 1
51... depending on the potential applied to the semiconductor substrate 111.
As shown by the arrow in Fig. 1(a), the electric currents such as n etc. (61.
. . . Two-phase clock pulses φ1 and φ2 are applied alternately to each frame, respectively. In the potential well created by...
Naturally, the lower layer electrode (5)... position is higher than the upper layer +1 pole (6:
...It is located in a deeply formed pavilion.

(P) The light incident point (
This light-receiving part (P) has no electrode and is made of an insulator 1 [14] made of silicon dioxide.
Only 1 exists.

In the charge transfer 1g card having such a configuration, during the photoelectric conversion period, when light is irradiated from the electrodes (5)..., (6;...), each light receiving portion CP )..., a certain number of minority carriers, such as electrons, are generated relative to the amount of incident light. At this time, clock pulse φS! High voltage state m, φ! When the voltage is maintained at a low voltage state, the generated electrons are received by the lower electrode (Pi...vc) adjacent to which the clock pulse φ1 is applied (m-gf).
Concentrate below. For example, in the plan view of FIG. 1(a), the electrons generated at the light receiving part (P5 (1) are concentrated at the lower electrode (51 position ■). Then, during the primary charge transfer period, a clock pulse φ1 is applied. When φ2 is switched from a low voltage state to a high voltage state, the electrons μ that were concentrated at Similarly, high voltage is applied to the layer electrodes (14K) and the upper layer 4 poles (6).

The electrons generated at each light receiving section (3) are sequentially transferred along each meandering channel (3). As a result, electrons as image information are ejected to the outside from the terminal end of each channel (3).
Since the light-receiving part is closed at the part where no electrode is present, the light-receiving area is
Compared to a general image sensor equipped with an RC transparent electrode, it has advantages such as no attenuation of incident light. Since the image capturing [・perform #l is prevented, the playback ii
This resulted in a decrease in image resolution *f. Also, when the electrons being transferred to the channel (3) during the charge transfer period reach, for example, the lower electrode position θ, the potential at #O is naturally lowered to this extent, so the light receiving part (open, P)
There is an inconvenience that the electrons generated in There were no words to resolve it.

In view of the points mentioned in the present invention, it has been made possible to capture an image for one pixel with one light receiving section, and further includes a means for separating each light receiving section from the T channel, and a four-sgate solid-state image sensor. 0j12a which is what we offer! An embodiment of the solid-state image sensing device of the present invention will now be described. The same figure -) is a plan view, the same figure C
A cross-sectional view along the IV-IV line in the same figure (
c) (a) Cross-sectional view in the v-v line direction at K, the same figure (
A cross section IIi diagram in the Vi-V11 direction when burning on Menba (a),
It is. In the diagram of Koko et al., (1)%(21,13)
, 141. +5L 161, and () indicate a semiconductor substrate 111% channel stopper region, a channel, an insulating film, a lower layer electrode, an upper layer electrode, and a light receiving part, as in the conventional device shown in FIG. ) as the frame.In this case, a P-type silicon substrate is used, and each upper layer electrode (6
) position, the channel stopper area 121 has parallel pupils.
A higher concentration of P-type impurity is introduced into K. In this case, the channel (3) consists of an N medium-sized region doped with N-type impurities at a high concentration, and has a meandering structure as shown by the arrow in N2 diagram (a). It consists of an insulating film (4: in this case, transparent silicon dioxide 7).

The upper and lower layers are made of a metal material, in this case aluminum, and are perpendicular to each other to form an entrance window tube. The light-receiving part (c) consists of an N'' type region in which a low concentration of N-type impurity is introduced into the semiconductor substrate (11) at the above incident window position. , an auxiliary channel stopper region (2) extending from each wide portion (2) of the channel stopper region (2) is provided.

Depending on this auxiliary channel stopper area (2), each □
They are located at points that partially surround the periphery of the light receiving g(P). 41i (various frame, rectangular light-receiving mail)...
The brim area 12) on one side is in contact with the wide part...
Furthermore, an auxiliary channel stopper area (2) shaped like a key rest is in contact with one side of either the left or right side of the four sides and one side of the upper side. Each light receiving section (g) is separated from the three channels (3) by f'L.

On the other hand, one side below the light receiving part (G) is connected to the lower layer electrode (6).
. . . is in contact with a gate region (7) made of a type P region formed at the upper side position of f. That is, each light is received through the gate region (7) and is divided by a meandering channel (31 channel stopper region (2) and gate region). I) - is connected to... #lI group, the plurality of lower layer electrodes 11 (51...) are alternately given tallock pulses φ1%φI2 marks m''g, and the upper layer electrodes (61-... are alternately given tallock pulses φ2... φ
4 is applied i! fL 4゜Next, refer to the tie (Nanda country and the potential of 411) in Figure 1g5 to clarify the operation of the main element. , odd field charge transfer period Teb,
Each tarok pulse φ1, φ2, .
φl, 44 kIndication L/lAo iI4 WIr
In tl 2 Figure (a) K indicates rIt ■, [Yes]...
The potential t at position t corresponding to . ...t6-1lIrc is shown in the diagram.

First, in the odd field photoelectric conversion period Ta, N
As shown in Figure 3, the gate area below the lower electrode +51151 (
7)...Potentials at positions ■ and ■ are determined by each light receiving part (6 (
In order to lower the potential below the potential of column position O1■, clock pulse φ1ft is set to a high voltage VH level, and other clock pulses φ2. φ5, φ4t? Low is defined as the L level of pressure. As a result, the meandering channel part (3) position θ,
(2) A deep potential well is formed, and the other channels (all La) positions [F], [phase], and e are at a relatively high level. Then, the L level potential φ5
The gate part (7) under the lower electrode (5) to which is applied
...Position ■ always maintains a high level of potential. Channel stopper area 121° Its wide part (2
) and the auxiliary channel stopper region (2). Therefore, at time 1at during this period ia
1, tX, IK 411 K indicates Ta (, depending on the incident light, the odd-numbered column light receiving part (Takumi and Furnace) position 0 and [phase]
The photocharges, in this case electrons, generated in the gate area (7
) position of and beyond channel 13) position θ and ■
can be stored in −10,000, depending on the incident light.

The electrons generated at the even-numbered light-receiving section (no position) are trapped in the potential well at this position llf:
I keep it.

Next, during the odd field charge transfer period Tb [at time t2, the clock pulse φ2 is reached as shown in FIG.
Only the clock pulse φ1 at time tl has an R level of 0% lower voltage, and the other clock pulses φ1, φl, φ4
Let tl be the level. Depending on f'L, the potential well changes from channel (3) position θ at time t1 to position [
F] and also move downward from the t position, so
Electrons follow this potential well into the channel (8
) Move to position [F]. Subsequently, as shown in 1lI311, at 1 time tsfIc, the tarotsuta pulse φS
Only tH level.

At ll, 1lt4, only the tarok pulse φ4 is set to the 1lll level, and the electrons together with the potential well move to the channel (3) positions ■, ■'I! -Move to sth order. Then, at the next time t5, only the clock pulse φ1 is set to the tH level and is transferred to the vc'IIL child t channel (3) position 6, together with the potential well, #dJ. Since φ1 is set to H level which is lower than VH level.

The potential of the gate part 17 device ■, @ under the lower layer electrodes (5), 15) does not decrease much, and the potential of the other gate parts (■, ■ of the 71 position ■) is at a high level.
Depending on the channel (3) position θ, move to C and
This prevents an accident in which electrons generated at the light receiving section (1 (Pl) are mixed into the electrons being transferred.
1. φ2. φS, one of the circles of φ4 is switched to the next fifth level.

In the next even-field photoelectric conversion period To, at time t6, as shown in FIG.
．． φ2. As shown in Fig. 5, each gate part 17)... position ■ as φ411 level.

41 of the potential at position 1 of ■ and ■ - potential 19 of the light-receiving part (to) position ■ is lowered and introduced into the potential well formed at the electron t-channel position @ of the even-numbered light-receiving part (to) do. Subsequently, in the even field charge transfer period Ta, as in the case of the odd field described above, the clock pulses φ1゜φ, φblack, φ4 are
If the switching to the fH level is performed, these electrons are output to the outside.As is clear from the above description, the solid-state TLL image sensor of the present invention has a meandering channel. ,! Since the light-receiving part has a channel stopper area in the same direction as the Nayan channel, this channel becomes 0. Therefore, compared to the conventional element where two light-receiving units S are used to capture one pixel worth of image tfy. It is possible to measure a large improvement in the solution *g.

Furthermore, since the gate region is provided on the side of the light receiving section where the channel stopper region does not exist, each light receiving section and the channel can be separated or connected by this gate region. Therefore, the inconvenience of new electrons from the light receiving unit being mixed into the electrons being transferred through the channel is eliminated, and a clear reproduced image can be obtained.

[Brief explanation of the drawing]

Fig. 1(a), (bl, (C1, ((L) is a plan view and cross-sectional view of a conventional solid-state image sensor)
[c), (d) ζ Plan view and cross-sectional view of one embodiment of the sensor element of the present invention, j[Figure 3 shows a clock pulse timing diagram, and Figure 1N4 shows a potential form diagram. It shows. (11...Semiconductor substrate, (2)...Channel stop area. Button...Auxiliary channel stopper area, 13)...Channel, 14)...Insulating film, (5)...Lower layer electrode,
(6)... Upper layer electrode, ())... Gate region.

Claims (1)

[Claims] 1) - A conductive type semiconductor substrate, an insulating film formed on the semiconductor substrate, and a plurality of lower layer electrodes arranged in parallel on the insulating film. A plurality of upper layer electrodes which are insulated on the top and arranged in a direction crossing the arrangement direction of the lower layer electrodes, and a solid body which constitutes a light receiving part as a total light incident window in the gap surrounded by the Karana 9 and both of the above electrodes. In the image sensor,
In the semiconductor substrate, a channel stopper region into which impurities of the same conductivity type as the substrate are introduced at a high concentration is arranged along the upper electrode of several f'L length, and the channel stopper region is located at the upper or lower layer electrode position. The solid body is characterized in that the solid body is formed by meandering in four ways to partition meandering channels through P, and each light receiving part is provided with a channel stopper area at a side location in the same direction with respect to the channel. Image sensor. 2) A solid body according to claim 1, wherein a gate region is coated with gold on the opposite side of the light receiving section where the channel strainer region does not exist, and each light receiving section is connected to the channel via the gate region. Image sensor.