JPS58182373A - Binary coded circuit - Google Patents

Abstract

PURPOSE:To obtain a binary coded signal in fidelity to original picture information, by improving a contrast correction circuit and a comparison signal generating circut with a video signal tracking circuit, a level tracking range limit circuit and a black level envelope waveform extracting circuit. CONSTITUTION:A signal tracking circuit 5 is an integration circuit, the video signal follows the change of the signal from black to white level with the delay characteristic of a time constant being nearly a period in the maximum picture frequency, and the signal is a waveform EB1 in matching with the video signal to the change from the white and the black level. The tracking to the white level is limited at a prescribed value E1 at a white level tracking limit circuit 9, and a black level envelope waveform EB2 is outputted. Then, the erroneous binary coding due to the ununiformity of background density is prevented. A signal tracking circuit 6 and a black level tracking limit circuit 10 operate as the inverted black and white level, and the circuit 10 outputs a white level envelope waveform Ew2. The output of the envelope of both levels is divided at a resistor RV, and a signal Ed1 is obtained. A voltage E0 and the signal Ed1 of a DC bias voltage source 15 are divided and a signal Ed2 is given to a comparator 16. Thus, white and black binary signals are outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a binarization circuit that has a modified comparison potential generation circuit for binarizing a video signal. This is a useful binarization circuit for use in a nine-part reading section of original image information used in a facsimile machine.

[Description of prior art]

The configuration of a conventional binarization circuit is shown in Figure 1, and its operating waveform II
A is shown in FIG. 2, and the conventional method will be explained.

In FIG. 1, the input terminal IK is for example a facsimile
A video signal such as an image information signal obtained by reading an original with a Q device is input. This video signal is shown as a waveform E1 shown by the solid line K in FIG. 2(a). This video signal E1 is input to the non-inverting terminal 10 of the comparator 2. On the other hand, the inverting terminal of this comparator -
, the positive side of the DC bias power supply Fjc and the input terminal 1
A resistor R8 and a capacitor C8 are connected between the resistor R8 and the capacitor C8.

A comparison signal ``Rj'' having a waveform shown by a broken line in FIG. The video signal Ki is compared with the comparison signal ER1 by the comparator 2, and the output terminal 3 of the video signal Ki is integrated from the total capacitor CoK.
A square wave-like binary signal Io shown in is output.

In such a conventional method, it is difficult to extract small amplitude black information a1 from a white screen or small amplitude white information bFi from a black screen, as shown in FIG.

For example, in order to extract black information a and white information S using the conventional method, if the time constant determined by resistor RQ and capacitors O and K is made small, then the comparison signal is
The waveform ΣR2 shown in FIG. Therefore, the waveforms C and d caused by the non-uniformity of the background density of the original are also extracted, resulting in an erroneous binarized signal as shown in FIG. This drawback can be completely solved by reducing the value of the DC bias voltage Ec, but in this case, Ktj has the drawback that it is impossible to extract the small-amplitude black information a from the white screen. For this reason, the above-mentioned method is not practically adopted.

[Purpose of the invention]

The present invention provides a binarization circuit that improves the contrast correction circuit and disables the comparison signal generation means so as to obtain a binarization signal that is faithful to the original image flavor signal. The purpose is to

[Key points of the invention]

The present invention provides a black level envelope waveform extraction circuit having a means for following a video signal, a white level following range limiting means, and a white level envelope waveform extracting circuit having a means for following the video signal and a black level following range limiting means. Equipped with a circuit,
Based on the divided potential between the black level potential extracted by the black level envelope waveform extraction circuit and the white level potential extracted by the white level envelope waveform extraction circuit, the output potential of the potential generation circuit and the DC potential as a reference. The present invention is characterized by comprising a comparator that binarizes the video signal.

[Explanation based on examples]

In FIG. 3, input terminal 4#'i is the terminal to which the video signal is input. This video signal is obtained by converting image information such as characters and lines on the document into an analog electrical signal using an image sensor or the like in the reading section of the facsimile machine. There is.

Input terminal 4Fi is connected to non-inverting input terminal 10 of comparator 16, and variable resistor 1 (one end of V Similarly, it is connected to the other end of the variable resistor RV via a white level envelope waveform extraction circuit composed of a signal tracking circuit 6 and a black level tracking limiting circuit 10.The signal tracking circuit 5.6 is It is an integrating circuit that operates with a fast time constant that follows the highest image frequency, and the white/black level tracking limiting circuit 9 and lO are each signal tracking circuit 5.
．． This circuit clips the output voltages of 6 at predetermined upper or lower limits, respectively.

The variable contact terminal of the variable resistor RV is connected via the resistor Ra,
It is connected to a DC bias voltage source 15 composed of a resistor Rb and a power source of voltage FXo, and also connected to an inverting input terminal - of a comparator 16. The output of this comparison 516 is led to the binary signal output terminal 17.

FIG. 5 is a diagram showing a specific example circuit of the signal tracking circuit 5.6 and the white/black level tracking limiting circuit 9.10 described above. In the same figure, the circuits surrounded by broken lines 5 and 6 are signal tracking circuits 5.6, respectively, and the circuits surrounded by broken lines 9.10 are white or black level tracking limiting circuits 9.1, respectively.
Indicates 0.

To explain this, the cathodes of diodes D and Fi are connected to the input terminal 4, and their anodes are connected to the power supply V through a parallel circuit of a resistor R4 and a capacitor C4. It is connected to the base of the NPN type transistor Tr. The collector of transistor Tr1 is resistor R2
■ Power supply through. 0 and its emitter is connected to resistor R5
It is grounded through the K ii 11 and connected to one end of the variable resistor RV. Further, the diode D2 has its anode side connected to the input terminal 4, and its cand 9+
ll' (r is grounded through a parallel circuit of resistor R4 and capacitor C2, and is connected to ground via a PNP type transistor Tr.
Connect to the base of 2. The emitter of this transistor Tr2 is connected to the power supply V via a resistor R5. C< is connected to the other end of the variable resistor RV via the line 12, and its collector is grounded via the resistor R6.

Next, the operation of this circuit will be explained.

First, in FIG. 3, when a video signal is applied to the input terminal 4 as shown by the solid line in FIG.

The signal tracking circuit 5Fi, as mentioned above, is an integrating circuit that operates with a fast enough time constant to track the highest image frequency, and its output waveform corresponds to the black of the video signal, as shown by the broken line K in Figure 4 (A). For changes from the level to the white level, the video signal is followed by a delay characteristic with a time constant of approximately the maximum image frequency cycle, but for changes from the white level to the black level, a waveform "Bj" that matches the video signal is used. The output of this signal tracking circuit 5 is input to the white level tracking limiting circuit 9, and as shown by the broken line in FIG. 1111 K Fi black level envelope waveform -7 is output.If the tracking range is limited by the white level tracking limiting circuit 9 in this way, the waveforms C and d due to non-uniformity of the original background density will be You can spin false binarization.

On the other hand, the signal tracking circuit 6 has a signal tracking circuit 11 that tracks the highest image frequency.
This is an integrator circuit that operates with a very fast time constant, and its output waveform is at the maximum image frequency when the video signal changes from the white level to the black level, as shown by the dashed line K in Figure 4 (b). It follows the video signal with a delay characteristic of a time constant on the order of a period, but when changing from the black level to the white level, the waveform ICw+ matches the video signal. Then, the output of this circuit 6 is output to the black level tracking limit circuit IO in the same manner as described above.
In this circuit IO, tracking to the black level side is limited to a predetermined value 2, as shown by the dashed line in Figure 4), and the white level envelope waveform KW2 is output on line 12. .

This signal follow-up circuit 5.6 and white/black level follow-up limit circuit 9
．． The operation of 10 will be explained in more detail based on the specific circuit shown in FIG. In the figure, the diode D of the signal tracking circuit 5 is reversed in the forward direction when the video signal changes from the white level to the black level, so the charging current of the capacitor 0 flows through the diode D. , the output of circuit 5 has a waveform that matches the video signal.On the other hand, when the video signal changes from black level to white level, diode D is biased in the opposite direction, so that the discharge current of capacitor C1 is blocked by diode D.

The input resistance of the white level tracking limit circuit 90 is very large.
Since the inflowing current is negligible, the discharge time constant is 0.0. and K, and the output of the signal tracking circuit 5 is a waveform "B" that follows the video signal with a delay characteristic, as shown in FIG.
It becomes the signal of j.

In the white level tracking limiting circuit 9, the output signal of the circuit 5 is given as the base potential of the transistor Tr, but the maximum value of the collector current of the transistor Tr is the voltage of the resistor R.
2 and resistor R5, the upper limit E1 of the emitter potential for the change of the tracking signal from the white level to the white level
exists, which limits tracking of the white level of the output of the circuit 9. Therefore, a signal having a black level envelope waveform as shown by the broken line in FIG. ts4 (c) is obtained on the line 11.

On the other hand, in FIG. 5, the diode D of the signal tracking circuit 6
2ti, the capacitor 02 is forward biased when the video signal changes from the black level to the white level.
is charged through the diode Dtt, resulting in an output waveform that matches the video signal. In addition, when the video signal changes from white level to black level, diode D2Fi is biased in the opposite direction, so capacitor C! The discharge current is blocked by the diodes D and K. The input resistance of the black level follow-up limiting circuit IO is very large and the current flowing into it is negligible, so the discharge time constant is determined by the resistor R4 and the capacitor C2. Therefore, the output of the circuit 6 has a waveform that follows the video signal, and is shown in FIG.
A signal having a waveform EWI as shown by the dashed line is obtained.

In the black level follow-up limiting circuit 10, the output signal of the circuit 6 is given as the base potential of the transistor Tr2, but it is limited by the collector 1101 resistor R5 of the transistor Tr2 and the resistor R, so that the follow-up signal changes from the white level to the black level. There is a lower limit z2 of the emitter potential with respect to changes in , which limits tracking of the black level of the output of the circuit IO. Therefore, the output of the circuit IO has a white level envelope waveform Fl! as shown by the dashed line K in Fig. 4). . is obtained.

Next, in FIG. 5, the black level envelope waveform output and the white level envelope waveform output extracted from the video signal as described above are divided by a constant voltage by the variable resistor RV, and a fourth line 13 is shown. Signal 1 with a waveform as shown by the broken line in Figure (E)
t11 is obtained. In addition, the DC/(Iasumi pressure source 15 is a circuit that generates a DC bias voltage Σ0, and the signals F, d1 and the free current bias voltage FXO are divided by a resistor Ra and a resistor Rb. A signal K d2 having a waveform as shown in is obtained at the connection A, 14, and is applied as a comparison signal to one terminal of the comparator 16.Thereby, the video signal applied to the other terminal is It is compared with this comparison signal "d2" and outputted to the output terminal 17 as a black and white binary signal as shown in FIG. 4(G).

Note that the DC bias voltage of 1° from the DC bias voltage source 15 is required because of the following development. For example, the potential of one video signal is the potential set by the white level follow-up limiting circuit 9, as shown in parts 8 and f of the video signal shown in FIG. 1 and potential 1 set by the black level tracking limit circuit 10.
If the potential between 2 and 2 is maintained for a constant time, the signal "alFi" at @13 will match the video signal at parts e and f. Therefore, this signal ld is directly used as a comparison signal. The W current bias voltage source 15t-1 is provided to provide an appropriate bias to prevent false binarization.

[Explanation of effects]

As explained above, if the comparison signal generation circuit in the binarization circuit is configured as in the present invention, the problem of erroneous binarization due to non-uniformity of the original area density, which has been a problem in the conventional method, can be completely eliminated. It is also possible to faithfully neutralize small-amplitude black information in white information or small-amplitude 1 information in black information in a video signal.

[Brief explanation of drawings]

Figure 1 shows a conventional binarization circuit. FIG. 2 is a waveform diagram for explaining the operation of the conventional circuit. FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention. FIG. 4 is a waveform diagram of each part of the circuit according to the embodiment of the present invention. FIG. 5 shows a specific example circuit of the comparison signal generation circuit. 4...Video signal input terminal, 5...Signal tracking circuit,
6-! Optimal slave circuit, 9-・White level tracking control win path, 1
0... Black level tracking limit circuit, 15... DC bias voltage source, 16... Comparator, 17... Binarized signal output terminal. Ivy 1 diagram; ¥15 diagram

Claims (1)

[Claims] (1) In a circuit that leads a video signal including white level information and black level information to a comparator, and converts this video signal into a binary signal by comparing it with a comparison potential of a comparison potential generator in this comparator, The comparison potential generator outputs a signal that follows the video signal with a characteristic of delaying the change of the video signal from the black level to the white level, and also outputs a signal that follows the video signal by a predetermined value. A black level envelope waveform extraction circuit that limits the black level envelope waveform extraction circuit, and outputs a signal that follows the video signal with a characteristic that delays the change from the white level to the black level of the video signal. a white level envelope waveform extraction circuit that limits the change to the side by a predetermined value, a DC bias voltage source, the black level envelope waveform extraction circuit, the white level envelope waveform extraction circuit, and the DC voltage (Iasumi pressure source). A binarization circuit comprising: a synthesis circuit that synthesizes outputs and sends the synthesized outputs to the comparator.