JPS58182339A - Data transmitter and receiver - Google Patents

Abstract

PURPOSE:To improve transmission efficiency, by incorporating a time generator, decreasing the redundancy so as to make the section of a transmission and a reception signal clear with the generated timing, eliminating the useless time for the synchronism and reducing errors in interpretation. CONSTITUTION:Electromagnetic waves are received on an antenna 9, unnecessary signals such as image are eliminated at a prestage selection amplifier 10 in advance and inputted to a mixer of the next stage. An averaging processing circuit 16 inputs the timing from a clock 17. An input terminal 17' is a control input terminal controlling the timing of the clock 17, and the time is corrected by the operator manually or it is controlled automatically by transmitting a specific time correction code from the transmission side and receiving the code. Signals are averaged by a predetermined number of times at the predetermined time in the averaging processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmitting/receiving device, and an object of the present invention is to realize synchronization of transmission and reception with a simple configuration, and to enable efficient communication with few errors.

Conventionally, various types of radio waves have been used as transceivers, and they can also be used as data transmission and reception systems. -Blade In order to enable long-distance communication, there is a data transmission and reception system that averages received data based on a synchronization signal synchronized with the signal. Among them, a data transmitting/receiving device that performs averaging processing can obtain an S/N ratio improvement effect for white noise as the square root of the number of averaging times, compared to a transmitting/receiving device that does not perform normal averaging processing. However, in order to perform the averaging process, a synchronization signal that is synchronized with the signal is required, and in order to obtain this synchronization signal, the configuration becomes complicated. For example, it is necessary to form a start signal indicating from which point the signal starts, or to match the phase of the carrier wave when performing synchronous detection. The present invention is particularly characterized by a configuration that eliminates the need for the above-mentioned start signal and facilitates detection of synchronization.

FIG. 1 is a timing diagram of a conventional data signal. 1st
In the figure, when trying to transmit the characters ABC, the same signal is transmitted five times for each of M, B, and C. That is, A1 to M5 are the same signals indicating M, respectively. On the other hand, on the receiver side, M1 to M5. B
An improvement effect can be achieved by averaging 1 to Bs and C1 to C5, and A, B,
It is possible to obtain the C signal.

However, mixing and averaging the M and B signals yields poor results. In other words, to make someone believe i:+f, it is m1~
It is preferable to use only the signals from system 5. Also, since we are aiming for long-distance aerial propagation, we must consider that the signal is buried in aerial noise. In other words, just looking at M1, it is unclear whether this signal is a M signal or a B signal, and M1. A2
5. The joint of B1 is also noisy, so
It cannot be easily determined. Therefore, it has been essential to have a configuration in which a start signal is inserted at a predetermined position in a transmission signal and can be detected.

The present invention solves these problems and enables efficient communication with a simple configuration. An embodiment of the present invention will be described below based on the drawings. FIG. 2 is a timing diagram of signal transmission related to this embodiment. Second
In the figure, a protocol is determined in which M1 to M5 are transmitted using nine absolute time periods T1 to T6, and B1 to B5 are transmitted using absolute time T7 to T+2. Therefore the sending side.

Prepare clocks with the same time on the receiving side, and on the sending side, send the information you want to send, for example A, during the period T1 to T6, and then send the information you want to send next, e.g. B, to the second time during the period T7 to T12. As shown in the figure, T1 to T2 on the transmitting side and on the receiving side. T2-T3
．． Ts~T4. Find the signals for the six periods T4 to Ts and Ts to T6 (all equal times) using your own clock, apply averaging processing to the signals obtained in the predetermined period, improve the -, and then transmit the signal. The signal is read with additional processing to determine what the signal was.

By distinguishing the signals using a clock as described above, there is no need for a start signal indicating the start of the information to be transmitted, and there is no need for insertion of a start signal or configuration for detection. Furthermore, since there is no start signal in the transmission signal, transmission efficiency is improved, and since the timing of transmission and reception is agreed between both parties, redundant time for synchronization can be omitted.
This not only improves transmission efficiency but also prevents synchronization errors and information decoding errors.

FIG. 3 shows a transmitter in one embodiment of the present invention, and the fourth
The figure shows the output waveform. Further, FIG. 5 shows the structure of the receiver (=' 41) in one embodiment of the present invention.

In FIG. 3, 1 is a key input, and 2 is a key mat, which generates an electric signal in response to information inputted by key input. 3 is a time limit code generator which converts the electric signal generated by the key mat 2 into a serial code a predetermined number of times for a predetermined time from a predetermined time based on the time information from the clock 4. It is output to the next AM modulation section 6. The AM modulator 6 uses the frequency f from the carrier wave oscillation circuit 6. The carrier wave signal is converted into an intermittent signal by a serial coded signal fd. After being amplified by the drive circuit 7, it is guided to the antenna 8.

If the key indentation 1 is limited to 26 types from M to Z, a 5-bit serial code signal as shown in FIG. 4A is obtained from the time limit code generator 3. ”1
0100" 5-bit repeating is T1~T2.T2
It represents the period from ~T5.

“10100” is one information among 5 to 2.

This "10100" is a serial coded signal, and this serial coded signal is transmitted from a predetermined time a predetermined number of times for a predetermined time. An input terminal 4' is a control input terminal for controlling the time of this clock 4. FIG. 4(b) shows a waveform when the serial coded signal is AM-modulated and propagated in the air.

Next, in FIG. 6, the airborne radio waves are received by an antenna 9, unnecessary signals such as images are removed in advance by a preselection amplifier 1Q, and the signals are input to the next mixer 11. Here, the signal is mixed with the signal from the local oscillator 12, and then passed through the next intermediate frequency amplifier 13 only in a certain bandwidth in order to obtain the target signal. Since these methods are conventional superheterodyne methods, they will not be described in detail here. The 14 detectors are composed of square law detectors, delay detectors, and the like. In other words, other detection methods may be used as long as the signal component does not disappear even if the signal and noise levels are greater. In a square law detector, for an input of (S+N), the output is (S + N)2, that is, S
It becomes 2,000 2SN ten N2.

If S=gωt, then 52=cos2ωt, and the DC component appears as a signal. Transfer this result to A//DJ member.
15 and converts it into a digital signal. This is to make the next averaging process easier. The averaging processing circuit 16 receives timing from the clock 17 as input.

The input terminal 17' is a control input terminal for controlling the time of this clock 17, and the operator can manually adjust the time, or the transmitting side can transmit a specific time adjustment code and receive it. , it is also possible to control it automatically. Then, the averaging processing circuit averages the data a predetermined number of times starting from a predetermined time. That is, T1-T2. T2~Ts
, Ts~T4. The signals in the periods T4 to Ts and Ts to T6 are stored in memory and averaged.

The signal whose ratio has been improved by the averaging process described above is coded by the code decoder 18 and displayed on the display board 19.

Next, the above averaging process will be explained.

First, T1-T2. T2~Ts, Ts~T4, T4
~Ts.

Each of the signal numbers T5 to T6 is stored in memory.

It is assumed that the signals of T1 and T2 are sampled at a fineness such as S) so that the information of T1 and T2 does not become red. The sampled data is converted into an A/D comparator.
For example, it is converted to D bit, so T1 to T
2, T2~Ts, Ts~T4. T4~Ts.

T5 to T6 each have (S x D) bits of data. Averaging means averaging each sample sample (for example, the first or second sample out of eight).

° Therefore, the averaged result will also have 8 sample values.

Here, the clock timing and signal encoding method, and the clock timing and averaging processing circuit used in the present invention will be explained. These correspond to the time limit code generator 3 of FIG. 3 and the averaging circuit 16 of FIG. FIG. 6 shows the configuration of the time limit code generator 3, where 2o is an information input terminal where 26 types of information are input and encoded by the encoder 23. This encoder 23 has an s bit output. This 5 bit output is sent to the buffer memory 24
and wait for the timing. Timing is manually input from the timing input terminal 21 and transferred to the lock generator 22.
used as a trigger signal. Therefore, the signal is controlled to be outputted a predetermined number of times, for example, five times, starting from a certain time.

When the information input comes in, it is transferred to the buffer memory 24, and when the timing comes in from the end character 21, it is transferred from the buffer memory 24 to the shift register 25, and the shift register is transferred according to the timing of the clock from the transfer lock generator 22. 25 is outputted to an output terminal 26 as a serial code signal.

FIG. 7 shows the configuration of the averaging circuit 16, in which the signal from the input terminal of the digital code signal 27 is connected to the serial input terminals of shift registers 28-32. The shift register selection circuit 37 controls which shift register the code signal is input to, but this shift register selection circuit 37 is triggered by the timing signal from the timing input terminal 36 and automatically selects the internal The shift registers are sequentially selected depending on the timing that occurs. In this figure, the shift registers 28-32 have T1-T2 degrees, T2-T5 degrees, respectively. T
Digital signals of 5 to T4, T4 to Ts, and Ts to T6 are stored. 33 is a summation circuit which adds each parallel output signal when all the data enters each shift register. Next, division is performed by the division circuit 34 and an output is generated from the output terminal 35. The timing of these additions and divisions is determined by the shift register selection circuit 3.
Given from 7.

Incidentally, when constructing a so-called transceiver in which the transmitter shown in FIG. 3 and the receiver shown in FIG. 5 are integrated, the structure for timing generation can be simplified by sharing a clock.

As is clear from the above embodiments, according to the present invention, a time generator is built in, and the timing of the generation makes it clear whether the transmitted signal or received signal is separated. There is no need for insertion or detection, that is, no configuration for this is required. In addition, from the perspective of transmission efficiency, since there is no signal for synchronization, the degree of redundancy is reduced, and there is no wasted time for synchronization when receiving and decoding the transmitted signal, so there is no possibility of errors in decoding. This reduces transmission efficiency and improves transmission efficiency.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram of conventional signal transmission, FIG. 2 is a timing diagram of signal transmission according to the present invention, FIG. 3 is a block diagram of a transmitter in an embodiment of the data transmitting/receiving device of the present invention, and FIG. FIG. 5 is a block diagram of the receiver in this embodiment, FIG. 6 is a block diagram of the time limited yaw lower generator, and FIG. 7 is a block diagram of the average processing circuit. 1...Key input input, 3...Time limit code generator, 4...Clock, 6...
...Muy modulation section, 6...Carrier wave oscillation circuit, 14
......Detector, 16...Averaging processing circuit, 17...Clock, 18...Code decoder, 21...Timing input End, 22...
...Transfer lock generator, 23...Encoder, 26...Shift register, 28-32...
...Shift register, 33...Summing circuit, 3
4...Division circuit, q'...Shift register selection circuit.

Claims (4)

[Claims] (1) A data encoder that obtains digital data on the transmitting side, a transmitter that transmits the digital data, and a first
a time generator, at least one of the timing of the operation of the data encoder or the operation of the transmitter is controlled by the timing generated by the first time generator; It includes an averaging circuit that averages digital data and a second time generating device, and at least one of the timing of the operation of the receiving section or the start of processing of the averaging circuit is set to the timing generated by the second time generating device. In addition to controlling the
．． A data transmitting/receiving device characterized in that the operation timings of the second time generators are the same. (2) First. 2. The data transmitting/receiving device according to claim 1, wherein the second time generating device is shared by one time generating device. (3) First. 2. The data transmitting/receiving device according to claim 1, wherein the second time generating device has a timing at which the second time generating device generates the clock is controlled by an external input. (4) The data transmission and reception according to claim 3, wherein the second time generator on the receiving side is controlled by a time correction signal from the first time generator on the transmitting side. Device.