JPS58176937A - Fine pattern - Google Patents

Fine pattern

Info

Publication number
JPS58176937A
JPS58176937A JP5924882A JP5924882A JPS58176937A JP S58176937 A JPS58176937 A JP S58176937A JP 5924882 A JP5924882 A JP 5924882A JP 5924882 A JP5924882 A JP 5924882A JP S58176937 A JPS58176937 A JP S58176937A
Authority
JP
Japan
Prior art keywords
pattern
wiring
patterns
supporting
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5924882A
Other languages
Japanese (ja)
Other versions
JPH0470772B2 (en
Inventor
Junji Sakurai
桜井 潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5924882A priority Critical patent/JPS58176937A/en
Publication of JPS58176937A publication Critical patent/JPS58176937A/en
Publication of JPH0470772B2 publication Critical patent/JPH0470772B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the fall of a fine pattern by a method wherein supporting patterns which are constituted of the same pattern material layers and not related to the original functions of pattern are projection-formed on the side surfaces including the end parts of the main pattern having the original functions of the pattern. CONSTITUTION:The supporting patterns 2 which have conduction function original to wiring and are projection-formed in a branch form on the both side surfaces of the main pattern 1 of a wiring having a long straight line part and thus have the function of supporting the main pattern 1 not to fall are arranged. The supporting patterns 2 are formed to lengths l1'-l3' and widths W1'-W3' not to influence the adjacent patterns at desired intervals d1-d3 not to influence the adjacent wiring patterns, and formed of the wiring material layers equal to the main pattern 1, therefore heights h thereof are made equal to each other.

Description

【発明の詳細な説明】 (Jl)  発明の技術分野 不発明は微細パターンの構造に係り、%に烏さに比べて
幅の看しく狭い壁状を有し、且つfIL梅部の長い微細
パターンの構造に関する。
[Detailed description of the invention] (Jl) Technical field of the invention The invention relates to the structure of a fine pattern, and the fine pattern has a wall shape that is narrower in width than that of a crow, and has a long fIL plume. Regarding the structure of

(b)  技術の背景 近年、電子ビーム崖光技術、X−篇光技術、工有する微
細パターンの形成が可能になりて釆た〇このような微細
パターンを適用することは、VL8I等高集等高集積場
体ICを形成するうえに1めて有利であり、各方面でそ
の努力が払われている・(C)  従来技術と間融点 従来の微細パターンは、一般に本来の!Ik能を持9柳
分のみで形成されていた◎即ち例えば、配線パターン−
に於ては所望の機III!領域間を電気的に暑続する機
能を持9部分のみで形成され、レジストパターンに於て
は、マスクm11!を持う部分のみで形成される等であ
る。
(b) Background of the technology In recent years, it has become possible to form fine patterns using electron beam cliff light technology, It is the first advantage in forming highly integrated field ICs, and efforts are being made in various fields. (C) Prior art and melting point Conventional fine patterns are generally original! It had an Ik function and was formed only from 9 parts ◎That is, for example, the wiring pattern -
The desired machine III! It has the function of electrically connecting regions and is formed of only 9 parts, and in the resist pattern, the mask m11! It is formed only by the part that has .

然し、倒えば比較的比抵抗の高い多結晶シリコン吟から
なる配線パターン等に於ては、上鮎のように暢■が0.
1〔μm〕程度の微細パターンの場合は、配騙抵抗が大
きくなるのを避けるために、+の高さを1〔μm)程4
:ICする必4Nが生じて米る・又このような微細配−
バメーンを形成する際の選択エツチングは、通常リアク
ティブ・イオンエツチング等のドライエツチング法で行
われるので。
However, in wiring patterns made of polycrystalline silicon, which has a relatively high resistivity, the resistance is 0.
In the case of a fine pattern of about 1 [μm], the height of + should be set to about 1 [μm] to avoid increasing the wiring resistance.
: It is necessary for IC to generate 4N, and also for such fine arrangement.
Selective etching when forming the substrate is usually performed using a dry etching method such as reactive ion etching.

エツチング拳マスクとして用いるレジスト・パターンも
最低1(JIm)@Itの4%−Jが必IKなる・この
ように高さくhl K比べて暢WJが看しく狭く。
The resist pattern used as an etching fist mask must also be at least 1 (JIm) @ 4%-J of It. Compared to the high HL K, the smooth WJ is visually narrow.

しかも本来の機11部分のみで形成される従来構造の微
細バター7に1にでは、特にその直線部分の長さが長く
なると、製造工程中に付加される僅かな外力によって骸
微細パターンの倒れを生じ、 VLS I等の製造歩留
まりが低下するという間−があり九0(dJ  発明の
目的 本発明の目的は、倒れを防止す構造を^備し九歓細パタ
ーンを提供し、上起関伽点を除去することkToる・ (e)  4i明の構成 即ち不発−は、微細パターンに於て、パターン本来の機
能を持9本体パターンの端部を含むI11面ン に1本体パター/と同一のバターI#科層からなり、パ
ターン本来の41I簡に無関係な支持パター/が突出形
iM、′6れてなることを特徴とする0(f)  発明
の夷−例 以下本発明を実施flKついて、靭を用いて評細Kit
!―する0 l12−は牟導体IC等の配縁パターンに於ける一実施
例の要部斜視−で、第3噛はMO8ICのゲート電極に
於ける一実施例の1!部上面図(イ)及びA−A’矢視
断面図<cI)である0 半導体IC等に作り込まれる本発明のm遺を持9アルミ
ニウム(A jJ )、モリブデン(Mo)−モリブデ
ン・シリサイド(Mo8i)、多結晶シリコン等の微細
配線パターンは1例えはs、211!clK示すように
、配線本来の通電機能を有し、且つ長い直#Is分を肴
する配廟の不休ノ(ターンの両鱒向に枝状に突出形成さ
れ、不休)(ターフ1を倒れないように支える機能を持
つ支持)(ター/2が配設されてな9ている0なお同一
に於て、3は二酸化シリコン(SIO曹)−りん珪酸ガ
ラス(PSG)等の絶縁膜である0 そして不休パターン10輻Wが0.1(μm)ii!腹
高さhが1〔μm)程蜆の時、支持パターン2は例えば
5〜10(μm)al魔の、II壁配−ノ櫻ターン等に
影響な与えない所望の間隔’l* dme dmを置い
て、−譬パターンKm響を及はさない長場ム1′。
Moreover, in the conventional structure of fine butter 7 to 1, which is formed only by the original machine 11 part, especially when the length of the straight part becomes long, the skeleton fine pattern may not collapse due to a slight external force applied during the manufacturing process. The purpose of the present invention is to provide a thin pattern with a structure that prevents collapse, and to reduce the manufacturing yield of VLSI etc. (e) The structure of the 4i light, that is, the misfire, is the same as the 1 body putter on 11 planes, which has the original function of the pattern in the fine pattern and includes the edge of the 9 body pattern. 0(f) consisting of a butter I# family layer, characterized in that the original 41I simply unrelated supporting putter/ is made of a protruding shape iM, '6. Then, I will use the detailed evaluation kit.
! -0112- is a perspective view of the main part of an embodiment of the wiring pattern of a conductor IC, etc., and the third part is a 1! of an embodiment of the gate electrode of MO8IC. A top view (a) and a cross-sectional view taken along the line A-A'<cI). (Mo8i), fine wiring pattern of polycrystalline silicon, etc. For example, s, 211! As shown in clK, the wiring has the original power-carrying function, and the turf 1 is protruded in the direction of both trouts in the turn, and the turf 1 is not tipped over. In addition, in the same case, 3 is an insulating film such as silicon dioxide (SIO)-phosphosilicate glass (PSG). Then, when the non-stop pattern 10 width W is 0.1 (μm) II! and the belly height h is about 1 [μm], the support pattern 2 is, for example, 5 to 10 (μm) high. Set a desired interval 'l* dme dm that does not affect turns, etc., and set a long field 1' that does not affect the pattern Km.

it@’、Itm’及び暢Ws ’ 1 % ’ @ 
Ws ’に形成される0従、てd、、 due ct、
、 j/ Am’、 J!m’s Ws ’ eWs 
’ 、 Wa ’はそれぞれ等しい場合もめるOなお支
持パターン2と本体/リーン1!’!、同時に、同一の
配線材料層から形成されるので、その島さhは等しくな
るO 纂3−(イ)及び(ロ)は、本発明の構造を有する多結
晶シリコン−ゲート電極が配設されたMOS  ICに
於ける要部上面及びA−A’天視断面を示したものであ
るO k果槓廣のMO8ICに於ては、ソース電域S及びドレ
イン領域りが形成さnている一つのトランジスタw域の
@WT!、が例えば6−10 (μff1)極度に形成
され、フィールド酸化膜等の絶縁製3に覆われた分1i
IIl域Isoの輻WHgl家例えば2〜3 (11m
)sllに形成されるO従9て図のように複数のトラン
ジスタに共通したゲート電@Gを設ける場合その長さλ
G%!極めて黄(なるOそしてこれらトランジスタのゲ
ート量即ちグー)$ikの幅WQが0.1 (μm)I
ltで。
it@', Itm' and fluentWs'1%'@
0 followers formed in Ws', te d,, due ct,
, j/ Am', J! m's Ws' eWs
If ', Wa' are equal, then support pattern 2 and main body/lean 1! '! At the same time, since they are formed from the same wiring material layer, their island heights h are equal. This figure shows the top surface and A-A' astronomical cross-section of the main parts of a MOS IC. Two transistors in the w range @WT! , for example, is formed to an extreme of 6-10 (μff1) and is covered with an insulating layer 3 such as a field oxide film.
IIl area Iso convergence WHgl house e.g. 2~3 (11m
) formed in sll 9 Therefore, when providing a common gate voltage @G for multiple transistors as shown in the figure, its length λ
G%! Extremely yellow (O and the gate amount of these transistors, that is, goo) $ik width WQ is 0.1 (μm) I
In lt.

しかも該グー)電極Gが比較的抵抗の^い多結晶シリフ
ン等で形成される際には、ゲート電極Gの負荷抵抗な執
少せしめるために前述したようにその高さhG4tl〔
μm)1m度とする必要が生じ、該ゲート電4Gは暢w
Gが鳥さhGに対して看しく狭く、且つ長さAQの兼い
壁状パターンとなる。
Moreover, when the gate electrode G is formed of polycrystalline silicon or the like having a relatively low resistance, the height hG4tl [
μm) 1m degree, and the gate voltage 4G is smooth w
G becomes a wall-like pattern which is noticeably narrower than the height hG and also has a length AQ.

このような場合不発明に於ては、偶えばゲートに*Gの
両11面に6〜10 (a+m)置き、即ち壱分鴫領域
XSO上に位置するように2分#1領域Isoの暢WI
soよりも狭い−W′を有し、&Iするソース配k L
 s 、  ドレイン配−LD等と所定の間隔が保てる
ような長ζL′を有する支持パターン2を形成し、ゲー
ト電極Gの倒れを防止するQなお該実JI11例に於て
は、ゲートーー〇の鉤端−の支持パターン2′は配線パ
ッド領域をかねて。
In such a case, it is possible to place 6 to 10 (a+m) on both 11 sides of *G on the gate, that is, to place the WI of 2 minutes #1 area Iso so that it is located on the 1st area XSO.
The source distribution k L with −W′ narrower than so and &I
s, A support pattern 2 having a length ζL' that can maintain a predetermined distance from the drain wiring LD, etc. is formed to prevent the gate electrode G from falling. The support pattern 2' at the end also serves as a wiring pad area.

広い幅W“に形成している・ 又ゲート電極Gと支持パターン2及び2′は。Formed into a wide width W Also, the gate electrode G and the support patterns 2 and 2'.

四−の多結晶シリフンから同一バターユング工程で同時
に形成される◎ 上記実施例に於ては、不発明を半導体IC等に作り込ま
れるパターンに″)bて説明したが1本発明は上記以外
に、輪l〔μm)II綻の微細パターン形成する際のエ
ツチング・マスクとして用いるレジスト・パターンにも
適用され、その倒れが防止される・ 更に又上記貢施fliK於ては主パターンの両側面に支
持パターンを設けたが、if支持パターンは主パターン
の一万のg4画に設けても良い。
◎ In the above embodiments, the non-invention was explained as a pattern made into a semiconductor IC, etc., but the present invention does not apply to any other than the above. In addition, it is also applied to the resist pattern used as an etching mask when forming a fine pattern with a diameter of 1 (μm) to prevent it from collapsing. Although the support pattern is provided in the main pattern, the if support pattern may be provided in the 10,000 g4 strokes of the main pattern.

(gl  発明の効果 以上wiL明しえように1本発明によれば^さに比べて
幅が著しく狭い壁状の微細パターンの倒れが防止される
〇 従うて本発明はVL8I等尚集積曳の半導体IC等を製
造する際の歩留まり向上に有効である。
(gl More than the effects of the inventionwiL) As can be clearly seen, according to the present invention, collapse of a wall-like fine pattern whose width is significantly narrower than that of the VL8I can be prevented. This is effective in improving yield when manufacturing semiconductor ICs and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

ii1!1図は従来の微細パターンの斜視−1畠2図は
本発明の一実施例に於ける要部斜視図、惑3図は本発明
の他の一実施例に於けるIIN鄭上面上面図)及びA−
A’矢視断面1ii2←)である。 −に於て、1は本体パターン、2e  2’は支持パタ
ーン、3は絶縁層、Wは本体パターンの輪。 dIs a、、dsは支持パターン間隔、W/、Wl/
。 We ’ y Wa ’ @ V/Iは支持パターンの
暢 11p、Bit。 1%、1.1は支持パターンの長さ、Sはソース領域、
Dはドレイン領域、Gはゲート電極、ZIOは分lII
領域、wGはゲート電極の一1w1soは分離領域の幅
・hGはゲート電極の高さ、BGはグー)11E他の長
さ、LDはドレイン配■、Lsはソース配線を示す。
ii 1! Figure 1 is a perspective view of a conventional fine pattern - 1 Figure 2 is a perspective view of a main part in one embodiment of the present invention, and Figure 3 is a top surface of IIN Zheng in another embodiment of the present invention Figure) and A-
A' arrow-view cross section 1ii2←). -, 1 is a main body pattern, 2e 2' is a support pattern, 3 is an insulating layer, and W is a ring of the main body pattern. dIs a,, ds are support pattern intervals, W/, Wl/
. We ' y Wa ' @ V/I is a support pattern 11p, Bit. 1%, 1.1 is the length of the support pattern, S is the source area,
D is the drain region, G is the gate electrode, and ZIO is the
1, wG is the width of the isolation region, hG is the height of the gate electrode, BG is the length of the gate electrode, LD is the drain wiring, and Ls is the source wiring.

Claims (1)

【特許請求の範囲】[Claims] パターン不束の111!能を持り本体パターンの端部を
含む−II1面に1本体パターンと同一のパターン材料
層からなり、パターン本来の機能に無関係な支狩パタ゛
−ンが突出形成されてなることを%黴とする微細パター
ン・
111 with endless patterns! It is defined as mold that a supporting pattern, which is made of the same pattern material layer as the main pattern and is unrelated to the original function of the pattern, is formed protrudingly on the surface of II including the ends of the main pattern. Fine pattern
JP5924882A 1982-04-09 1982-04-09 Fine pattern Granted JPS58176937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5924882A JPS58176937A (en) 1982-04-09 1982-04-09 Fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5924882A JPS58176937A (en) 1982-04-09 1982-04-09 Fine pattern

Publications (2)

Publication Number Publication Date
JPS58176937A true JPS58176937A (en) 1983-10-17
JPH0470772B2 JPH0470772B2 (en) 1992-11-11

Family

ID=13107889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5924882A Granted JPS58176937A (en) 1982-04-09 1982-04-09 Fine pattern

Country Status (1)

Country Link
JP (1) JPS58176937A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185823A (en) * 1984-10-03 1986-05-01 Nec Corp Semiconductor device
JPH05259159A (en) * 1992-03-16 1993-10-08 Nec Ic Microcomput Syst Ltd Shape of wiring in semiconductor integrated circuit device
US6218223B1 (en) 1990-05-31 2001-04-17 Canon Kabushiki Kaisha Process for producing electrode for semiconductor element and semiconductor device having the electrode

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5167082A (en) * 1974-12-09 1976-06-10 Nippon Electric Co HANDOTA ISOCHI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5167082A (en) * 1974-12-09 1976-06-10 Nippon Electric Co HANDOTA ISOCHI

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185823A (en) * 1984-10-03 1986-05-01 Nec Corp Semiconductor device
US6218223B1 (en) 1990-05-31 2001-04-17 Canon Kabushiki Kaisha Process for producing electrode for semiconductor element and semiconductor device having the electrode
JPH05259159A (en) * 1992-03-16 1993-10-08 Nec Ic Microcomput Syst Ltd Shape of wiring in semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0470772B2 (en) 1992-11-11

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