JPS58176782A - Fingerprint collating processor system - Google Patents

Abstract

PURPOSE:To shorten the processing time for collation of fingerprint and to improve the reliability of collation, by using plural collating processors to collate each feature point of a fingerprint and controlling these collations by a control processor. CONSTITUTION:A control processor 1O stores the chip pictures and the segment pictures of all registered feature points of a person who is receiving a check of fingerprint into a receiving memory 3O and then delivers a collation start command after transmitting the data on the chip and seqment pictures, etc. concerning the feature point alpha (alpha=0, 1...n) to a collating processor 1. While the processor 1 receives these data the store them into a memory 3alpha to start collations in response to a collation start command. Then the chip picture is superposed on the segment picture to evaluate the resembrance between both pictures. Thus the way of superposition that has the highest resembrance is search?ed, and then the propriety of collation is decided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fingerprint matching processor system that matches a newly input fingerprint with a fingerprint that is previously set as Vat.

In fingerprint verification, usually many streaks (
Focusing on individual differences in feature points such as the end points and branching points of ridges, we check whether a newly input fingerprint (input fingerprint liI!! image) matches a previously registered fingerprint (reference fingerprint image). is determined from the correspondence between the previous station feature points in these two images.

- In order to find the correspondence relationship, it is necessary to process all 7 patterns of input fingerprint image, a large amount of data amounting to 256 bytes, and find all the feature points. !-It is required that the process be completed within a few seconds at most.
By using a device such as that disclosed in Japanese Patent No. 18932, the high-performance processing of a large amount of data as described above was accomplished by using so-called pipeline processing, in which different operations are performed simultaneously in parallel.

While I was trying to figure out how to use this method)
- Since the hardware becomes complicated, not only does the device become expensive, but its reliability decreases, and the software also needs to be sophisticated in consideration of pipeline control, etc. This invention was developed in consideration of the above circumstances, and its purpose is to provide a fingerprint verification processor system that is highly reliable, easy to program, and capable of high-speed processing of large amounts of data.

The above object of the present invention is to focus on a large number of individual-specific minutiae points present on a fingerprint, and to provide a plurality of collation processors that collate each minutiae point, and to provide all collation data to each of the collation processors and execute the collation process. A management processor that makes a comprehensive judgment of the matching result of the fingerprint from the matching results of the minutiae collected from each of the matching processors, and a management processor that is coupled to each of the processors to store the matching data. This is achieved by a fingerprint verification processor system characterized in that it has a memory and a coupling device Tr* for coupling the respective processors.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an eight-domain hardware configuration of a system for checking the presence of people in a special area (such as Ikuka) using fingerprints, which is an embodiment of the present invention. In the figure, 1° is a management processor, ll-In is a collation processor, 2. ~2111 is a bus coupler, 3°~3. Hamesosu,
4 is a bus, RO is an input/output dedicated processor + (hereinafter referred to as the ``processor 10''), 6 is a bus coupler that connects the processor 5 to the processor 10, and 7 is a processor for the input/output processor 6. Supported by memory. Also, 8 is a card input device, 9
1 is a fingerprint input device, 1o is a reference fingerprint image 7 isle, and 11 is a gate opening/closing device.

The management processor 1° instructs each verification processor to send data necessary for verification of one minutiae on the fingerprint image and perform verification, and also receives the verification results, from which it is determined whether the fingerprint is valid or not. Each processor 1-1 has a bus 4 and a bus coupler 2. ~2°, and the bus coupler 2α (α-0, 1°...1) is connected to the bus coupler 1mF.
) command to communicate with the other bus coupler and data DMA (Di
r+eat M@mory Ao.

・--S) Send and receive.

The dynamics of the Honjitsu 1ml1 device configured as described above will be explained below.

A person who wishes to enter the special placement room first inputs his or her L card into the card input device 8. The reference fingerprint [11) of this person is searched from the reference fingerprint image 7 isle 10 using the number stored in the memory 7 as a clue, and stored in the memory 7, and at the same time, the fingerprint input device 9, a fingerprint input tIP is requested from the person.

When a fingerprint is input to the fingerprint input device 9, this image is stored in the e*print memory 7 and immediately transmitted to the management processor as a reference fingerprint image and an input fingerprint image.

The transmission route at this time is from Engineering 10 Pro Nanatsusa 6 to Bus Coupler 6 to Bus 4. The bus coupler is 2°ti and the memory is 3°.

By the way, the input fingerprint image inputted by the processor 6 of the processing unit 10 is, for example, the serpentine binary image shown in FIG. The image data of the part has a value of “O”), but
What is sent to the management processor is not the entire input fingerprint image, but 4 points estimated to be near the special point #Ik within the input fingerprint image.
・Limited to images (second design). This is called a complete image and is abbreviated as g (engineering, J). Here, engineering y J-1s
2 + ...XJK (See Figure 3 [A). Since it is a cut-out Irt miserable 2f11 W image, g
The value of each point in J) is either ``o'' or ``1''.

10,000, the reference fingerprint images are C and 0 in Figure 2. At the time of registering a fingerprint in the checking system, a person selects a minutiae and instructs the system to scan the entire image of a small area centered on the minutiae. This is a registered image. Hereinafter, this will be referred to as a chip image and will be written as t (is j). Here' r j
-1+2v...see LoC Figure 3). Although this chip image is also a binarized image, it differs from the cutout image in the following points.

That is, the cutout image has a larger size than the chip image (L, >L6), and the chip image is thinned by standardizing the thickness of the fingerprint ridge to 1 (also called "skeletal lineization").

), and the chip image focuses on one feature point of the fingerprint (hereinafter referred to as the mountain part) (the image data of the ridge part is 1").
) and one that focuses on one part between the ridge and the wk line (hereinafter referred to as each part) (the value of 1 image data of the part between the ridges is "1"). be. The chip image 01 shown in FIG. 2 is an example of the former, and the chip images a and 0 are examples of the latter, which are expressed as fl D+ j) t f and (i+ J), respectively.

The management processor 10 stores the chip bust image and cut-out bust image of all the registered minutiae of the person who is undergoing a fingerprint check and [stores them in the receiving memory 3°].
The chip image, cutout image, and search area data between the feature points α are transmitted to α, and a verification start command is issued. Here, the search area is the area indicated by 8 in FIG. 3, and the search area data is data for defining the entire search area 8.2 In FIG. ~L8゜8! The horizontal direction of the rl meeting is expressed as ll-1 to TJ1,
The relationship L m - L x - Lo+ 1 holds true.

The verification processor Ig that has received the data stores the received data in the memory 3α and starts verification kM according to the verification start command. This verification involves superimposing the above-mentioned chip time/image and the 9-1 output image, evaluating the similarities between both images, searching for the method of superimposition with the highest similarity, and then determining whether the verification is successful. be.

The method of overlapping the two images described above can be defined by where the point PJ% in the upper left corner of the chip defect image is located, under the condition that no image protrusion or rotation is allowed. The movable range of the above point r is the search working area S. Therefore, during verification, the following correlation calculation is performed for each point (J, J) in the dlI)w-search area S, and the li1 flexibility of the image at the point P (J) is fully evaluated.

α)! Chip pair focusing on the line part: Image f (t + j
) to J J fl (11 pieces 1 stomach 1 j-
Calculate 1. Here it is.

(1) Calculate the chip sub-image focusing on the part between iis and iii*. Here, we use the following formula, and only when there are 6 points (x"e y") that satisfy the verification pass, we add 0-order formula til1, which sends φ -1 to 1111F management terminal 1°. Point (X.

J Qin) does not exist, φ,=Ot is considered a failure.
Send.

φ, Cx", z")'j: x, tp φ, (X"
,z”)≧x, ---(i) However, K, , is a constant management processor 1. When the processor 1 receives the focus results ψ, f from each matching processor 1.1, it calculates the following comprehensive evaluation. conduct.

However, ■, the constant η = 1 means that the overall evaluation of the matching results of all feature points is passed, and only in this case, the management processor 1° instructs the engineering 10 processor 5 to unlock the gauge. issue.

With this command, the machine 10 processor 6 controls the gate opening/closing device 1.
Command 1 to unlock.

In the above embodiment, the fingerprint verification processor of the present invention
Although we have shown an example in which the entire system is used as a system for checking the number of people using fingerprints, the field of application is not limited to this.

As described above, in the present invention, each minutiae on a fingerprint is compared using 1 mm matching processors, and these are managed by a separate management processor, which improves reliability and reduces processing time. Effects such as shortening can be obtained. To discuss this point in detail, regarding the improvement of reliability,
If the failure rate of one processor is tγ (≦1), then the gold body of the management processor and one type of processor! It is clear that the probability that 1-1 of the +1 units fails and the inquiry system becomes useless is γ1-1, which is smaller than r.

Furthermore, if we ignore the processing time required for one-finger fingerprint verification, and ignore the time required for data transmission and reception, the processing time required for verification of one minutiae is always approximately equal to the processing time required for verification of one minutiae, regardless of the minutiae. Note that this processing time is a small area w (t-1s2
It is possible to shorten the processing time to 1/m by having separate inquiry processors share the work related to y...凰).

[Brief explanation of the drawing]

No. 1m shows the hardware configuration of the system for checking the attendance of people to special areas, which is an embodiment of the present invention. 3 is a diagram showing an example of both input fingerprint images and a chip image, and FIG. 3 is a diagram showing a verification method. 1゜: Management processor, 11-1st: Collation processor,
2゜~2□i bus coupler, 3゜~3゜: memory, 4: bus, δ8 engineering 10 pro sevens, 6: bus coupler, 7: memory, 6: more card input device, 9! Fingerprint human power supply, 10
+Reference fingerprint image file, 11: Gate RWIi device,
A1 human fingerprint image, B1 cutout # image, 01*Os
T-chip image. Figure 2 Continued from page 1 0 Inventor: Minoru Hatada, System Development Laboratory, Hitachi, Ltd., 1099 Ozenji, Tama-ku, Kawasaki City, Hitachi, Ltd. 0 Inventor: Akihiro Kondo, 1-1 Kokubu-cho, Hitachi, Ltd. Kokubu Factory, Hitachi, Ltd. Inside

Claims (1)

[Scope of Claims] 0) vIWl that focuses on a plurality of individual-specific minutiae points existing on a fingerprint and compares an input fingerprint image with a reference fingerprint image for each partial region containing each minutiae; The verification processor provides verification data t to each of the verification processors to give full instructions for verification execution, and also synthesizes the verification results of the fingerprint from the verification results of the minutiae collected from each of the verification processors. 1. A fingerprint m-processor system comprising: a management processor for performing judgment; a memory coupled to each of the processors for storing the verification data; and a coupling device for coupling all of the processors. (2) The fingerprint verification processor system according to claim 1, wherein the verification data consists of data representing the mountain portion of the fingerprint IIi image and at least one of the data representing each portion.