JPS5817408B2 - Automatic offset method of recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for automatically offsetting a recording device 1 of a recording device, such as a measuring device, a detector, etc., which continuously records a DC signal that changes over time.

Generally, a pen recorder is used when testing and evaluating measuring instruments, detectors, etc. (hereinafter referred to as devices under test).

FIG. 1 is a diagram showing the recording state of such a pen writing recorder, in which a signal to be measured from a device under test 1 is supplied to a recording device 2, and a pen 3 is driven to follow this signal to be measured. Changes in the device 1 over time are recorded on a recording paper 4.

Therefore, in the apparatus shown in FIG. 1, since the change over time of the target signal to be measured is recorded on the recording paper 4 over time, the change over time can be clearly understood, and the recording paper 4 has the advantage of being able to be stored for a long period of time.

However, in this type of device, it is necessary to set a unique offset voltage for each device under test 1.

The reason for this is that the output signal level (absolute value) of the device under test 1 and the temporal characteristics of the signal are usually significantly different in order.

For example, in general analog measuring instruments, the output signal level is often on the order of several volts (volts).

So, for example, if the signal level is 5V and its temporal change characteristics are expected to be 1% or less, the input signal range (full scale of pen movement) of the recording device 2 connected to the device output section is 5VX0.01= It needs to be about 50mV.

With this setting, it is possible to accurately measure changes within 1% of the signal under test of the device 1 (for example, changes over time in the signal under test).

However, in order to magnify and measure only the change in the signal under test of device 1 as described above, the absolute value output signal of device under test 1 (the output signal of device 1 when the measurement signal is zero) An offset circuit is required to subtract the

FIG. 2 shows a configuration in which the apparatus shown in FIG. 1 is provided with an offset adjustment circuit.

That is, the absolute value output signal of the device under test 1 is e.

= 5V, if you insert an offset adjustment circuit 6 (subtraction circuit) such as a potentiometer between these 5 devices 1 and the recording device 2 and adjust it to 5V, the absolute value output signal of the device under test 1 will be The time-varying characteristics of device 1 are expanded and recorded with recording device 2 set to 50 mV range.
It can be recorded on paper 4.

However, with this method, it is necessary to adjust the offset adjustment circuit 6 each time due to changes in the equipment 1 or the environment, and if the offset adjustment circuit 6, which is a potentiometer, moves during measurement, the measurement of changes over time becomes meaningless. turn into.

The present invention has been made in view of the above circumstances, and
The above-mentioned offset adjustment by subtracting the absolute value is automatically performed using digital processing means, and this eliminates offset voltage changes during measurement, such as with potentiometers with moving parts, and improves the aging characteristics of the device under test. The present invention provides an automatic offset system for a recording device that accurately and quickly records images on a recording medium, such as recording paper.

Hereinafter, one embodiment of the present invention will be described with reference to FIG.

In the figure, e is a signal under test input from a device under test (not shown), and eO is a signal obtained by subtracting the absolute value output signal of the device under test.

11 is a comparator circuit which receives signals eIN and D-A.
It compares offset voltage ef output from converter 12 and outputs a logic signal.

Reference numeral 13 denotes an offset calibration switch, and when it is turned on, the subsequent one-shot timer 14 is triggered, and a reset signal QR is output from this terminal Q to reset the contents of the up counter 15.

Further, a signal enters the terminal CLK of the flip-flop circuit 16 from the terminal circuit of the one-shot circuit 14, and a signal QS="1" is output from the terminal Q and enters one input portion of the AND circuit 17.

The output signal of the comparator circuit 11 is input to the other input part of this circuit 17, and a "■" signal is outputted under the AND condition of both signals.

18 is a flip-flop circuit.

The up counter 15 has a function of up-counting when a clock signal is input when the terminal Q of the flip-flop circuit 18 is 1'', and storing and holding the counted value.

Output terminal of up counter 15.

, D1 to Dn are D-A converters 12 that convert digital signals to analog signals and output offset voltage ef.
input terminal B.

, B1 to Bn. 19 is a differential amplifier consisting of an OP amplifier, which receives input signals eIN and D.
- The offset signal ef of the A converter 12 is added and the absolute value output signal of the device under test is automatically subtracted to produce a signal e.

Output.

Next, the operation of the automatic offset voltage generation circuit shown in FIG. 3 will be explained.

In the figure, the minimum resolution of the D-A converter 12 is selected to be smaller than the minimum input range (maximum sensitivity) of the recording apparatus, and this value is assumed to be e (V).

Now, when the signal under test e is being supplied to the comparator circuit 11 from the device under test, the offset calibration switch 13
When turned on as shown in Figure 4A, one-shot timer 1
4 is triggered, a reset signal QR as shown in FIG. 4B is output from the terminal Q, and the up counter 15 is reset.

Also, the one-shot timer 14 is inverted and output from terminal Q.
When the 1" signal is output, the flip-flop circuit 16 is triggered and a QS-"1" signal is output from the Q terminal.

At this time, due to the comparison operation of the comparator circuit 11,
When the ``signal'' is output, a ``1'' signal is input to the terminal of the flip-flop circuit 18 when the condition of the AND circuit 17 is satisfied.

As a result, the terminal CE of the up counter 15 becomes 1'' as shown in FIG. 4E by inputting the clock signal (see the fourth diagram).

At this time, since the output of the counter 15 has already been reset by turning on the switch 13 as described above, counting starts from 0 every time the clock signal CLK is input.

Accordingly, the offset voltage e of the D-A converter 12 also gradually increases as shown in FIG. 4F.

Then, when eIN<ef, the comparator circuit 11
The output part of the circuit becomes 0", and the terminal Q of the flip-flop circuit 18 also becomes 0" through the AND circuit 17. At this time, when the clock signal CLK enters the counter 15, the output becomes 0" as shown in FIG. 4E. The terminal CE changes to "0" and the counting operation stops.

Almost at the same time, the terminal Q of the flip-flop circuit 18 becomes 1'', so the flip-flop circuit 16 is reset (see FIG. 4 (j)).

Therefore, at this point, the voltage e (to the offset cell 1 of the DA converter 12) is elN<ef<eINl+2.

In this case 1) If the resolution of the -A converter 12 is sufficiently small, it can be approximated as e T N , ('! f).

As a result, the output level of the differential amplifier 19 is f JN
IN IN... (1).

If el is the voltage at the start of measurement (when the switch 13 is turned on and the calibration is turned 1F), this voltage is the voltage at the up counter 15.
Therefore, if a sufficiently stable D-A converter 12 is used, e' will be held semi-permanently.

, which means that the output voltage e of the differential amplifier 19.

is the voltage obtained by subtracting the current signal to be measured e from the initial voltage e', that is, the voltage e that shows changes over time.

will be output. In the above embodiment, the offset voltage is obtained using the up counter 15 and the D-A converter 12, but as an alternative, the same effect can be achieved by combining, for example, a shift register and an I)-A converter. 3. Moreover, if the difference voltage between the offset voltage ef at the start of measurement and the current signal to be measured e is obtained, the temporal change characteristic can be obtained, and the equation (1) may be completely reversed.

An example is e. -l e r N e f! It's like Nono.

As described in detail above, according to the present invention, the offset calibration switch is turned on whenever necessary to clear the previous offset voltage memory value when measuring the aging characteristics of the device under test, and then the clock signal is counted. However, since this is converted to an analog signal to obtain the offset voltage at the initial stage of measurement, there is no need to reset the offset voltage memory value every time a measurement is made. Well, also time the clock signal? Since the offset voltage is obtained by calculating the offset voltage, the accuracy of the offset voltage value can be improved.

In addition, since the clock count value is stored digitally, it is possible to output a stable offset voltage at all times during the storage period.]・1
We can provide methods.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram for recording the output signal of the device under test.
FIG. 2 is a block diagram of a conventional device that records a time-varying signal by providing an offset adjustment circuit, FIG. The figure is a time chart diagram explaining the operation of FIG. 3. 1...Device to be measured, 2...Recording device,
11...Comparator circuit, 12...
D-A converter, 113...Bias calibration switch, 14...One-shot timer, 15.
...Up counter, 16°18...Flip-flop circuit, 19...9 differential amplifier.

Claims (1)

[Claims] 1 Prior to measurement of the signal under test of the device under test, output a reset signal in response to the signal obtained by turning on the offset calibration switch as necessary, and output the first condition signal after the reset signal is turned off. The output reset signal and condition signal generating means compare the signal under test output from the device under test and the output signal of the D-A converter at the start of measurement, and when the signal under test is thick, the second condition is determined. a comparator circuit that outputs a signal; and a digital circuit that is cleared by the input of the reset signal and that performs up-counting operation of the clock when an AND condition between the first condition signal and the second condition signal is established and stores the counted value. the digital memory, and the D that outputs the count value obtained by this digital memory as an offset voltage of an analog signal.
- A converter; when the output signal of this converter becomes larger than the signal under test, the second condition signal of the comparator circuit is cut off and the condition signal generating means is made inoperable; means for storing and retaining the count value in a memory, and by using a difference voltage signal between the signal under measurement and the offset voltage of the D-A converter corresponding to the pre-stored count value as an input signal of the recording device. An automatic offset method for a recording device characterized by making it possible to know the temporal change characteristics of the device.