JPS5817406B2 - Kenshiyutsu Cairo - Google Patents

Description

[Detailed description of the invention] The present invention relates to a circuit for shaping and detecting a signal input wave.

In recent years, in the field of precision measurement, there has been an increasing need to photoelectrically convert and count light density images such as moiré images and laser interference images.

Since the contrast of these optical patterns is weak compared to that of the light and shade drafts, and the brightness is also low, it is necessary to perform processing such as converting this into an electrical signal and then amplifying it to a considerable level.

In this case, the optical signal itself contains noise components caused by the light source, or noise is mixed in the photoelectric conversion process, electrical amplification process, etc., and the electrical signal contains hum or impulse noise. There are many things.

These noises can cause erroneous measurements.

Although the level detection device disclosed in Japanese Patent Publication No. 46-4289 is not directly aimed at solving the above-mentioned problem, it detects the voltage at the reference voltage input terminal of the operational amplifier that receives the input signal by feedback. Since hysteresis is given to the signal response of the level detector by changing the level detector in stages, it has the advantage of not malfunctioning due to noise within the level.

However, this device cannot respond correctly to impulsive noise of a certain amplitude or more.

An object of the present invention is to provide a detection circuit that can prevent false detection caused by impulsive noise with a narrow duration and large amplitude and noise with a large duration and small amplitude mixed in a signal wave component. Our goal is to provide the following.

First, the outline of the circuit according to the present invention will be explained according to FIG.

A is an amplification circuit including an input signal terminal 1 and a reference voltage input terminal 2.

The curve shown on the input line connected to terminal 1 is a diagram showing approximately one cycle of the signal input wave, with two points showing the level at which amplifier A is activated and a point Q showing the level at which amplifier A is deactivated.

B has an input terminal and a detection output terminal 13, and reads the input terminal voltage, that is, the output voltage of the amplification circuit A, only when a clock pulse is applied; It is a storage circuit configured to continue sending voltage to the detection output.

C is a feedback circuit that feeds back the output of the memory circuit B to the reference voltage input terminal of the amplifier circuit A.

Incidentally, the above-mentioned level detection device uses the memory circuit B having the above-mentioned configuration.
This belongs to the circuit format in which .

Next, the embodiment of the detection circuit according to the present invention shown in FIG. 2 will be further described.

The part surrounded by the dotted line A is the amplification circuit described above.

A first input terminal 5 of the amplifier γ is connected to an input signal terminal 1 via a resistor 3, and a second input terminal 6 of the amplifier γ is connected to a reference voltage input terminal 2 via a resistor 4.

The other end of the resistor 9 connected to the output end of the amplifier γ and the first
A resistor 8 connected between the input terminals is a feedback resistor.

The circuit part explained above is the part that amplifies the signal.

This amplifier is activated when the signal reaches the level of P,
It becomes inactive when the signal decreases and reaches the level of Q.

This level is determined by the voltage level of the reference voltage input terminal 2, as will be described later.

If the level of Q is Vth and the hysteresis width is ΔVth, the level of P is vth+ΔVth.

+Vcc and -Vcc indicate the power supply for this amplifier.

The output level of amplifier 1 is controlled by diode D1 . The portion constituted by D2, transistor P8, and resistor 10.11 is a portion that converts the output to the input signal level of the TTL logic circuit, and in this embodiment, the collector voltage of Pl, that is, the amplifier circuit A. The bilevel of the voltage at the output terminal 12 is 5 volts, and the L level is approximately 0.
Becomes a bolt.

Memory circuit B includes a flip-flop circuit (Texas Instrument Co. 5N) on the positive edge
74-70).

This memory circuit is a circuit that can store input information at the D input terminal during the positive edge of the backclock pulse, that is, the clock pulse changes from L to H, and can take out an output signal from the output terminal QQ.

For times other than about 0.1 microseconds around that point, the output will not change no matter how the input information changes.

The above is exactly the same in the case of a negative edge trigger.

The output terminal Q of the memory circuit B is connected to this detection circuit output terminal 13, from which a detection output is output.

A clock pulse with a cycle of 100 KHz is applied to the clock pulse input terminal CI.

The feedback circuit C effectively amplifies the output of the memory circuit B.
This is a circuit for feeding back to the reference voltage terminal 2 of.

The portion constituted by the transistors Q2 and Q3 resistors 15 and 16°1γ changes the collector voltage of the transistor Q3 to 0 or E1 to 1 in accordance with the Q output of the memory circuit.
This is a circuit that changes the load resistance R6 of Q3 to Q
It has a sufficiently large resistance value compared to the collector and emitter resistance values when 3 is on.

The part formed by the voltage divider (R1+R2) is a part for changing the hysteresis width Δvth.

The portion constituted by the voltage divider (R3+R4) is a portion for changing the inactivation level vth of the amplifier circuit A.

A voltage divider (R, +R2) is connected between the collector and emitter of the transistor Q3.

The voltage divider (R3+R4) is connected between the lead terminal of the voltage divider (R1+R2) and the constant power source R2.

The following relationship is given between the load resistance R6 of transistor Q3 and the resistances of these voltage dividers.

(R3+I(4)>>(Ro+R1+R2)-----
--・-■ Therefore, vth is given by the following equation when Q3 is on.

v th= R3R3/ (R3+R4)...
・・・・・・・・・・・・■ Also hysteresis 1】△
vth goes to 7 Vth=E, R, /(Ro+R1+R2)--
-------...-0 Next, the operation of the circuit according to the above configuration will be explained with reference to FIG.

FIG. 3 is a diagram showing the signal applied to the input signal terminal 1 of the amplifying circuit A and the clock to the memory circuit B superimposed on each other.

Clock pulses are shown simply as dots.

Figures 3 and 3 show circuits obtained by removing the memory circuit from the detection circuit according to the present invention, for example, the above-mentioned Japanese Patent Publication No. 46-4289.
FIG. 2 is a diagram showing the output characteristics of a circuit as shown in the above issue (hereinafter simply referred to as a preceding circuit for simplicity).

1 and 2 show output characteristics for signal waves without impulsive noise, and 2 and 2 show output waveforms when impulsive noise is mixed.

When the input signal voltage gradually increases and reaches vth+△vth, that is, point P, the voltage at output point 12 of amplifier circuit A becomes +5.
■ Become.

If the circuit does not have the memory circuit B like the preceding circuit, this output immediately appears at the output end (■ and ■).

Also, due to the feedback action, the reference voltage input terminal of the intensifier A becomes vth, creating a stable state.

In the circuit of the present invention having the memory circuit B, even if the output of the circuit A changes and the input to the input terminal of the memory circuit B changes, the voltage at the output terminal 13 immediately changes unless a clock pulse is input. Never.

At the time point P' when the clock pulse is input, the human power at the input terminal of the memory circuit is read and the output changes (■ and ■).

Next, when impulsive noise 1 enters, the output in the preceding circuit once reaches the L level and returns to the H level after the noise disappears (I
V).

In the circuit of the present invention, the output does not change (V) unless the positive edge of the clock pulse and the impulsive noise match.

The same applies to noise 2.

Noise whose amplitude is not very large, such as Noise 3 △
Noise that changes within vth does not change the output even in the preceding circuit.

When the signal gradually decreases and reaches Vth, that is, point Q, the preceding circuit immediately changes to L level (■ and ■).

In the circuit of the present invention, even if the input end of memory circuit B reaches the L level, the output does not change immediately, and the output (■ and V) does not change immediately when the positive edge of the next clock pulse occurs.
At the same time as changes, reference input terminal 2 of amplifier circuit A becomes vt.
h.

Then, when noise 4 exceeding the level of vth+ΔVth is introduced, the output of the preceding circuit changes, but in the circuit according to the present invention, the output of the output terminal 13 does not change unless it coincides with the positive edge of the clock pulse (V).

Now, if the frequency of the clock pulse is 100 KHz and the time required to memorize the flip-flop in the positive edge trigger J- is 100 1 seconds, the probability of malfunction is 100 1 seconds compared to the previous circuit. It will be reduced to the value divided by 0.01, or 1%.

Further, the hysteresis width Δvth of the circuit according to the present invention is determined as a function of the resistors R8, R11R2, that is, R1
When R2 is increased and R2 is decreased, Δvth increases.

The level vth that deactivates the increasing circuit A is determined by the resistors R3 and R.
4 and as a function of voltage E2.

Therefore, these can be adjusted independently of each other.

As described above, since the circuit according to the present invention can significantly change the degree to which the detected output waveform is affected by impulsive noise, the accuracy when counting signal wave numbers is significantly improved.

Furthermore, since the detection level can be adjusted independently from the hysteresis width adjustment, the adjustment is extremely easy, and detection reliability can be improved by appropriately adjusting the detection level according to the expected noise level, such as the hum level. .

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the configuration of a detection circuit according to the present invention, FIG. 2 is a diagram showing an embodiment of the detection circuit according to the present invention, and FIG. 3 is a diagram for explaining the operation of the detection circuit according to the present invention. This is a diagram. A... Amplifying circuit, B... Memory circuit, C
... Feedback circuit, 1 ... Input signal terminal of amplifier, 2 ... Reference voltage input terminal of amplifier, C
P: Memory circuit clock pulse input terminal, 1
3.14... Output terminal of play circuit, R1, R
2...First voltage divider of feedback circuit, R3, R4...
...Second voltage divider of the feedback circuit.

Claims (1)

[Claims] 1. An input signal terminal to which a weak analog electrical signal with periodicity is connected, a reference voltage input terminal to which a threshold voltage signal for binarizing the analog signal is connected, and an output terminal to output the binarized signal. an amplification circuit comprising: a signal binarized by the amplification circuit is connected to an input terminal, and the voltage at the input terminal is read and stored only when a clock pulse is applied, and at other times; A storage circuit that continues to send out binary signals that have already been read and stored to a detection output terminal; and a storage circuit that is connected between an output terminal of the storage circuit and a reference voltage input terminal of the amplification circuit; and a feedback circuit configured to provide positive feedback to the binary output of the amplification circuit to a reference voltage input terminal of the amplification circuit.