JPS58173975A - Binary-encoding system - Google Patents

Abstract

PURPOSE:To binary-encode video signal with good resolution simply, by changing the binary-encoding threshold value, depending whether the binary-encoded output level of the picture element just before a picture element to be binary- encoded (noted picture element) is white or black level. CONSTITUTION:A comparator 4 takes a voltage at a connection point between resistors R1 and R2 as a binary threshold value, the level of the inputted video signal is compared in the unit of picture element, to output logic ''1'' level (white) to the picture element having a level above binary threshold and logic ''0'' level (black) to the picture elements having a level below the binary threshold value. The output of the comparator 4 is transmitted externally from a terminal 2 as the binary-encoded output. The output level of the comparator 4 to a certain picture element appears at a Q output of an FF6 at the rise of the main scanning clock incoming just after the picture element. In other words, the binary-encoded output level to the picture element just before the picture element to be binary-encoded (noted picture element) at the comparator 4 appears at the Q output of the FF6 or its inverted level at the Q output.

Description

[Detailed description of the invention] The present invention relates to an improvement in a video signal binarization method.

2. Description of the Related Art In image processing devices such as facsimile machines and digital copying machines, it is common to scan a document with a scanner and convert the read video signal into two values into white and black. In this binarization, the video signal is converted into an analog signal as it is, or is converted into a digital signal by multilevel quantization, and then the level is compared with a binarization threshold to obtain a binarized output. In any case,
Scanner M'PF (Modulation Tr
If the answer function is bad, the binarization (
As a result, thin lines in the original image tend to become blurred, resulting in a reduction in the resolution of the reproduced image.

In order to solve this problem, the level of each pixel of a multilevel quantized video signal is corrected by M 'l' F by referring to the level of surrounding pixels, and the pixel level after correction is converted into a binary 2 of the video signal by comparing the level with the
A method for obtaining digitized output has been proposed. However, this method requires complicated software to perform the M TF correction, and there is another problem that the cost of the binarization device increases.

Therefore, an object of the present invention is to provide a method for binarizing a video signal with high resolution using a simple and low-cost device configuration.

Another feature of the present invention is that in a binarization method that binarizes a video signal by comparing its level with a 2+U conversion threshold on a pixel-by-pixel basis, the pixel to be binarized (the pixel of interest)
The object of the present invention is to provide means for changing the binarization threshold value depending on whether the binarization output level of the pixel immediately before is a white level or a black level. More specifically, this means shifts the binarization threshold to the white level of the video signal when the binarization output level of the pixel immediately before the pixel of interest is the white level, and the binarization output When the level is the black level, the binarization threshold is shifted to the black level side of the video signal.

Embodiments of the present invention will be described with reference to drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In the figure, a video signal is input to terminal 1, and
The value output is obtained from terminal 2, and the high level of the video signal is white.
Low level is black. As for the binary output, the cooking level is white, and the logic level is level '0'.

Diode 1), capacitor C1, and resistor R form a peak hold circuit, and a voltage that follows the peak value of the video signal input to terminal 1 (background level of the original) is obtained at the non-grounded end of capacitor C. . This voltage is input to a high impedance amplifier 3. The resistor R is for discharging the capacitor C when the background level drops and causing the capacitor voltage to follow slowly, and its resistance value is selected so that it is acceptable and the CR time constant is about several seconds.

A series circuit of resistors R1, R2, and R3 is connected to the output of the amplifier 3, and a connection point between the resistors R1 and R2 is connected to one input terminal of a comparator 4 for binarization. The other input of this comparator 4 is connected to terminal l.

5 is a field effect transistor (FE'r), which functions as a switch. The drain (or source) of this FET 5 is connected to the connection point between resistors R2 and R3, and the source (or drain) is grounded.

The gate of FET 5 is connected to the Q output of flip-flop (Ii"F) 6. The 9 output of this FF 6 is connected to the output of comparator 4, and the CK input is connected to terminal 7. The main scanning clock (pulse synchronized with pixel transfer timing) of a scanner (not shown) that sends out video signals is manually input.

Explain the operation in detail.

Comparator 4 sets the voltage at the connection point of resistors R1 and R2 to 2
As the digitization threshold, the level of the heka video signal is compared in terms of pixel degree, and for pixels with a level below the binarization threshold, a logic ``1'' level (white) is output, and for pixels with a level below the binarization m value, a logic level of ``1'' is output. The pixels (two of them output a logic "0" level (black)). The output of the comparator 4 is sent to the outside from the terminal 2 as a 21-digitalized output.

The output level of comparator 4 for a certain pixel is determined by FF6 at the rising edge of the main scanning clock that arrives immediately after that.
Appears at the Q output °. That is, FF6 delays the binarized output by one pixel time and outputs it. In other words, the binarization output level for the pixel immediately before the pixel (target pixel) to be binarized by the comparator 4 appears at the Q output of the FF 6, and its inverted level appears at the Q output.

When the Q output of F p 6 is at the logic "0" level, that is, the binarized output of the pixel immediately before the pixel of interest is at the "1" level (
(white), the FET 5 is in an open state (high impedance between the source and drain). Therefore, the resistor R inputs the output voltage Vp of the amplifier 3 to the comparator 4 as a binarization threshold. Conversely, when the Q output of F'F6 is at the logic "1" level, that is, when the binarized output for the pixel immediately before the pixel of interest is at the "0" level (black),
FET5 is closed (the impedance between the source and drain is sufficiently low). Therefore, the voltage VTL2 which is obtained by dividing the amplifier output voltage VP by the resistors R1 and R2 is P21'tl+R2'.
is input.

Needless to explain, if Vp is constant, VTR>
There is a VTL relationship. In other words, if the binarized output of the pixel immediately before the pixel of interest is °'l'' level (white), the binarized threshold is shifted by 7 to the white level side (high level side) of the video signal, and the 2-value If the conversion output is "o" level (black), the binarization threshold is on the black level side (low level side) of the video signal.
771.

FIG. 2 shows the video signal, binarization threshold, and
The relationship between the binarized output and the Q output of FF6 is shown. This diagram is
This shows a case where a text document with thin lines on a white background is read and scanned. As is clear from the figure, thin lines and narrow gaps between the lines are correctly reflected in the 21 direct delivery force. Therefore, images can be reproduced with high resolution from the binarized output.

Another embodiment of the present invention is shown in FIG. 3. Note that parts equivalent to those in FIG.

In the configuration of the embodiment, when the clock is high-speed,
A delay in switching the binarization threshold due to a delay in the FET 5 may become a problem. Therefore, the non-implemented example is P E 'I'
Without using a switch element like 5, resistors R, 1 and R2
The comparator 11 binarizes the video signal using the white level side binarization threshold VTH obtained at the connection point of , and the video signal is binarized by the black level side binarization threshold VTL obtained at the connection point of resistors R2 and R3. Comparator 1 for binarization
Set up 2.

Then, depending on whether the binary output of the pixel immediately before the pixel of interest is 1" level (white) or "0" level (black), one of the outputs of comparators 11 and 12 is selected and sent to terminal 2. Therefore, the binarization threshold value is indirectly switched. This switching is performed by AND gates 13 and 14, OR gate 15, and FF6.

In other words, the binarized output of the pixel immediately before the pixel of interest is "1"
” level (white), F1 is activated at the time of input of the pixel of interest.
Since the Q output of 1'6 is the "1" level and the Q output is the "0" level, the output of the comparator 11 of the binarization threshold VTR is selected through the A, ND gate 13 and the OR gate 15, and the output of the comparator 11 of the binarization threshold VTR is selected. (= At the same time as it is sent out, it is manually input to FF6. If this binary output is at the "1" level (white), the state of FF6 does not change, so the output of the comparator 11 for the next pixel of interest will also be binary. On the other hand, if the binarized output is at the ``0'' level (black), the Q output of FF6 is inverted at the next pixel of interest, and the AND gate 14 and OR gate 15, the output of the comparator 12 of the binarization threshold VTL is selected and sent to the terminal 2, and simultaneously inputted to the FF6.

In this way, in this embodiment, the output selection of the comparators 11 and 12 is used to switch the binarization threshold.

This switching of the binarization threshold can be performed much faster than switching the binarization threshold using a switch element as in the previous embodiment. Therefore, this embodiment has an advantageous configuration when the main scanning clock is high speed.

In each of the following two embodiments, an analog video signal is converted into 21 times as is, but the video signal may be converted into a multi-level digital signal and then converted into a binary signal. In this case, the comparator that performs the binarization may be a digital comparator, and the binarization threshold may be provided as a digital quantity. Further, in each of the above embodiments (-), the binarization threshold is changed to follow the peak value of the video signal, but this is not an essential element of the present invention.

As described in detail above, according to the present invention, a video signal with poor MTF' can be binarized with good resolution without using a complicated device configuration, and the effect is remarkable.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram of various signals of the same embodiment, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. 1... Video signal input terminal, 2... 21 direct output terminal, 3... Amplifier, 4, 11.12... Comparator, 5... Field effect transistor, 6... Flip 70 tube , 7... Main scanning clock input terminal.

Claims (1)

[Claims] (Level comparison of 11 video signals with a binarization threshold at pixel threat level (in a binarization method that binarizes from two, the pixel immediately before the pixel to be binarized (the pixel of interest) A binarization method characterized by having means for changing the threshold value to 21 depending on whether the binarization output level of the target pixel is a white level or a black level. When the binarization output level of the pixel of interest is the white level, the binarization threshold is shifted to the white level side of the video signal.
2. The binarization method according to claim 1, wherein the partitioning amount value is shifted toward the black level side of the video signal.