JPS58172094A - Generating circuit of carrier signal - Google Patents

Abstract

PURPOSE:To remove a difference frequency component, to eliminate the need for the trap of a filter, and to improve reliability, by setting phase differences between signals 40fN and signals fSC inputted to two converters to 90 deg. and summing up two outputs. CONSTITUTION:A signal switching circuit 11 switches four signals 40fN from a 1/4 frequency dividing circuit 2 to output two 90 deg. out-of-phase signals 40fN. The output of an oscillator 6 is supplied to a converter 14 and also delayed in phase by 90 deg. through a 90 deg. phase shifting circuit 16 to be supplied to a converter 7. The two converter outputs are summed up at a part 15 to remove a difference frequency component while leaving a sum frequency component because the signal 40fN lags the input to the converter 7 by 90 deg. and the signal fSC leads it by 90 deg.. Therefore, almost no spurious component appears at the output of the adder 15 and the trap of a BPF8 is unnecessary. Therefore, the cost is reduced and the performance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is essential for frequency conversion of VTR color signals! The present invention relates to a carrier signal generation circuit for generating a carrier.

In a home VTR, the color signal is band-converted to the lower frequency band of the FM-modulated luminance signal and reproduced. In a VTR system in which the carrier frequency of this low-pass converted color signal is 40fH (fH: horizontal scanning frequency), this band quality [K The required carrier signal has a frequency of 40fH, that is, approximately 421nj7z. . In other words, during recording, when the color signal with the carrier frequency fsc is multiplied by this carrier signal and the difference frequency component is extracted from the resulting sum and difference frequency components, the carrier frequency is 4.
An OfH low-frequency conversion color signal is obtained. On the other hand, during playback, when this low-frequency converted color signal and carrier signal are multiplied and the difference frequency component is extracted, the original carrier frequency becomes fsc
This means that color signals can be reproduced.

This carrier signal is usually created by a circuit like the one shown in FIG. In Figure 1, 1&! .

The first oscillator that oscillates at 160fI (usually a VCO (voltage controlled oscillator) is used), 2 is a divide-by-one circuit, 5
is a signal switching circuit, 4 is a D-flip flop (hereinafter referred to as D-F)
, F), 5 is LpF6 is 5.58 MHz,
In other words, the oscillator of irises 2 oscillates at fsc, 7 is the converter, and 8 is BPF1? 1 is a horizontal synchronizing pulse input terminal, and 10 is a carrier output terminal.

The output of the first oscillator 1 is divided by 1/4 times by the 1/1 frequency divider circuit 2, and is divided into four 40'f
It becomes l signal. The signal switching circuit 5 switches and outputs these four 40fH signals every horizontal scanning period (hereinafter abbreviated as I) to produce a 40fH signal whose phase is shifted by H*Kqo°.

This 40fH signal is further knocked back by the 160fI signal at DF, 1°4 so that the 90@ phase relationship is maintained accurately. This phase shift processing is performed to reduce the amount of noise from adjacent tracks.

The 40fH signal that is the output of D-F, F, and 4 is generally a rectangular wave and contains many harmonic components of 40fH, so it is
After this harmonic component is reduced by the PF 5, it is supplied to the converter 7 and multiplied by the output of the second oscillator 6. Therefore, the output of the converter 7 is the sum frequency (4.21 Mlh in fsc + aOfx) and the difference frequency (2.95 MHz in fsc -40fH) of these two input signals.
It becomes two frequency components. By passing this through a BPF 8 containing a trap at the difference frequency as shown in FIG. 2, a desired carrier signal of fsc+40fx is obtained.

If this difference frequency component remains, it will cause distortion in both phase and amplitude of the converted 40fH signal, as will be explained below.

extremely accurate and large attenuation (more than 40 da at 2.95 MEz) is required.

Now, assuming that a color signal having a phase difference φ is input with respect to a carrier signal, frequency conversion is performed as shown in the following equation.

(2) (2πfsc・t+φ)・Focus 2π(fsc+40
．． fi;r)t+(2)(2πfsc・t+φ)・k(
2) 2K(fsc-4Oflr)tten-[(2)2π(
C2fsc-4ofx)t+φ)+oos (2π・
40f1・t+φ)〕・・・−・・・・・・・・・・・・
・・・・・・・・・・・・・・・(1) (However, k is the carrier (fsc+aofx) spurious for K (f
sc-40fl) level ratio) 4ofx with LPF 5
If only the frequency component is taken out, it becomes 5, which is a linear equation, as can be easily seen from equation (1).

&sm2φ width ((2 40fl −φ) −αrctα' 1 +
kcm2m '...-...) In other words, the phase of the color signal (
(that is, hue) K, the amplitude & main (
1-k) to (1+&), that is, the amplitude ratio varies by a factor of 10 from the original amplitude. The phase also varies from the original phase φ to ±αrctal.

In this way, the color saturation level 1 hue is changed depending on the phase (that is, hue) of the color signal.

K that keeps this shadow within 1°, 196 is 0.
01 or less, that is, the attenuation of BPF 8 must be 40tLx or more.

Because such strict specifications are required, the conventional method has the following two problems.

First, the cost is high because adjustments are required. The second point is that since such a trap is necessary, BPF
The problem is that the transient response time of the step-like phase transition of the input signal to B becomes longer. As mentioned above, since the 40fH signal has a 90" phase shift for each B, this BPF 8
The input signal to the input signal also undergoes a 90# phase shift every H. Since this phase switching is performed using a horizontal synchronizing pulse, the switching point is approximately 4 μ3 before the burst signal. Therefore, when the transient response time becomes longer, the transient response period enters the burst signal period. For this reason, the burst signal no longer has correct phase and amplitude information, and correct color reproduction is no longer possible.

The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and eliminate the need for expensive filters! It is an object of the present invention to provide a carrier signal generating device that provides improved performance and improved performance.

For this purpose, in the present invention, two converters are provided, and the phase difference between the 40fH signals input to these two converters and f
By setting the phase difference of the sc signals to 90 degrees, making the sum frequency component in the two outputs in-phase and the difference frequency component in opposite phase, adding these two outputs, and removing the difference frequency component from K, This makes it unnecessary.

FIG. 3 is a block diagram showing one embodiment of the present invention. 1
1 is a signal switching circuit that outputs two 40fH signals with a phase difference of 90 degrees, 12 is a second DF, Fo, 13 is a second LPF, 14 is a G2 converter, 15 is an adder circuit, 16 is a 90@phase shift circuit. The present invention will be explained in detail using FIG.

The signal switching circuit 11 switches the four 40fH signals that are the outputs of the frequency divider circuit 2 for each H. The section is configured as shown in FIG. 4, for example.

α, ~α4 are each 40f out of phase by 90@
The H signals, B, and ~H4 are generated by frequency division from the horizontal synchronizing pulse for only 1H period) and A (Btg
k) 4H cycle switching pulses, G, to G8 are two-manpower NAND gates, G,.

Gto is a 4-person NAND gate.

Now, α, is for α, α, is for α, and G4 is G3
It is assumed that the phase is delayed by 90 degrees.

If we assume that from H8 to E, , Hs, H4 and Jli there will be a no-i period, now in the H period when Hl becomes no-i,
G1 is output from the NAND gate G with the opposite phase, and the NAND
D game) Go, Gs - Since the output of G4 is in the No-Y state, G1 is output from the HAND gate G.

On the other hand, α.

is output from NAND gate G6. Since the output of G,,G,is in a high state, NA
ND Goo) G10 α is output.

Next, when K Ht goes high, this time the NAND gate G!
Since the gates of and G are selected, the HAND gate G@
*G11) outputs α and a, respectively.

When H8 goes high, HAND gate Gs and 0 gates are selected and HAND go)
Hatake and G4 are output, and when H4 becomes high, NARD gate G4G Hatake is selected, and NAND gate~F Go e G
l. 6 and α are output respectively. Next K again H
When l goes high, the HAND gates G, , G, are selected, and the NAND gates) Go -G,. , α, and α, are output respectively.

In this way, the two outputs φ and φ are always φ and φ,
While the phase relationship of 90" delay is maintained, the phase is delayed by 90@ for each H (. In this way, two desired outputs are obtained. These two signals are respectively 10D- F, F, 4 and 20th D-F, F, 1
2, it was re-tapped with the same black signal, and it was correctly 90＠
K so that the phase relationship is maintained.

On the other hand, the output of the second oscillator 6 is transmitted to the second controller (-14
On the other hand, the 90° phase shift circuit 16 is connected to the 90°
@The phase is delayed and the first conno (-toughly supplied, supplied.

Therefore, in the first converter 7, the following multiplication is performed.

cas2π@40fH-t+■2π-fsc -t-'
1os2π(f sc+4Dfx)t+cxs2πCf
5 c - 4 of
Since the r signal is delayed by 90 degrees and the fsc is ahead by 90 degrees,
The following multiplication is performed.

(-dH2π・40fH−6)th2π・fsc −t
= ± ((2) 2π sc + aOfx) is partially 2π (fs
c-40fH t... (4) Therefore, adding the two converter outputs, 0m2π(fsc + 4(3fx) t...
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・(5), only the sum frequency component remains,
The difference frequency component is removed.

As a result, the output of the adder 15 has almost no spurious components, so the BPFB does not require the conventional circuits and circuits, and can be completed with a very simple configuration of, for example, one L and one C element. Of course, no adjustment is required.

This 90@phase shift circuit 16 and JLL converter 7
, the second converter 14 and the addition (9) path 15 are as follows:
For example, it can be easily realized in the form shown in FIG.

In FIG. 5, 17 is an input terminal to which the output of the second oscillator 6 is applied, 18 is an input terminal to which the output of the first LPF 5 is applied, and 19 is an input terminal to which the output of the LPF 15 of 's2 is applied. A terminal 20 is an output terminal of the adder circuit 15.

This is the circuit. The transistors Q and Q11 constitute a fully balanced multiplier, which serves as the first inverter 7, and the transistors Qtt to Q4 constitute a fully balanced multiplier, which serves as the second converter 14.
Furthermore, the transistor QstQll * (i'll *
Since the collectors of the QCs are connected in common and the output currents are added by the resistor R13, an adder circuit 15 is configured at the same time.

Here, a constant bias is applied to the transistor Q+s t Q10, and the same bias is applied to the transistor Qlt QCs and the capacitor C! The frequency fs that occurs at
Since the alternating current signals of c are added together and applied, the differential pair transistors Qx2*QCs and Qlat Qll are switched with the signal phase of the frequency fsc generated in the capacitor C.

On the other hand, capacitors C and K are connected to transistors Qll and G8.
A signal of the resulting frequency fsc is applied and the transistor q
, and Qlo are applied with a signal having a frequency fsc generated in a series-connected load of resistor R2 and capacitor C1. Therefore, the differential pair transistor Q,.

Q, and the differential pair transistors QIo and Qll are switched by the phase of the difference signal between these two signals.

By the way, as can be easily seen from FIG. 5, this difference signal is ultimately the voltage across the resistor R1. Transistor Q, h/
6 is sufficiently high, the same current flows through the resistor R8 and the capacitor CI, so the voltage across the resistor R1 becomes a signal in phase with this current, and the voltage across the capacitor C becomes a signal delayed by 90' from this current.

Transistor Q4 is conductive on the positive polarity side of the signal voltage across capacitor CI, whereas transistor Q11 is conductive on the negative polarity side of the voltage across resistor R2. Transistors Q□ and Q have the same relationship, so in the end, the second
The differential pair transistor Ql! of the converter 14 of pQ
la and Q 14 e Qll are switched with a phase lead of 90@ with respect to the differential pair transistors Q, , Q· and QCs l Qll of the first converter 7.

In this way, since the voltage across the resistor and capacitor is used, a phase difference of 90° can be maintained very accurately.

Also, resistors R6, R, which determine the gain. , R,4,R,
If they are integrated into the same IC, they all need the same resistance value, so they can be manufactured with a relative accuracy of about ±1-. therefore,
The difference in level between the two converter outputs can be extremely small. Even if we take all the variations into account, it is easy to make the difference frequency component less than -30 dj compared to the sum frequency component, so it is sufficient to attenuate 10 ctj with BPF,
BPF 8 beams.

An extremely simple filter of about one stage C is sufficient.

Further, as is clear from FIGS. 4 and 5, the scale of the added circuit is small, and most of it can be integrated into an IC, so there is almost no need to add peripheral components. Second LPFls
Even so, only one circuit each for L and C is sufficient. In this way, assuming IC implementation, BPF 8 can be easily pressed,
Since no adjustment is required, the cost is low.

Also, since BPF 8 has simple and broad characteristics,
The transient response time during switching can also be shortened, the influence of the transient response on bursts can be significantly reduced, and color reproducibility can also be improved.

In order to maintain the phase difference between the two 40fl signals at 90'', it is not necessarily necessary to use the signal switching circuit 3 as shown in FIG. 5; for example, as shown in FIG.
, F, 4 output to one more stage D-F, F, 1
It may also be obtained by passing 2.

In this case, compared to the case of FIG. 3, the NARD shown in FIG.
5 gates of G11-Ga and G1° can be omitted.

Further, the VTR that performs the signal processing described above is a two-head helical power scan type VTR.

In this case, since two modes are switched for each field, the phase of the carrier wave of the reproduced color signal becomes discontinuous at the time of this switching. At this time, when the phase approaches 180°, it takes time for the TV's APC* to follow and the demodulation axis of the TV's color signal to reach the normal phase, making it impossible to reproduce colors correctly.

To prevent this, when the carrier phase approaches 180', the phase of the 40fx signal may be inverted by 180@ to invert the carrier phase and correct the discontinuity. To do this, K may be configured as shown in Part 7. In FIG. 7, 22 is an input terminal for inputting a pulse to control the phase inversion of 40fx 2, and 22 is this pulse input terminal 2.
T-F whose state is inverted by the pulse input from 1;
! ,.

G, , G, 1 is an inverter, 011 to G1M are 2
It is a human-powered NAND gate. Now, when Q is high, G
,hG,.

f) Since one input of the NAND gate is in the high state,
The other input (that is, the output of the phase switching circuit 11 is inverted and outputted. On the other hand, G8.

Since one input of the Gl HAND gate is always in the low state, the output remains in the )-i state. Therefore, G
, s, G, , after all, φ, which is the output of the phase switching circuit 11, and φ!, respectively. is output.

On the other hand, when the Q outputs of 7-F, F, 22 are in the no/no state, G, 4. The signal from G is '1@S'
'16, so φ1, φ, and (
15 Signal power 1 whose phase is inverted from the output of the phase switching circuit 11
Output.

Here, as is easily understood, φ, with respect to φ,
In the case of a 90° phase lag, φ also has a 90° phase lag with respect to φ, so the first DF, F, 4
The phase difference between the outputs of and the second D-F, F, 12 is T-F
, F, remains constant regardless of the output state K of 22.

In this way, phase inversion is performed before D-F and F, because gates have a delay time between input and output, and this delay time differs depending on each gate.
The phase difference between the I output and the 01.0 output deviates from 90° by the delay time difference caused by this variation. This time difference is 6t, D-F, F, 4 and D-F, F, 12
It is absorbed and the phase difference is exactly 90@.

Using two D+F and F in this way and locating the means for aligning the phases of the two signals at the end is extremely preferable in terms of performance.

The example explained above is the case of NTSC. In the case of pAL, when recording with one head, there is a 90° phase shift similar to NTSC (the phase is delayed by 90° for each H).
However, when recording with the other head, this processing is not performed and the phase is continuous. In this case, any one of the switching pulses H3 to H4 shown in No. 4 IiK
It is only necessary to keep one high at all times, and the present invention can be applied as is. However, in the case of NTSC, the required carrier frequency is fsc+4o1x, but in the case of pAL, fsc
+ aafx + fir. Therefore, p
At present, it is common to set the first oscillator to 40 fl and the second oscillator to f sc + -fx at AL0.

In this way, the present invention can be applied as is even if fsc +-fx is used instead of fsc, which is the frequency of the second oscillator 60, and it goes without saying that no inconvenience will occur. Shitakatsu [
, in FIG. 3 or 7 during PALO, the oscillation frequency of the second oscillator 6 is fsc + -flKL,
When recording the rosin of the signal switching circuit to one side, it is delayed by 90 degrees every H. When recording to the other side, it is delayed by 90 degrees every H, and when recording to the other side, one of the switching nodes Itl-H4 is set to no. All you have to do is convert it to .

Furthermore, in the case of pAL, it is also possible to set the oscillation frequency of the second oscillator 6 to fsc, similar to NTSC. In this case, a pulse of the oscillation frequency wave number of the first oscillator is created, and an offset of -fi is created. In this case, a configuration as shown in FIG. 8 may be used. The only difference from FIG. 7 is that a divide-by-7 circuit 26 that divides the output of the first oscillator by one is added. Of course, the T inputs of the first DF, F, a and the second DF, F, 12 may be the oscillator output of the first oscillator.

In addition, in a home VTR, the carrier wave frequency of the recorded silver color signal is (44--)fl, and when recording with one head, the phase is continuous, and when recording with the other head, the phase is reversed every 1H. (180° phase shift). The present invention can be easily applied to this case as well, for example,
This can be realized as shown in the figure. In FIG. 9, 1 is the first oscillator that oscillates at 175f1, 24 is the first oscillator,
The pulse (NT) indicates which head is in use.
Head pulse input terminal for inputting 5QHz (in case of SC). Reference numeral 25 designates a switching circuit for outputting two signals having a phase difference of 90° with a phase inversion every 1H when one head is used, and a continuous phase when the other head is used. If the portions of the upper frequency divider circuit 2 and the switching circuit 25 are expressed as *, the result will be K as shown in FIG. In Figure 10, D-F, F,
, 28 is the second TP', F constituting the one-frequency divider circuit.
-* Gto to G14 are two-man powered NAND gates.

The 50th D-F, F, and the 4th D-F, F, 27 are
A synchronous frequency divider circuit is configured with the output of the oscillator 1 of @1 as the T input. Therefore, these two D −F,
The duty of all four Q and ζ outputs of F is 50tste,
90° phase difference (D-F, F, 26 (DQD-F, F,
27 Q, D-F, F, 26 Q, D-F, F
.

It is a signal with a 90° delay in the order of Q of 27).

(Of course, this type of divide-by-one circuit can also be used in the cases of Figures 3, 7, and 8.)
Four signals with a 0° phase difference can be generated.

On the other hand, when the TFF2B head pulse is low, the horizontal synchronizing pulse is divided by one, so Q and Q become high alternately every 1H. Therefore, from GWt, D
The ζ output and the ζ output of the FF 27 are output, and the ζ output and the ζ output of the DFF 26 are outputted alternately every 1H from the G14, and the phase of each is inverted every 1H. G again
t When I output is Q of DFF 27, G, 4 output is D
Since it is the ζ output of FF 26, the Gt4 output is always Gt
There is a 90° phase delay with respect to l. For example, when Dobals is No. 1, K.

The second FF 28 is always Q regardless of the T input.
Assuming that , the G,1 output becomes the ζ output of the DFF 27, and the G snow 4 output becomes the ζ output of the DFF 26, resulting in a continuous phase.

In this way, even with the method of inverting the phase every 1H,
This means that it is possible to generate two signals with a 90° phase difference extremely easily.

As explained above, in the present invention, the oscillation output that oscillates at an integral multiple of the horizontal frequency is divided by 7 or
Create four signals with a phase difference of 0°. In the signal switching circuit, two sets of signal switching sections having the same configuration are provided, and the signal switching section is connected to the signal switching section so that the signals outputted with the same switching pulse have a 90° phase difference in the two signal switching circuits. 90
The configuration is such that four signals (or parts thereof) having a phase of - are inputted to two signal switching sections, respectively. Furthermore, a phase inverter is provided to synchronously invert the phases of the two signals output from the signal switching circuit according to INK, and finally the phases are adjusted using the same clock pulse. For this reason, the phase shift of 90° (or 180a) for each H can be performed very accurately, and at the same time, the 90° phase difference between the two signals can be maintained very accurately.

Also, the second oscillator 6 is fsc (158 in NTSC)
Since the oscillator oscillates at MHz (4.45 MHz for PAL) or its vicinity (usually within ±fx), it can be made into an extremely stable oscillator using a crystal resonator. Therefore, the phase shift circuit 16 only needs to shift the phase by 9011 considering the frequency of about one point, so this is also a switch for switching the accurate crystal oscillator, 33 is the crystal oscillator for PAL, and 64 is for NTSC. Water crystal oscillator, 56 is D-F, F, 37 is PAL/NTSC switching signal input terminal, G2l1'''''G, ? , G! ,~G0 requires two people N
AND gates G, , 0.8 to G, 6 are inverter circuits.

In Figure 11, VCO 29 &
Oscillates at 8fH. Therefore, when divided by i, (47
+ −> fH. With this and the oscillation frequency fsc of the second oscillator, the carrier frequency f required for NTSC is
sc+ (47+ −) lx is obtained.

4 On the other hand, during NTSC, the "H" output becomes high and the D -
The Q output of D-F, F, 35 is fed back to the DVC of F, F, 55. Therefore-C1D-F, ! ,
35 is divided by one frequency. D-F, F, 56 is this D-7
', Since the Q output of 1.55 is input, D-F, F
, 56 output a signal 1H before the output of DF, F, 35. In other words, when Q of DF, F, 55 is high, D -F, F.

Q of 36 is low, reverse [D-F, F, when Q of 55 is low, Q of 56 is high.

Therefore, G! Since one of the inputs of 9 and G8I is always low, G, , .

The output of Gs@ is always low. On the other hand, G16 is D-
When the Q of F, F, 35 is 4-, both hands) 1 A,
GI is 2 when Q of D-F, F, 55 is No/I.
Human power is also high. Therefore, for every 1B, there are 4 G
The output of Gse and Gse can have a phase shift of 90@. Therefore, by adding the outputs of the two converters, the addition of the sum frequency component and the subtraction of the difference frequency component can be performed extremely accurately. , it goes without saying that the scope is extremely wide. For example, in NTSC, the carrier frequency of the color signal recording signal is (47+-)jx
When recording on one side, the position is reversed every H, and on the other side, the phase is continuous, and in PAL, (47--)fz
A method has also been proposed in which the phase is shifted by 90° every H when recording with one head, and the phase is continuous with the other head.

Even in such a case, NTSC' can be achieved by switching only part of the circuit and using it as shown in Figure 11.

It is easily understood that it can be used in common for both pALs very easily.

In Figure 11, 29 is approximately 378f in NTSC.
i is a VCo that is controlled to oscillate at approximately 375fi during PAL, 50 is a phase inversion during NTSC, and pAL
Signal switching circuit with occasional 90° phase shift, 31.5
2 gets you high. Ga4 is D-F, F, 26 f)
Q and D-F, F, 27 no Q, Gse is D-F,
Since the Q of F, 27 and the Q of DF, F, 27 are selected, phase inversion every 1H can be realized. To, when the pulse is No. 1, D-F, F, 26 and D-F, F,
Since the Q of 27 becomes No), the output of 0.3 always becomes No, and the phase shift is stopped.

Next, the operation during pAL will be explained. At pAL, VCO
29 is controlled to oscillate at 575fl.

Therefore, when the frequency is divided by -, it becomes (47--7;'')fl.

On the other hand, K, switch 51, and switch 32 are switched so that the oscillation frequency of the second oscillator 6 becomes the fsc of PAL. Also, the time constant of 90@phase shift circuit 60 is PAL's fs
c.

From this K, the frequency of the carrier signal becomes fsc+(47-,)flK required during pAL.

On the other hand, at pAL, the input side of G□ becomes 7・A, and D−F
, F, 35, the Q output of DF, F, 56 is fed back. Therefore, D-F, F, 35 and D-F, F, 36 constitute a one-frequency divider circuit. Therefore, the outputs of Ga3 to G86 are sequentially turned on every 1H, and D-F, F, Q of 27, D-F, F,
26 Q.

D-F, F, Q of 27, D-F, F, Q of 26
and are sequentially switched every 1H. In this way, 90 phase shifts can be realized. This phase shift may be advanced or delayed by 90 degrees every 1B.

When the pulse is high, it is the same as the NTSC, and 6
．． Only 3 goes high and the phase shift is stopped.

According to the present invention, since the logic circuit generates a 90° phase difference between two signals at the same time as processing the phase shift of ``ax9o'', it is possible to obtain an extremely accurate 90° phase difference.
Since each converter circuit multiplies signals with a 90° phase difference of frequencies near fsc, the difference frequency component, which is an unnecessary component of the two converter circuit outputs, is accurately multiplied by 1.
It becomes possible to set the phase to 80°, and cancellation can be performed by adding the output of this converter circuit, making it possible to eliminate traps. Therefore, significant effects such as phase error improvement due to a reduction in transient response, cost reduction, and substrate area reduction are brought about because there is no need for traps or traps.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional carrier signal generation circuit, FIG. 2 is a characteristic diagram showing an example of frequency characteristics required for a BPF, and FIG. 3 is a diagram showing an example of the frequency characteristics required for a BPF. , Figure 4 is a circuit diagram showing the main parts of the signal switching circuit, and Figure 5 is a circuit diagram showing the main parts of the signal switching circuit.
The figure is a circuit diagram showing a specific example of a 90° phase shift circuit.
Figure 7 is a diagram showing a second embodiment of obtaining a 90@ phase difference in the output of the first oscillator, and Figure 7 is a diagram showing a second embodiment of the present invention. Fig. 8 is a diagram showing the third embodiment of the present invention, Fig. 9 is a block diagram showing the fourth embodiment of the invention, and Fig. 10 is a specific example of a divide-by-7 circuit and a signal switching circuit. FIG. 11 is a circuit diagram showing a fifth embodiment of the present invention. Explanation of symbols 1・・・・・・・・・・・・・・・・・・First oscillator 2・・・・・・・・・・・・・・・・・・−Frequency divider circuit 1
1.25... Signal switching circuit 4.12...
......D-F, F. 7.14...Converter circuit 15...
・・・・・・・・・Addition circuit 6・・・・・・・・・
......Second oscillator 16...
・・・・・・・・・ 90° phase shift transition circuit 'ff11 diagram'

Claims (1)

[Claims] The first oscillator register that oscillates at an integer multiple of the horizontal frequency is 1 or 2) □frequency divider circuit and the □m x 4
mx From the output of the 4 frequency divider circuit, le × 90 @ phase transition for each horizontal station (however, le is 0,
1, 2.3) A first phase shift circuit that generates two signals having a phase difference of 90°, and a first converter to which one of the two outputs of the first phase shift circuit is input. ,
a second converter into which the other output of the first phase shift circuit is input; a second oscillator that oscillates at or near the color subcarrier frequency; a second phase shift circuit that converts into two signals having a phase difference and supplies one signal to the first converter and the other signal to the second converter, the first converter and the second converter; A carrier signal generation circuit comprising: an addition circuit for adding outputs of converters.