JPS58170289A - Synchronizing signal generating circuit of pal system television signal - Google Patents

Abstract

PURPOSE:To process PAL signals with a simple subtraction or addition and to obtain the synchroinzing signal of PAL accurately and easily, by processing the offset component at each horizontal period specific to the PAL signal digitally. CONSTITUTION:A clock CP4 four times the chrominance subcarrier frequency fsc is applied to a horizontal address counter 2 from a reference signal forming circuit 1 and a pulse having 2 fH of frequency is applied to a vertical address counter 3. A line discrimination signal from the counter 3 is applied to a phase sfifter 4 and a readout control circuit 5 and a signal different from the phase by 90 deg. from a phase shifter 4 is applied to a wave shape ROM 9. A type discriminating signal from the circuit 5 is applied to a burst gate signal generating circuit 6 and a data ROM 7, and the offset component at each horizontal period is processed digitally by using an operation circuit 8, the ROM 9 and a digital filter 10. The synchronizing signal of PAL is outputted accurately by processing it with a simple subtraction or addition.

Description

[Detailed description of the invention]

The present invention relates to a horizontal synchronizing signal and a vertical synchronizing signal for a PAL television signal, and relates to a synchronizing signal generating circuit that generates an equivalent pulse within the vertical blanking period, more preferably a color burst signal. 2. Description of the Related Art In recent years, television signals have been converted into digital signals, which are then recorded and played back by digital VTRs. In this case, the horizontal and vertical synchronizing signals of the television signal, as well as the color burst signal, etc., are signals with a fixed frequency and phase relationship, so when recording the digital television signal to the VTR, remove these signals. Then, during playback, the reproduced digital television signal is converted back into an analog signal, and then formed based on the first quasi-signal in the synchronization signal generation circuit on the playback side at the original original synchronization signal position and color burst position. K complete original analog TV with additional insertion of 9 sync signal or color burst signal? ) trying to get a blasphemous signal. In this way, a synchronization signal generation circuit is required on the reproduction side, and normally, in this circuit, the horizontal synchronization signal, vertical synchronization signal, color burst signal, etc. are generated at the color subcarrier frequency f. For example, in the case of the NTSC system, 55 fl (+-=2'm (fx is the horizontal frequency)...
------From the relationship (1), " m c-910f
m and frequency 4f. By using the fact that the clock of 4f is an integer multiple of the horizontal frequency, It is possible to create a vertical synchronization signal by dividing the frequency of j (clock) by a counter to form a horizontal synchronization signal by K, and further dividing this horizontal synchronization signal by a counter. In the case of a PAL television signal, the relationship is 0, and the frequency is 4 because of the component '625'.
7. . Even if it is used as a reference signal, it will not be an integer multiple of the horizontal frequency 9, and the synchronization signal etc. will not easily form ζ. The purpose of this is to accurately generate a synchronization signal digitally. An example of a generating circuit according to the present invention will be explained below with reference to the drawings. 11th! ! FIG. 9 is a lock diagram illustrating the configuration of the metal body of this invention. In Fig. 1, (1) is a reference signal forming circuit, and in this reference signal forming circuit (1), the frequency is 4.
f,1! Clock cps and CPs whose frequencies are 2f0 and f, which are obtained by dividing CP4 (Fig. 2).
(Figure III B and C) Three types of reference signals are formed. (2) is a horizontal address counter, and this horizontal address counter (2))K is counted by being supplied with a clock CP4 of frequency 4f and @ from the reference signal forming circuit (1). And in this horizontal address meeting (2),
By counting four CP4, one horizontal trench is obtained, and O addresses for one horizontal period are obtained. Here, the clock CP4 of l water period K471@ is C
Only 1135 + 645 ) pieces will be included, but if j
Assuming that only 1135 K1 horizontal period Sekimushi 9 puk p tsuku CP4 will be included, we will divide this into the first half (0 to 566) and the second half (θ to 567) and count them ( This reduces the equalization/4 las and half 9 ji that occur during the vertical retrace period.In this way, as mentioned above, 4 fse = (1135
+ finger) Since there is fm, one frame of 625 horizontal lines is short by 7202404 black lines. Therefore, in this horizontal address counter (2), the second half of the last line of the l frame is set as a period for counting four extra clocks (0 to 571) CP4 (
(See the lower part of the second diagram). Further, from this horizontal address counter (2), the frequency 2'IP (f
NP generates a pulse 2112 (E) at a horizontal frequency (temporary). These 2f, 0 pulses P are supplied to the HFi vertical response counter (3). This vertical address counter (3)
In this case, this pulse P is counted (0 to 1249) to make one frame period, and the top 1 of the count output is
A 0 bit (the least significant bit is not used) is used to create a vertical address, an address indicating a multiline line number (.theta..about.624) (see FIG. 2F). Also, the lowest pin of this vertical address counter (3)
#il Since this is a signal whose state is alternately inverted to @θ″11″ every horizontal period, this is used as the line discrimination signal LID. Used as a line discrimination signal between even and odd lines. Furthermore, a signal FID which is inverted every frame is obtained from this vertical address counter (3). (4) is a phase shifter, and the phase shifter (4) receives signals 02 and 2fa of frequencies f and c from the reference signal forming circuit (1).
The signal CP3 of t and the line discrimination signal LID from the vertical address counter (3) are supplied, and this line discrimination signal causes the frequency zse and the signal CP1 of 2f, e.
and CP snow, and as shown in the vector diagram in Figure 3, the frequency fma (D signal is obtained every 2 ins) with a different phase of 9011. Also, the signal of frequency 2f1. is inverted for each line. 1 Next, (5) is a readout control circuit. This readout control circuit has a vertical address counter (signal FI that inverts the state for each frame from the stem).
D is supplied, and a count output consisting of 11 pins, and vertical address data V indicating 0 to 1249.
ADD is supplied. In addition, a horizontal address counter (2
), the data of the 10th focus (29) is supplied to the top. In this read control circuit (5), the read of the data ROM (7) is controlled by the vertical address data VADD indicating 0 to 1249 sent from the vertical address counter (3) and the signal FID which is inverted every frame. It is something to do. In other words, first of all, the output signal to be obtained is divided into four types as shown in Fig. 4, depending on the pulse width in the horizontal period (equalized for the synchronization signal, the arm pulse is 1, and the base pulse width) and the presence or absence of the color burst signal. Type I, I, l. A signal RC for identifying these four types is taken out as a selection signal from this read control circuit for two pits and is supplied to the data ROM (7). Next, in this readout control circuit (5),
Figure 4 tie! In the case of ■ and type ■, there is no need to read data in the latter half of each horizontal period and the pedestal level is always sufficient, so data ROM (7) is used for this part.
A signal HIMP is generated to stop reading of the data ROM (7), and the data ROM (7) is controlled by this. The type identification signal RC from the read control circuit (5) is supplied to the parsing (r-) signal generation circuit (6). Further, horizontal address data HADD for 9 pits from the horizontal address counter (2) is supplied to this /f-st dart generation circuit (6), and the read control circuit (
5) It is determined whether or not it is a horizontal period in which it is necessary to generate a burst signal by the signal RC from 5), and when it is a horizontal period in which it is necessary to generate a burst signal, K indicates that the burst signal should exist. A burst f-to signal that is at a high level for a period is formed from the horizontal address information. Data ROM (7) Fi One waveform worth of data is written for each of the synchronizing signals and the envelopes of the burst signals of the four types of output signals of types I to N described above. This data ROM (7) contains horizontal address data HADD from the horizontal address counter (2).
is supplied to its address terminal and type 1.1
．． The signal RC from the readout control circuit (5) for identifying ``Zen'' and ``2'' is supplied as the most significant two pits of the address, and four types of output addresses are selected. Therefore this data ROM (7)
Then, the signal RC selects which of the four types of signals to read out in that horizontal period, and then horizontal address data HAD is read from the beginning of that horizontal period.
The data is sequentially read out by D, and data as shown in FIG. 4 is extracted. As mentioned above, Thailand! In the case of ■ and ■, there is no change at all in the second half of one horizontal period and there is no need to read data, so the signal HIMP from the read control circuit (5)
Therefore, even if horizontal address data HADD is supplied to this data ROM (7), its read operation is stopped. In this way, the synchronization signal waveforms of types 1 to 2, the envelope of the burst signal, and the equalization pulse waveform are each extracted from the data ROM (7) as data for the focused focus, and these are supplied to the arithmetic circuit (8). be done. This arithmetic circuit (8) has the upper 10 of the 11 bits of address data VADD of the vertical address counter (3).
A bit (address indicating the line number mentioned above) is supplied. This arithmetic circuit (8) corrects the timing phase, which is peculiar to the PAL signal mentioned above and shifts every horizontal period. The details of the correction will be described below. The arithmetic circuit (8) calculates the level information read from the data ROM (7) and the top 10 pits of the vertical address data VADD from the vertical address counter (3) as described below, thereby achieving the above-mentioned PAL method. -125” per horizontal period characteristic of a television signal of
As a result, output signals of type 1.1° II and mV are obtained from the arithmetic circuit 8, respectively. In this case, the color burst signal is its envelope! This is obtained as the output of the arithmetic circuit (8), but the amplitude is similar to that of the horizontal interperiod (4 pulses) of this color burst signal. The data (8 pins) from the arithmetic circuit (8) thus obtained is supplied to the waveform shaping ROM (9), and as described later, a limiter is applied at the sync chip level of the synchronization signal, and the burst signal envelope 0 - is limit shaped based on the synchronization signal's sync signal level, and furthermore, the burst signal's envelope is made to have a phase difference of 90 degrees every horizontal period by the phase shifter (4) as described above. The signal CPl of the frequency fee is superimposed on the envelope 7 portion as a burst signal. The output (8 bits) of the waveform shaping ROM (9) thus configured is supplied to a digital filter (G) in order to remove sharp corners such as nip portions of the output. Then, the output (8 pins) data of this digital filter (7) is D
- It is supplied to the gam converter (c) to restore the analog waveform, and it is supplied to the filter (6) for smoothing and output to the output terminal (to). Next, the operations of the data ROM (7), the arithmetic circuit (8), and the waveform shaping ROM (9) will be explained in more detail. The input of the data ROM (7) is the horizontal address counter (
9-bit horizontal address data HADD from 2) and 2-bit signal R from read control circuit (5)
These are address information for a total of 11 pits of C, and a control signal HIMP from the read control circuit (5). And the output is adjusted to analog level such as synchronization signal11
There are 12 bits in total, including digital data of the pit and one bit of a control signal used for controlling whether addition or subtraction is performed in the arithmetic circuit 8. The signal HIMP forces all 12-bit output data to a high level (to stop readout) in the following two cases.The portion raised to a high level at this time is transferred to the waveform shaping ROM (9). When the limiter is shaped with When Shitaibu 1 or Rin is selected, if it becomes the half of that l Mizuko period, data R
The tie written in OM (7)! The data corresponding to point 1 is as shown in FIG.
This is for the lower 9 pits specified by DD. 1 to obtain the horizontal synchronization signal from "0" of "0" to r99j
1 pittle health data n, %D・kai are written, and the address no. ``100'' or r511J contains an 11-pit repeat kf''-toe-I to obtain the envelope f-It of the burst signal. ) s■ is written. In this case, more information on each of the falling and rising edges is written than the necessary level information. In other words, in this case, the level data is 11 pits. Because of this, levels from 0 to 2047 can be expressed, but as shown in Figure 5, the black level (
Pedestal level) ha 1250 level, sink tip level halo 25 level,! : Establish the first f. Then, as information on the fall of the synchronization signal, data from the data Do at address "0" to address "8" from the necessary 1250 level to the θ level, which is 625 lower than the 625 level.
9 Sunnors up to data D8 are allocated at equal level intervals. On the other hand, regarding the information on the rise of the same network signal,
Nine samples from data DI4 at address "84" to data DI at address "92" are allocated at equal level intervals up to 1875 level, which is 625 higher than the required 625 level to 1250 level. address"
8” data D Lu to address “83” data D11
All the data up to the address "92" are at the O level, and the data from the address "92" to the data D-- at the address "99" are all at the 1875 level. The width of the sync tip portion of the horizontal synchronization signal is a frequency of 4f. This corresponds to 80 clocks CP4. data ro
The output data of M (7) is stored in the waveform shaping ROM as described above.
In (9), the result is the sync chip level (625
Since the limiter is applied at the sync chip level), the width of the sync chip level part is the width from data D4 to DI4, and the data is read at the clock cycle CP40, so
That's equivalent to 80 cp4 clocks. Since the length from the trailing edge of the synchronization signal to the leading edge of the burst envelope corresponds to 12 m of the clock CP4, the leading edge of the burst envelope is data D1° at address r100J. becomes. The falling edge () and rising edge information for the envelope of the burst signal are exactly the same as the falling edge and rising edge information of the synchronization signal, and the data I)t at address r100J.
9 from oo to data DIO- at address r108J
The information about the falling edge of the sandals is at address r136J.
data Dtsa to data D1 at address r144J
Rising information is written for 9 samples up to 44. The data Dies "" DI31 from address r108j to r135J are all set to 0 level,
Data D14 from address r144J to r511J
4 to I) stt are all set to the 1875 level. Next, in the case of tie fTi, only information whose rising and falling edges of the synchronizing signal of tie 7'l are exactly the same as that of 9 is written. In other words, in the case of this type ■, information on the envelope of the burst signal is not written, and from data D*1 to Dill, data with a level of 1875, which is 625 levels higher than the black level, is continuous. . In type (2), the slope portions indicated by eight pieces of falling and rising data are stored in eight pieces each, such as data D and D8 and data D44 to Dsl, as in types I and (2). Since type (2) is a half-edge error within the vertical blanking period, the width of the sync tip level portion is set to be equal to 40 elementary cyclic clocks CP4 of the horizontal synchronizing signal. Therefore, the data that should be at the sync chip level are data D4 and data D44 that is 024040 clocks later. Therefore, the information at the level of rising 9 is eight pieces from data D44 to data DIl. Type ■ is vertical synchronization noise, and as shown in Fig. 4, this data must have a width equal to the sync chip level portion of three clocks CP4048.Therefore, in this case, the data that should be at the sync chip level is data D4. and I) asy, ibC, data D, to D, . . . are O level data, so the data at the rising edge 9 is taken to be from data Dast to data Dass. In FIG. 5, the level of all data after the data Dats is set to 2047K, which indicates that the data is not read out but raised to a high level by the control signal HIMP. In the above case, the level difference in the rising and falling parts is created by data for 9 samples each, so this level difference is 9625
2 = 1250 levels are clock CP in terms of time
This is equivalent to 8 cycles of 4. Therefore, the length corresponding to the Lebel difference is one hundred cycles of the clock CP4. This is nothing but an error with respect to the clock of frequency 'flle for each horizontal period shown in FIG. 6, which is specific to the PAL signal mentioned above. On the other hand, as shown in FIG. 7, if the falling level data is added by the level data, the rising waveform of and will be shifted upward in parallel by the VC level, as shown by the dotted line in the figure. If we look at this between the black level and the sync tip level, we can see that this rising waveform is slightly delayed. This delay is a delay time corresponding to the parallel shifted level difference, and as is clear from the above, in the case of a VC level, the clock CP4
This is one neck period. In other words, by adding line number/(- as a level to the output data of the falling edge of the data ROM (7), it is possible to correct the error for each horizontal period. Conversely, for the level data of the rising edge, the line number is added to this value. By subtracting the data RO from the data RO
For the level data of 11 pits from M (7),
By adding or subtracting the vertical address and the address data indicating the line number of the 1O pit from the counter (3), information such as a synchronization signal in a state that matches the horizontal period of each line number, and the armpit (-) etc. is obtained. For the calculation in this calculation circuit (8), the data ROM
The output data from (7) is made into 12 bits by adding 1 pit's worth of data to the 11 pits' level data. This 1-pit additional data is information on whether to perform addition or subtraction in the arithmetic circuit (8), and as indicated by ■ in Figure 5, addition is performed on falling data. For example, power information ``0#'' is used as additional data, and information that should be subtracted from data, such as ``1'', is used as additional data for data with a rising 9 as indicated by θ in the figure. The output of the arithmetic circuit (8) is the data ROM
The 11 pit data in (7) is converted to 8 pits,
Therefore, the level is also converted to 8 pits, with the sync tip level being 78 and the black level being 156. In other words, the difference between the sync tip level and the black level is 78, the minimum value of the falling waveform is 01, and the maximum value of the rising waveform 9 is 156 + 78.
= 234. This 8-pit data is limited between the sync tip level and the black level in the waveform shaping ROM (9) as follows, the burst envelope is set to that level, and the burst envelope of frequencies f and c is A signal is superimposed on the burst envelope. That is, FIG. 8 shows a flowchart of the operation of this waveform shaping ROM (9). To explain this flowchart, step [1] is the start, and step [2] is the step of reading the 8-pit data g (g is level data) from the arithmetic circuit (8). In step [3], X is level 156
It is determined whether the If 2 is greater than 156, in step [4] all 2 are forced to 156, while in steg [3], if the frost is less than 156, go to step [5] and this step [ 5], it is determined whether 2 is smaller than level 78. When 2 is less than 78, the data is forced to level 78. Field is 7
If it is between 8 and 156, proceed to step [7]. Through the above steps [3] to [6], the nickel limiter operation is performed between the black level 156 and the sync tip level 78 (see FIG. 9A). In step [7], parse) f-) generation circuit (6
) is at a high level. Perth)? -) When the signal is not at a high level, that is, when it is not a burst period, the process proceeds to step [8], and the data π is derived as the 11 output. Perth) The fact that the f-t signal does not go high means that there is no burst signal during the horizontal period, and this indicates a tie! In the case of (2), Grave, and W, the burst period is information indicating the black level, and this is read out as is. Parse) r-) When the signal is at a high level in that horizontal period, step from step [7]

[9] K moves. and this step

In [9], an operation is performed to convert the data X of s+156 to -7-. In other words, the 20th level based on the f rack level 156 is "K"
Damn it! One burst of nine bursts of emperoso is converted into the amplitude of the pot (see Figure 9B). and this step

After [9] there is a step (103゜(
In steps 11), (12], and (13), the burst signal is added. In this case, the burst signal is added at the frequency ! from the phase shifter (4), and the signals of 2f and e. 14, based on the information on the envelope of the burst signal and K.Then, when adding this next burst signal, depending on the states of the frequency !, @ signal and the frequency 2f13 signal, as shown in Fig. 10C, Each data is assigned to the O level of the burst signal, the +1 level which is the maximum positive value, and the -1 level which is the maximum negative value.In other words, since the data arrives at a repetition frequency of 4f1, this For signals with frequencies f and e, 4 samples arrive in one cycle.Then, the signal with frequencies f and .
San! When ringing, these signals are originally synchronized, so the sangrinda phase is the frequency! ,. 0°, 900.180", 270 for the signal of
”.If you look at each point with ζ, you will get 0@ and 180'
This is because the point 90o should be the θ level of the burst signal, the point 90o should be the +1 level, and the point 270' should be the -1 level. The actual processing contents of the waveform shaping ROM (9) are as follows. That is, in step [10], it is determined whether the signal with the frequency 2flIa (FIG. 10B) is in the state of '0' or not. If the signal with the frequency 2f@e is in the state with 0, then In step [11], the data is forcibly set to a level of 156. In terms of the phase of the carrier, it is oo or 180.
1 information and is carried over to the 1560 level f librack level. After this Stella f (11), the process goes to step [8] and the data set to the level of 156 is output as is. Frequency 2 f,. When the signal of , is in the state of '1', the process proceeds to STAYfC12), and it is determined whether the state S of the signal of frequency imc (person in Figure 10) is O. Then, J
When the signal of iItlL number f is in the "ol" state, the process goes to step (13) K, and in this step [13], as is clear from FIG. 10, the burst data at this time must be at the +1 level. First, in this rounding step [13], an operation is performed to convert (312-g) to 1 (this 2 is the step

It was converted to s+156 1]-1 in [9]. ). In other words, when the data is brought to the peak level in the positive direction of the burst data, it becomes k. Frequency in step [12]! ,. When it is determined that the signal is 1, the burst data has a negative peak value of -1, as is clear from FIG. Therefore, in this case, the process goes from step [12] to step [8], and the data at that time is derived from step [11]. As mentioned above, in the waveform shaping ROM (9), the first
The protection data is added as shown in Figure DK. To summarize the above, it operates as shown in No. 111111C. That is, the data with the rise and fall times as shown in the figure is read from the data ROM (7),
This data and the line number are added or expanded/subtracted in the arithmetic circuit (8) (FIG. 1), and the waveform shaping ROM
(9) In the limiter of the synchronization signal part (C in the same figure)
, a burst envelope limiter (D in the same figure) and a burst signal addition (E in the same figure). Next, an example of a more specific configuration of the boot stock shown in FIG. 1 will be explained with reference to FIG. 12 and subsequent figures. That is, the enlarged reference signal forming circuit (1), the horizontal address counter (2), and the 11m address counter (3) shown in FIG.
, phase shift! (4), gun protrusion: I:/) CI-rule circuit (5), and parse In"-) signal generation circuit (6) are shown in detail. Reference signal type IIt circuit (1) Frequency expansion 4f1 A crystal oscillator (101) with an oscillation frequency of . and a frequency division counter (
102), the clock from the crystal oscillator (101) is used as the reference clock of the above-mentioned 0 frequency 4f□, and is divided by the counter (102) to obtain frequencies 2 fsc and f, respectively. The signal CP dropped to
False # CPl is obtained from this. Horizontal address counter (2) is a counter (201X20
2) (203) and orff -) (204) (205
X206) further has Nando f −) (207),
195'lf circuit (208X209) (210X211
). The counters (201X202) and (203) are each 4-bit counters, and the counters (2010202) use their respective 4-bit outputs, but the counters (201
03), only the lower two pits of the four bits are used, making a total of 10 bits. Horizontal address data HADD (9 bits) is stored in counters (201) (202).
) is used as its lower 8 bits,
47 in the latch circuit (210). . Latched by 0 clock. Also, the lower 1 bit of the callan p (20B) is latched by the latch circuit (209) K, which is 1
Horizontal address data HM)
) horizontal address data HADD is derived. One horizontal period is the first half of the count from 0 to 566,
It is Nan I' that performs the address calculation that is divided into the second half of 5671 from O? -) According to the output of (207). rit)
The output of the Nant gate (207) is the counter (201) (
202M203), this becomes 56.
When it reaches 567, its output goes low and the counter (201) (202X20
3) are cleared at the same time. and,
The operation to distinguish between the first half and the second half, that is, count at 566t for the first half, count at 5671 for the second half, and lower the output of NAND ff-) (207) to a low level, is performed by the iii*address kakunta described later. Since the least significant bit of is triggered by the 2f0 signal as mentioned above, the state of the signal is inverted in the first half and the second half of the horizontal period.Using this fact, OR r -) (2
04). In other words, the lowest bit of the address counter is “1”.
If it is 1, the output of ORff-) (204) is always 1. This or? - This is the information of the least significant bit of the horizontal address counter (2).
-), this means that the lowest pitch of the horizontal address information is always ``1m,'' which means that the lowest pitch of the horizontal address information is always 1m.
When 01X202) (203) counts clock CP4, the Nando Dart (207) O output goes low. On the other hand, if the least significant bit of the vertical address counter is @0'', this means that the output of this OR f -) (204) will be 10''@''1'' based on the information of the least significant bit of the horizontal address counter (2). Therefore, this counter (201
) (202) When 567 clocks CP are counted in (203), the O output falls to the low level, and thus the first half and the second half can be distinguished. Next, only in the second half of the last horizontal period of the l frame, do an operation that counts from 0 to 571, 4 more times than in the normal state.K is the 17th frame from the IITMR address kakunta (3). According to the signal obtained at the time of termination. t6 Utilizes the fact that the output Q of the D flip-flop circuit (305) constituting the vertical address counter (3), which will be described later, falls to 101 in the latter half of the final line of one frame. Is the output of the OD flip-flop circuit (305) or? -) (20G) K supplied. On the other hand, the fourth bit O information from the bottom of the horizontal address counter is supplied to the OR (r-) (206). Therefore, D7 reset circuit (305) C
) information is '1'', the output of Nando Dart (207) will have no relation to the output of this 4th bit, but
When this falls to 101 in the second half of the final line, this OR r-) (206) 0 If the 4-bit information that is the other input does not rise to IK, the NAND f-) (
207) does not fall to "0#".As a result, four extra counting operations from 0 to 5711 are performed in the second half of the last line of this one frame.Horizontal address Top pit of counter (2), 2nd bit welfare latch circuit (211) of counter (203)
This is the read control circuit (5)
period data RO for the second half of the aforementioned one horizontal period.
It is a rounded signal that forms HEMP, an axis signal for stopping reading from M (7). Also, the horizontal address counter (2) NAND r-)(
As can be seen from the above, the output of P! ■It is. This signal is latched in the latch circuit (208), and flT1i
Address counter (3) K is supplied. The vertical address counter (3) has three 4-bit counters (301X302) (303) and 7Y
l'-) (304), D flip-flop circuit (30
5), T7 lip flop circuit (306X307X30
g) and a counter (301X302
) and the lower 3 bits of the counter (303) are used as 11-pit vertical address data VADD. In this case, the upper 3 bits of the counter (301), the 4-bit information of the counter (302), and the upper 3 bits of the counter (301)
03), the tb counter (301) (302) (303) (from the D output &l
The upper 101' bits of the lk'' and O information are derived as line number information.The lowest 1 bit is the signal pa with a frequency of 2f0 from the horizontal address counter (2).
Since n is frequency-divided to 1iK1, this is a signal with a horizontal period], and this is a signal with a horizontal period.
8) as a trigger signal, and a line discrimination signal indicating whether the line is an even line or an odd line is derived from this T flip-flop circuit (30g). Counter (301) (30
2X303) O Output O Information on predetermined bits is supplied to Nando Dart (3G4), and the counter (301) (
When 302X303) counts 1249 (corresponding to the beginning of the second half of the last line of one frame), the output of Nandogoo (3G4) falls to low level. The output of this NAND f-) (304) is latched in the flip-flop circuit (305), and the counter (301M302X303) is cleared by the output. What, Nando? -), (304) falls to low level in the second half of the final frame of one frame, and the information that the output is delayed by one clock D flip 70 day path is sent to the counter (301X302).
It will be supplied to the clear terminal (303). Therefore Karan/ (301M302X303) Fil
It is cleared every frame. Counter (30
1) (302x303) will count twice the number of lines actually included in one frame, but by not using the lowest 1'1/t, it will end up counting 625 lines. . The second half of the final twin is not counted, but since it is not equally involved as the final bit line number, no problem arises. (305) (1) The output is supplied to the Teflidefrodde circuit (306) as its trigger signal. Therefore, a signal that is inverted every l frame is obtained from this T flip-flop circuit (30g), and this is used as the frame discrimination signal FID. In addition, the output of the latch circuit (20B) of the horizontal address counter is supplied to the digital fritz circuit (307), and a signal that is inverted every horizontal period is obtained.
4), and is used as a signal to form the signal HIMP in conjunction with the output of the aforementioned latch output 208). The phase shifter (4) is a D-flip 7El tube circuit (401) and an AND-OR? −)-ro (402),
In the D7 logic fwA path (401), the frequency from the reference signal forming circuit (1)! 1. Is the signal CP1 the reference number of cycles? 4f, , by the clock cP4, the phase becomes 9 with respect to the original frequency f, e signal.
01 - A delayed good signal is obtained from this. In this phase shifter (4), the line discrimination signal LID from the T7 lip flop circuit (308) is
The signal with a frequency of 2fo is further supplied as is, and is inverted and supplied through an inverter (403).
02), a signal with a frequency fSC whose phase is in its original state and a signal with a delay of 90' is alternately derived every horizontal period, and a signal with a frequency 2fme is alternately phase-inverted every horizontal period. 0
Frequency 4f. The reference signal is extracted as is. The read control circuit (5) has a ROM (501), an AND-OR f-) circuit (502), a D77 lip-flop circuit (503), and a tb latch circuit. In addition, this read control circuit (5)
f −) (5G4) and or? -) (505). The ROM (50
1), O10 bits of vertical address information from the vertical address counter (3) supplied to this, and tb
This indicates a line number, and a signal is derived from this to determine which type of the above-mentioned types (1) to (V) the horizontal period belongs to. As described above, this is divided into four types depending on the pulse width and the presence or absence of a burst signal, and these are supplied to the AND-OR-DART circuit (502) as four output signals. Furthermore, the frame discrimination signal FID from the KT Fritzoff circuit (306) is this AND-OR? -) Circuit (502)
Supplied by, from now on, the type of horizontal period! ~
Two bits of information are obtained as information indicating which one of W is the one, and this is latched into the p7 output circuit (603) and derived as outputs RC and RC. The signal HIMP is formed in the latter half of the true horizontal period and the signal that determines this type is used as information, and it is formed by using the signals that determine the type of the true horizontal period.
). Next, 1 perspective)? -) The signal generation circuit (6) is ANDf-
) (601X602) and orff-) (603) and 0
It consists of 7 lip flop circuits (604). ANDf - (601) K has the 6th and 7th bit O information of the horizontal address information supplied to its input, #-fr -) (602) KFi this ANDf
-) (601) and the output of the 8th bit of the horizontal address output are supplied, and the OR f -) (602)
The output of AND'r -) (603) t) is input, and the inverted signal of the information RC1 and RC from the readout control circuit (5) for determining types ■ to ■ is input to this AND'r -) ( 603), and by these three f-) circuits (601X802X603), when the required type among types ■ to ■, i.e. type An f-) signal indicating the position where the originally parsed )ff-) signal should be generated is generated, and this is sent to the D frizzoff circuit (604) to which the clock CP4 is supplied.
) and is used as a burst gate signal. Next, FIG. 13 shows the data ROM (η, arithmetic circuit (8)
, waveform shaping ILOM (9), and digital filter (to). Data ROM' (7) is ROM (701) (702
) and a latch circuit (703M704). The arithmetic circuit (8) consists of a latch circuit (801X802) that latches vertical address information and an arithmetic circuit (i103X8).
04) (805) (806) and latch circuit (807
)have. The waveform shaping ROM (9) consists of a BoM (901) and a latch circuit (902). The digital filter (to) is the latch circuit (1001) (1
002) (1003') and adder (1004) (10
05), and its output terminal is derived as shown in the figure. FIG. 14 is a specific example showing the parts of the D-me conversion circuit α filter and the Rono filter (6), respectively.
) is the D-large converter, (121) is the filter, (131)
is a batsaande for output extraction. As described above, according to the present invention, it is possible to digitally generate the offset for each horizontal period unique to PAL signals, and moreover, by simple subtraction or addition processing. It is very important to be able to accurately and accurately transmit signals.

[Brief explanation of the drawing]

#! IWA is a block diagram of an example of the present invention, FIGS. 2 to 11tEl are diagrams for explaining the same, and FIGS. 12 to 14 are block diagrams of a concrete example of the invention. (1) Mining standard signal type *Family, (2) is horizontal address counter, (3) is - address counter, (5) is read control circuit, (η is data ROM1 (8) is arithmetic circuit, (9 ) is a laryngeal orthopedic target. Shu Hosuke Figure 7 Figure 11 Procedural amendment June 1, 1984 Patent application No. 5zsso No. 2 Title of invention PAL television signal 3, Amendment class 6 Relationship with the synchronization signal generation circuit incident Patent applicant Representative director Kazuo Iwama 6 Number of inventions increased by amendment 7 M Correct (7) Detailed explanation column (1) Details of the invention of subject @ H4g In the book, page 29, line 7 r 2fsc J to r
Correct as 2fmt J -, -. (2) Same page, lines 18-19 if r"l"
) If the output of (2G4) is r"o", then the output of the OR gate (!04) is corrected as "" by the inverter. (3) Same, page 29, line 7, "If @0, then this" is corrected to "If it is 1, this is done by the inverter." (4) Same, page 30, line 19 [second half of one horizontal period]
is corrected to ``a period during which the horizontal address data HADD becomes data indicating that it is r512J or more''. (5) Same, page 36, line 3, insert the following after "...signal to be determined". "And the signal when the horizontal address data HADD becomes more than rs1zJ" (6) In the drawing, figure 1lIE11 is corrected as shown in the attached figure. that's all

Claims (1)

[Claims] Information on the reference signal forming circuit that generates a clock signal with a frequency four times the color law carrier frequency and the synchronization signal for one horizontal period, where the falling edge of the signal is from the black level to the sync chip level. The level of the sync chip level also has extra level information below the sync chip level, and the information on the rising part is the data from the sync tip level to the black level, which also has extra level information above the black level. data ROM that stores
, the clock signal is counted and the data ROM is
a horizontal address counter that specifies an address within a horizontal period, a vertical address counter that counts the output of this horizontal address counter and obtains line number information within one frame to five frames, an arithmetic circuit, and a waveform shaping circuit. , and a D-me conversion circuit, the data read from the data ROM within the horizontal period and the data indicating the line number are added in the arithmetic circuit for the falling edge, and are added for the falling edge. Above) A subtraction operation is performed on K, and the output data is limited to a level between the black level and the sync chip level in the waveform shaping circuit and output *b.
A synchronization signal generation circuit for a PAL television signal, which is converted back into an analog signal by the D-A conversion circuit.