JPS5816789B2 - Signal discrimination circuit for automatic channel selection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal discrimination circuit suitable for a television receiver equipped with an automatic channel selection device that automatically performs channel selection operations.

In general, in television receivers, tuning is often done by rotating the channel heir, but especially when using continuously variable tuning like when selecting a UHF channel, the tuning operation is cumbersome and cumbersome. Ta.

In addition, in the case of television receivers equipped with touch-type or remote-control type tuning devices, the tuning operation when changing channels is easy, but the preset tuning operation at the time of initial installation is still troublesome and requires inexperienced amateurs. It was difficult.

Therefore, automatic tuning devices that automatically perform such tuning operations have been proposed in the past, but the present invention relates to a signal discrimination circuit used in such automatic tuning devices, and relates to a signal discriminating circuit that is used in such automatic tuning devices, and In order to reliably receive a television signal that arrives mixed with noise, a circuit is provided that determines whether a received signal is a regular television signal or not.

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings, but first an automatic channel selection device in which a signal discrimination device according to the present invention is used will be described.

FIG. 1 is a block diagram showing an example of a television receiver having an automatic channel selection device, where 1 is an antenna, 2 is a tuner, 3 is an intermediate frequency circuit, 4 is an AFT circuit, and 5 is a video circuit, 6 is a synchronous separation circuit, 7 is a deflection circuit, 8
is a picture tube, and these constitute a normal television receiver.

Here, a start/stop circuit 9, a tuning voltage generating circuit 10, a memory circuit 11, and a signal discriminating circuit 12 according to the present invention are added to these to constitute an automatic tuning device.

When a search start command (automatic tuning command) is given to the start/stop circuit 9 during preset tuning, a search start pulse is generated from the circuit 9 and supplied to the tuning voltage generation circuit 10.

At this time, the tuning voltage generating circuit 10 generates a sweep voltage that gradually increases or decreases, and this is supplied as a tuning voltage to the tuning diode of the tuner 2 via the memory circuit 11.

Therefore, at this time, the receiving frequency at the tuner 2 is gradually changed.

When the television radio waves of the channel of the current broadcasting station are received in this way, a television video signal is derived from the intermediate frequency circuit 3, and along with this, a synchronization signal is derived from the synchronization separation circuit 6 and is supplied to the start/stop circuit 9. be done.

On the other hand, the AFT detection output from the AFT circuit 4 is also supplied to the start/stop circuit 9.

In particular, since the polarity of the AFT detection output voltage changes when the television radio wave is precisely received, this time is detected and the search stop pulse and vertical synchronization signal are generated from the start/stop circuit 9.

Here, the vertical synchronization signal also serves as a search stop pulse.

The search stop pulse is supplied to the tuning voltage generation circuit 10, and accordingly, the sweep wave generation operation is stopped in the generation circuit 10. From then on, this instantaneous voltage is held, and this is used as the tuning voltage via the memory circuit 11. The signal is supplied to tuner 2.

On the other hand, at this time, the vertical synchronizing signal derived from the start/stop circuit 9 is supplied to a signal discrimination circuit 12, where it is discriminated whether or not the signal is a regular television signal.

When it is determined that this is a regular signal, a memory command is derived from the signal discrimination circuit 12, and the command is supplied to the memory circuit 11, whereby the memory circuit 11 receives the tuning signal supplied from the tuning voltage generation circuit 10. The voltage is memorized.

However, when the pseudo synchronization signal is derived from the start/stop circuit 9, it is detected by the signal discrimination circuit 12, and the circuit 12 generates a re-search start pulse.

This pulse is supplied to the start/stop circuit 9, whereby the same operation as when the above-mentioned first search start command was given is repeated again.

In this way, the same operation is repeated until a regular television vertical synchronization signal is derived from the start/stop circuit 9, that is, until correct reception is performed by the tuner 2, and only when the reception state of a certain channel is accurately achieved is the signal received. A memory command is issued from the discrimination circuit 12, the tuning voltage at this moment is stored in the memory circuit 11, and thereafter this memory voltage is supplied from the memory circuit 11 to the tuner 2.

Note that once the preset tuning operation for a specific channel as described above is performed, if a channel selection instruction is given to this memory circuit 11 by touch or remote control during normal channel selection, the memory circuit 11 The memory voltage is supplied to the tuner 2 as a tuning voltage, and this channel is selectively received.

Although only one memory circuit 11 is shown here, in reality, similar memory circuits are provided for the number of pre-sent stations, and the pre-sent operation (automatic channel selection operation) of the tuning voltage stored in each memory circuit is already performed. This is performed by the same operation as described above.

The present invention relates to a signal discriminating circuit 12 used in the automatic channel selection device as described above, and one embodiment thereof is shown in FIG.

The operation of this circuit will be explained next. When a radio wave from an arbitrary broadcasting station is received and a vertical synchronizing signal is supplied from the input terminal 13 to the cent input terminal S of the R-S flip-flop 14, the output terminal Q of the Noritubflock 14 becomes "'H".
" state, and this "H" output is supplied to one input terminal of AND gates 15 and 16, so a vertical synchronizing signal appears from AND gate 15, and a clock pulse is generated from AND gate 16. The clock pulses generated in the device 11 are exposed.

That is, when a vertical synchronizing signal arrives, AND gates 15 and 16 are opened simultaneously, the synchronizing signal from AND gate 15 is supplied to frequency divider 18, and the clock pulse passing through AND gate 16 is supplied to divider 19. Ru.

Here, if the frequency division ratio of the frequency divider 18 is m11/m and the division ratio of the other divider 190 is 1/n, then the frequency divider 18
A signal with a pulse width of Tlm is derived from the frequency divider 19, and a signal with a pulse width of T2n is derived from the frequency divider 19.

However, here, T1 is the period of the vertical synchronization signal (T□-16
, 7m5ec), and T2 is the period of the clock pulse, which is particularly set to Tlm minus T2n.

In other words, the frequency divider 18 is set to finish counting the synchronization signals earlier than the clock pulse counting by the divider 19 (and when the frequency divider 18 finishes counting the clock pulses, the output of the frequency divider 18 is applied to the monostable multivibrator 20, and at this time, the multivibrator 20 is driven and a signal having an arbitrary pulse width is derived to the output terminal 21.

This signal means that a regular vertical synchronizing signal is supplied to the input terminal 13, and is led to the memory circuit 11 described above as a memory command signal.

This signal is also applied to each reset terminal of the flip-flop 14 and the dividers 18 and 19 through the ORKATE 22, and the reset signal causes the clock pulse counting output to appear in the frequency divider 19 and remains in the "L" state.

Therefore, at this time, the monostable multivibrator 23 is not driven and no output appears at the output terminal 24.

However, if the number of synchronization signals is insufficient for some reason,
The number of synchronization signals input to the branching unit 18 is less than m,
Since the counting time of the divider 18 is longer than the dividing time of the frequency divider 19, the output of the frequency divider 19 appears earlier,
Added to monostable multibibreak 23.

As a result, a signal having an arbitrary pulse width is derived at the output terminal 24.

This signal means that no regular synchronization signal was supplied to the input terminal 13, and is supplied to the start/stop circuit 9 described above as a re-search start signal.

This signal is also supplied to each reset terminal of the flip-flop 14 and the branchers 18 and 19 through the OR gate 22, and the Q output of the flip-flop 14 becomes the "L)l state."

Therefore, the AND gates 15 and 16 are closed and the frequency divider 18
, 19 are stopped.

When a vertical synchronizing signal is supplied to the input terminal 13 in this state, the Q output of the flip-flop 14 becomes "H91" again.
state, and the same operation as described above is repeated.

When a regular television vertical synchronization signal is supplied to the input terminal 13 through the above operation, one of the output terminals 21
A pulse signal is derived from the other output terminal 24, and when the synchronization signal is not a regular signal but a pseudo signal, a pulse signal is derived from the other output terminal 24.

In addition, in the embodiment shown in FIG. 2 above, if the division ratio of the divider 18 1 190 is set to, for example, 2, and the clock pulse period of the clock pulse generator 17 is 1 m5ec, then the output pulse derived from the divider 18 is Width is 0.0
167X30=0.501 sec, and the pulse width of the output derived from the divider 19 is 0.001X60
0=0.6 sec, and when a regular vertical synchronization signal arrives, the monostable multivibrator 20 is driven first,
A pulse signal will be derived to the output terminal 21.

According to the signal discrimination circuit of this embodiment, as described above, the television synchronization signal derived at the time of automatic channel selection is counted in one frequency divider, while the reference clock pulse signal is counted in another division divider. and compare the counting outputs of both,
It detects which counting ends first, that is, which output is derived first, and determines whether or not there is a predetermined number of synchronization signals within a certain period of time, and determines whether or not it is a regular television signal. This is to determine the

Therefore, if such a signal recognition method is used in an automatic tuning device, it will not malfunction due to various interference radio waves and noise.
Regular television signals can be reliably received.

Note that in the embodiments described above, a vertical synchronization signal is specifically used as the synchronization signal, but of course a horizontal synchronization signal may also be used, or a color subcarrier or an audio carrier may also be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an automatic channel selection device, and FIG. 2 is a block diagram of an embodiment of a signal discrimination circuit according to the present invention. 1...Antenna, 2...Tuner, 3
...Intermediate frequency circuit, 4...AFT circuit, 5...Video circuit, 6...Synchronization separation circuit, 7...Deflection circuit , 8... picture tube,
9...Start/stop circuit, 10...
...Synchronous voltage generation circuit, 11...Memory circuit, 12...Signal discrimination circuit, 14...R
-S flip flop, 17... Clock pulse generator, 18° 19... Frequency divider, 20, 23
...Monostable multi-by-break.

Claims (1)

[Scope of Claims] 1. A first counting means for counting synchronization signals, a clock pulse generation means for generating a reference clock pulse, and a second counting means for counting the clock pulses generated by the means; A signal discriminating circuit for an automatic channel selection device, comprising determining means for detecting which count output of the first and second counting means is derived first and determining whether or not the synchronization signal is a regular synchronization signal. 2. A signal discrimination circuit for a patented channel selection device, characterized in that a vertical synchronization signal is used as the synchronization signal. 3. The signal code of the automatic tuning device according to claim 1, characterized in that a horizontal synchronization signal is used as the synchronization signal.