JPH0748836B2 - Television receiver - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a television receiver that discriminates between television broadcasts of different systems and switches to a reception mode adapted to each system.

(Prior Art) In satellite television broadcasting, for example, NTSC system and MUSE
When broadcasting signals of different systems such as the systems, the receiver needs a receiving system adapted to the two systems as shown in FIG.

The satellite broadcast wave transmitted in the SHF band is converted into a GHz band first intermediate frequency signal by the first frequency converter and supplied to the input terminal 10. This input signal is converted into a second intermediate frequency signal by a second frequency converter (not shown).
The second intermediate frequency is supplied to the FM demodulator 11 and converted to baseband.

When the NTSC signal is received, the demodulated signal is supplied to the video signal processing system and the audio signal processing system. In the video signal processing system, the audio signal is removed by the audio trap circuit 12, the emphasis process is performed by the de-emphasis circuit 13, and the dispersal removal circuit 14 is further processed by clamping or the like to obtain an NTSC composite signal. On the other hand, in the audio signal processing system, the QPSK demodulator 15 performs 4-phase phase demodulation, the PCM decoder 16 obtains a 2-channel or 4-channel digital audio signal, and the digital-analog (D / A) converter 17 further obtains this. I am trying to obtain an audio signal by analog conversion.

On the other hand, when a MUSE system signal is received, the demodulation output of the FM demodulator 11 is introduced via the buffer amplifier 18 to the MUSE decoder 21, which is a dedicated signal processing device provided in the subsequent stage, where the video and Audio reproduction processing is performed.

In the figure, a block 100 surrounded by a broken line is known as a BS tuner, and a block 200 surrounded by a broken line is a signal processing and switching unit, which decodes a baseband signal and outputs an output conforming to a received signal system. It is selected and supplied to the video monitor 300 and the speaker 400.

The signal processing and switching unit 200 has an NTSC decoder 20 for decoding an NTSC composite signal and a MUSE decoder 21 for decoding a MUSE baseband signal. NT
The output of the SC decoder 20 is supplied to the terminal 2a of the switch 22, and the output of the MUSE decoder 21 is supplied to the terminal 2b of the switch 23. The signal selected by the switch 22 is
Supplied to 0. The output from the digital-analog converter 17 is supplied to the terminal 3a of the switch 23, and the MU is connected to the terminal 3b.
The output from the SE decoder 21 is supplied. The signal selected by the switch 23 is supplied to the speaker 400.

The switches 22 and 23 are switched according to the broadcasting system to be received, and are normally switched manually by the user.

(Problem to be Solved by the Invention) According to the conventional receiving system, the switches 22 and 23 are manually switched according to the broadcasting system to switch the receiving mode. However, even if the same reception channel is used, a problem arises when the operation is performed such that the broadcasting system is switched midway. For example, in the NTSC system reception status, if the reception status temporarily deteriorates, the screen will be disturbed,
Similar screen mess occurs even when the broadcasting system is switched to the MUSE system on the way. Therefore, it is difficult for the viewer to determine whether the deterioration of the reception state is the cause or the switching of the broadcasting system is the cause.

Therefore, an object of the present invention is to provide a television receiver capable of automatically switching the signal processing mode of the receiver according to the broadcasting system being received, and the switching thereof being stable. .

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to a television receiver for receiving two or more television broadcast signals composed of different synchronization systems.
A plurality of signal processing circuits supplied with the received signals and corresponding to signals of respective broadcasting systems, switching means for switching and selecting one of outputs of the plurality of signal processing circuits based on a control signal, and the plurality of signal processing circuits. The presence / absence of a synchronization signal corresponding to the broadcasting system of each signal is detected using the signals processed by the circuit, and a plurality of detection signals (A, B), and the detection signal (A,
Only when the state of B) has a predetermined relationship and continues for a predetermined period, the output corresponding to this relationship is obtained and the switching control signal of the switching means is generated. When there is no continuation for a predetermined period, the switching means is provided with a judging means for holding the previous selection state.

(Operation) By the above means, for example, when two detection outputs A and B are the same for a predetermined period consecutively, and one of A and B is "1" and the other is "0", the detection is performed. Switching is performed based on the output, and in other states (detection outputs A and B are not the same value for a predetermined number of times continuously, or both A and B are “0,
When it is 0 "or" 1,1 "), switching is not performed and the previous state is retained. Therefore, when the reception state is unstable,
It is possible to prevent unnecessary switching when the broadcasting system is unstable immediately after switching.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The difference from the circuit shown in FIG. 7 is that sync detection circuits 51 and 52 are connected to an NTSC decoder 20 and a MUSE decoder 21, respectively. The outputs of the synchronization detection circuits 51 and 52 are supplied to the determination circuit 53, and the output of the determination circuit 53 controls the switch 54. Therefore, the other parts are the same as those in FIG.

If the received signal is an NTSC format signal, BS tuner 10
From 0, NTSC composite signal and NTSC audio signal can be obtained. Therefore, the synchronization detection circuit 51 connected to the NTSC decoder 20 outputs the output A (= 1) indicating that it is in the synchronization state.
Is output. On the other hand, the synchronization detection circuit 52 connected to the MUSE decoder 21 outputs the output B (= 0) indicating that it is in the asynchronous state.

The judgment circuit 53 judges the states of the inputs A and B and obtains the judgment output C. Judgment output is C = 1 when NTSC, C = MUSE
It is "0". As a result, the switches 55, 5 of the switch unit 54
6 is controlled. Switch 55 is for video signal selection,
The switch 56 is for audio signal selection.

When the judgment output C is "1", the switches 55 and 56 select the terminals 5a and 6a, respectively, and when the judgment output C is "0", the switches 55 and 56 select the terminals 5b and 6b, respectively.

Further, the output C of the determination circuit 53 is also used as a control signal for the horizontal synchronization switching circuit 301 and the aspect ratio switching circuit 302 of the video monitor 300. This is because the horizontal sync frequency and aspect ratio differ between the NTSC system and the MUSE system.

As described above, by detecting the presence or absence of the synchronization signal, it is possible to determine whether the received signal is based on the NTSC system or the MUSE system, and automatically switch the output signal.

FIG. 2 shows a concrete example of the synchronization detection circuit 51 or 52.
An analog input signal from the input terminal 60 is converted into a digital signal by the analog-digital converter 61. The digital signal is supplied to the clock recovery circuit 62. The clock recovery circuit 62 recovers the system clock from the input digital signal. For example, a video signal includes a synchronization signal such as a reference burst signal, and a phase locked loop is used to create a system clock synchronized with the synchronization signal. At this time, the phase error between the internally generated system clock and the input reference signal is detected, and the phase of the internal clock is controlled according to the error.However, if the input analog signal is not normal, a large error output is obtained. If the input analog signal is normal, the error output is small. By monitoring the error output, it is possible to determine whether or not the recovered clock is in the synchronous state, and the error output is supplied to the asynchronous detection circuit 63. The output of this asynchronous detection circuit 63 is
It is used as the output A or B described above.

FIG. 3 shows still another embodiment of the synchronization detection circuit 51 or 52.

The input analog signal is supplied to the analog-digital converter 72 via the terminal 71 and is supplied as a digital signal. The digital signal is supplied to the clock recovery circuit 73 and the sync separation circuit 74. The clock regenerating circuit 73 regenerates the system clock similarly to the circuit of FIG. The system clock is
In the frequency divider 75, the frequency is divided into, for example, the same frequency as the horizontal synchronizing signal, and the frequency division output is supplied to the phase comparator 76. The phase comparator 76 compares the phase of the horizontal sync signal from the sync separation circuit 74 and the frequency-divided output, and if the phase error is within a certain range, outputs a pulse from the terminal 76a and outputs the pulse outside the certain range. For example, a pulse is output from terminal 76b. Phase comparator 7
The 6 output pulses are supplied to the counter 77. Comparator 76
Is reset when a pulse is input from the terminal 76b, and counts the pulse from the terminal 76a. And counter 76
Outputs the output A or B when the count value becomes a constant value. Therefore, according to this synchronization detection circuit, since the output is obtained only when the horizontal synchronization signal is continuously obtained for a certain period, the probability of malfunction due to noise or the like is small.

FIG. 4 shows a specific example of the determination circuit 53. The output A of the synchronization detection circuit 51 is supplied to one terminal of the monostable multivibrator 82 and the NAND circuit 83 via the terminal 81. The output of the monostable multivibrator 82 is the NAND circuit 83.
Is supplied to the other input terminal. Further, the output B of the synchronization detection circuit 52 is supplied to the monostable multivibrator 85 via the terminal 84.
And to one terminal of the NAND circuit 86. The output of the monostable multivibrator 85 is supplied to the other terminal of the AND circuit 86. AND circuit 83
Is supplied to the set terminal of the flip-flop circuit 87, and the output of the AND circuit 86 is supplied to the reset terminal.

If A is at a high level (NTSC reception),
A pulse is obtained from the NAND circuit 83 and a flip-prop circuit is obtained.
87 is set and the output C becomes "1". Conversely, when B is at a high level (MUSE reception), a pulse is obtained from the NAND circuit 84, the flip-flop circuit 87 is reset, and the output C becomes "0".

FIG. 5 is a timing chart of the above circuit, and t shown in the drawing is a time constant of the monostable multivibrators 82 and 85. If the time constant period A or B continues to be at the high level, the determination result can be obtained accurately. When the level of A or B is indefinite, the flip-flop circuit 87 maintains the previous state and unnecessary switching is prevented.

The above judgment function can also be realized by a microprocessor programmed according to the flowchart shown in FIG. First, the output C is set to "1" (steps S1 and S2), and in step S3, A and B are read n times (for example, in the horizontal cycle) and the level is determined. Then, for n times, it is determined whether A and B are continuously at the same level. When A and B are at the same level, it is determined whether A = “1” and B = “0”. If this holds, it means that the signal of the NTSC system has been received, the output C = "1" is set, and the process returns to step S3. On the contrary, if A = "0" and B = "1", this is judged in step S7, the output C = "0" is set, and the process returns to step S3. If the conditions of steps S5 and S7 are not satisfied, the process returns to step S3. Even in this case, when both A and B are "0" or indefinite, the determination output remains in the output state before that, and unnecessary switching operation can be prevented.

[Effects of the Invention] As described above, according to the present invention, the processing mode of the signal processing circuit can be automatically switched according to the broadcast system of the received signal, so that signal processing according to the received signal is always performed. It is possible to do it, and not wait for the user's judgment.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing an example of the synchronization detection circuit of FIG. 1, and FIG. 4 is an example of the determination circuit of FIG. FIG. 5, FIG. 5 is a timing chart shown for explaining the operation of the circuit of FIG. 4, FIG. 6 is a flow chart showing another embodiment of the determination circuit, and FIG. 7 is a conventional satellite broadcast receiver. It is a structure explanatory view. 100 …… BS tuner, 20 …… NTSC decoder, 21 …… MUSE
Decoder, 51, 52 ... Sync detection circuit, 53 ... Judgment circuit,
54 …… Switch section, 300 …… Video monitor, 400 …… Speaker.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yu Sakurai 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa, Ltd. Home Appliances Technology Laboratory, Toshiba Corporation Yokohama Works (56) Reference JP-A-58-66474 (JP, A) ) JP-A-62-77769 (JP, A) JP-A-53-135513 (JP, A) JP-A-60-248082 (JP, A)

Claims (2)

[Claims] 1. A television receiver for receiving two or more television broadcast signals having different synchronization systems, wherein a plurality of signal processing circuits are provided to which received signals are supplied and which correspond to signals of respective broadcasting systems, A switching means for switching and selecting one of the outputs of the plurality of signal processing circuits based on a control signal, and a synchronization signal corresponding to the broadcasting system of each signal by using the signals respectively processed by the plurality of signal processing circuits. Detecting means for detecting the presence or absence of each of the broadcasting systems and obtaining a plurality of detection signals (A, B) representing the presence or absence of the synchronization signal of each broadcasting system in binary, and the state of the detection signals (A, B) from the detecting means. Is a predetermined relationship and only when it continues for a predetermined period, an output corresponding to this relationship is obtained to generate the switching control signal of the switching means. The television receiver, further comprising: a determination unit that causes the switching unit to retain the previous selection state when there is no continuation for a predetermined period. 2. The detecting means detects the presence or absence of the synchronizing signal by detecting whether or not a system clock reproducing circuit required for performing digital signal processing is synchronized with an input signal. The television receiver according to claim 1, wherein: