JPS58166386A - Multiscreen display method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Technical field of invention.

The present invention relates to a multi-screen display method for a cathode ray tube (CRT).

Background of the Technology CRTs are widely used in display terminals such as personal computers. In other words, data entered from the keyboard is displayed on a display for the operator to visually check for errors, and the display also displays processing results to notify the operator.
T is often adopted.

By the way, as the functions of personal computers became more sophisticated and began to process multiple types of tasks simultaneously, CRT
It becomes necessary to display multiple types of tasks simultaneously on the screen of the user, that is, to make the screen multi-screen.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a method that can perform multi-screening simply, appropriately, and easily, and can efficiently perform cell task processing.

The structure of the invention, that is, the multi-screen display method of the present invention is provided with a division ratio memory that generates an output for dividing the CR7 screen, and also prepares a screen memory for one screen for each task, so that the standard state is determined by the contents of the division ratio memory. The present invention is characterized in that a portion of the image is displayed in each section of the CRT screen, which is equally divided, and the size of the section is changed by changing the contents of the division ratio memory.

Examples of the invention This will be explained in detail below with reference to Examples.

As shown in FIG. 1 <a), in the present invention, the CRT tube surface (screen) is divided into four parts A, B, C, and D, and these are used as the basic state. The display method of this CRT is Rusk scan type.
Count clocks with a counter and D/A the counted value
The converted output becomes a horizontal deflection control signal for the electron beam, and the overflow pulse of the counter is counted by a second counter, and the D/A converted output of the counted value becomes a vertical deflection control signal.

In this example, the number of dots on the elm of the screen (corresponding to each count of the first counter) is 640, and the number of vertical dots (corresponding to each count of the second counter) is 640.
In the case of a color of 200, the 6-category AND with three elements R, G, and B as one dot corresponds to each task, and task 1 is displayed in category A, task 2 is displayed in category B, and so on. These divisions can be enlarged by pressing keys on the keyboard. Figure 1(b) shows the group of push buttons, 10°12
．． 14 and 16 are for enlarging sections A, B, C, and D, and 18 is for returning to the basic state shown in FIG. 1(a). Figure 1(c)
shows the screen situation when push button lO is pressed, where section A has expanded both vertically and horizontally, and sections B, C, and D have been eclipsed accordingly. Fig. 1(d) shows the presser opening 14 in the state of (c).
Shows the screen status at the moment of pressing, that is, push buttons 10 to 16
When pressed, it is reset to the initial state and then enlarged.
The magnification rate is proportional to the pressing time.

This kind of display is performed as follows in Ipchi task 1.
~4, the full size of the CRT tube is 640 in this example.
A screen memory for X400 is provided, and a mask is applied so that only 174 of them are displayed in the basic state. When expanding the display sections A to D by pressing a button, the mask is enlarged.The task whose 0 display section has been enlarged is the one that is being prioritized at that time, so the weight of this task is increased.The hardware that performs this operation is Shown in Figure 2.

In Figure 2, 22.24.26.28 are tasks A, B, and C.
, D, that is, the above-mentioned screen memory.

Reference numeral 30 denotes a memory for storing the screen division ratio, and outputs S1.30 in synchronization with the scanning of the CRT indicate which output from the memories 22 to 28 is to be adopted for the current scanning. Since the 0 screen that generates S2 is divided into four parts, the number of bits of the signal required to indicate each division is 2, and the binary 2-bit signal Go, 01.
Let 10°11 be the selection signal for the memory 22, 24, 26, 28. 32 is a video selection circuit that performs this memory selection, and this output signal S3 becomes a video output used for brightness control of the CRT. The II-plane memories 22 to 2B are read out in 1-byte units.

FIG. 3 is an explanatory diagram of the memory access section, where 64 is a clock generator, 66 is a first counter that counts this and generates a horizontal deflection control signal, and 68 is a first counter that counts overflow pulses of counter 66 and generates a vertical deflection control signal. A second counter that generates a deflection control signal. The count values of these counters also serve as address signals for the screen memories 22 to 28 and the division ratio memory 30. The memories 22 to 28 are sequentially output one byte at a time, and the one byte output is loaded all at once into the shift register 70, shifted at the clock of clock generation [164], and becomes the video output S3. S4 is a load signal.

The address signal terminals of each memory 24 to 2B are connected in parallel and commonly receive the output of the counter 66.6B, but the output of the stored contents is the H (high) level and L (low) level of the signal input to the enable terminal. The 0 division ratio memory 30, which is controlled by the level and outputs only one memory at a time, also receives an address signal from the counter 66.6B, but since it can be in units of 1 byte, the remainder after removing the lower 3 bits of the counter 66 is sufficient. The capacity of this memory 30 is (64048)×4
It is 00X2 bits. The 2-bit output 81.32 read for each access is decoded by the decoder 72 and
The output selects one of the memories 22, 24, 26, and 28.

Returning to FIG. 2 again, writing to the division ratio memory 30 is performed by the output of the combinator through the multiplexer 34, and the signal S5 indicates the write address and data from the CPU. In the standard state, the data to the division ratio memory 30 is as shown in FIG. (
In a), 40×20 sets of 00, 01, 10, and 11 are written to the area corresponding to section A, the area corresponding to section B, the area corresponding to section C, and the area corresponding to section C, respectively. When push button 10 is pressed, the CPU resets to this standard state, and then changes to 00 rows in the vertical and horizontal directions as the push button continues for 1, 2, 3... clock cycles (this clock is different from the one for scanning). , increase the column by 1.2.3... rows and columns (rewrite 10.11 to 00 in the adjacent B-D section), when push button 12.14.16 is pressed This also applies. When reading from memory 30, multiplexer 34 is switched to scan address generation circuit (counter 66.6B) 36 side, reading is performed in synchronization with scanning of memories 22-28 and CRT, and selection signal S1.32 is generated.

The circuit group 50 changes the weight of the task and sends the selection signal 31.
．． 32 decoders 38, and an integrating circuit 42 for each system of tasks 1 to 4. 44. 46.48, one-shit four-piece multivibrator 52°54.56.58, and an or gate 62. One Sit Multi 52~5
8, the output pulse width is changed by the output voltage of the integrating circuits 42 to 48, and the rising edge of each output becomes the task switching interrupt signal S6 through the OR gate 62, and the falling edge of the output outputs the next one-sit multi signal. trigger.

The selection signals Sl and S2 remain unchanged during the first half and second half of each horizontal scanning line, and the decoder 38 selects the first half and the second half of each horizontal scanning line.
Integrating circuits 42 (or 46), 44 (or 48) during the second half period
) to perform time integration over the period. Therefore, the output of each integrating circuit 42.44°46.48 is divided into sections A, B,
The output determines the time length allocated to tasks 1 to 4, which is proportional to the width of C and D. However, each of sections A to D can be expanded to occupy the entire screen of the CRT, so A
If you expand it to the full screen, B, C, and D will be zero, but
The minimum amount of time allocated to each task is not zero, because as long as the tasks operate in parallel, the allocated time cannot be zero. one sit multi 5
2 to 58 are adjusted between the minimum pulse width as Wl and the maximum pulse width as W2 by the output of the integrating circuit. If one of the integrating circuit outputs increases, the other decreases, so the sum of the output pulse widths of the one-shot multi-pulses 52 to 58, and therefore the sum of the times allocated to each task, is constant.

However, due to the one-shot multi operation, the processing time of each task is not synchronized with the scanning of the CRT, and the initial start is performed by the trigger signal TG generated when the power is turned on, and thereafter, the triggers are sequentially triggered in a closed loop as shown in the figure. , self-propelled.

As described in detail, in the present invention, a division ratio memory is provided to divide the screen of a CRT, and a screen memory with a capacity for one screen is prepared for each task, and the contents of the division ratio memory are standardized. In the state, each of those 174 is displayed as 4 on the CR7 screen.
The screen is displayed in each divided section, and each section can be enlarged by changing the contents of the division ratio memory by operating the push button corresponding to each section, so the desired section on the CR7 screen can be enlarged with simple and easy operations. For example, the data currently being input can be viewed in detail.
It can be made reliably visible. As the divisions are expanded, the time allocated to each task can be changed, thereby making it possible to appropriately perform multi-task processing.

Of course, the number of divisions is not limited to four, but can be arbitrary, but each task of multitasking can include data input from the keyboard,
There are many ways to print out, load files, create lists, etc., and if the number of divisions is too large, the display surface will become too small, so it is appropriate to divide it into four.

Furthermore, in the present invention, one type of scrolling can be performed by operating each push button, and a virtual screen of 1280 x 800 dots can be assumed, which is the sum of four 640 x 400 dot screen memories of each task.

In addition, in the present invention, if the display is set to the standard state and the output of the address counters 66 and 68 is input to the memories 22 to 28 with a shift of 1 point to the right, only odd addresses in the memory will be accessed and the number of read data will be halved. It is also possible to simultaneously display the contents of the entire screen memory for tasks 1 to 4 on the CRT screen, although the display will be rough. In the embodiment, pressing a button enlarges the corresponding display section, but it is also possible to change this so that the display section is decreased (other sections are enlarged).

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the display method of the present invention, FIG. 2 is a block diagram showing the road side where the present invention is implemented, and FIG. 3 is a block diagram showing details of a part of FIG. 2. In the drawing, numerals A, B, C, and D are each section of the CRTg surface divided into four, 30 is a division ratio memory, and 10, 12, 14, and 16 are push buttons for changing the size of each section. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] +1) A division ratio memory that generates an output for dividing the CRTli screen is provided, and a screen memory for one screen is prepared for each task, and the contents of the division ratio memory are used to divide one screen in a standard state. A multi-screen display method characterized by displaying the image on each section of a CR7 screen divided into equal parts, and further changing the size of the section by changing the contents of the division ratio memory. (2) The multi-screen display method according to claim 1, characterized in that the processing weight of the corresponding task is changed according to the area ratio of the section of the CR7 screen.