JPS5816549A - Housing for semiconductor device - Google Patents
Housing for semiconductor deviceInfo
- Publication number
- JPS5816549A JPS5816549A JP11557281A JP11557281A JPS5816549A JP S5816549 A JPS5816549 A JP S5816549A JP 11557281 A JP11557281 A JP 11557281A JP 11557281 A JP11557281 A JP 11557281A JP S5816549 A JPS5816549 A JP S5816549A
- Authority
- JP
- Japan
- Prior art keywords
- housing
- semiconductor device
- package
- leads
- static charges
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の容器(以下パッケージと呼ぶ)の
表面に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surface of a container (hereinafter referred to as a package) for a semiconductor device.
パッケージは半導体装置(以下半導体チップ)上に形成
された電極を外部に取り出す外部端子(以下リードと呼
ぶ)とリード間を電気的に絶縁する材料によって構成さ
れ、チップを外部環境から遮断している。The package consists of external terminals (hereinafter referred to as leads) that take out the electrodes formed on the semiconductor device (hereinafter referred to as the semiconductor chip) to the outside, and a material that electrically insulates between the leads, thereby isolating the chip from the external environment. .
パッケージ材料としては通常金属、セラ虐ツク。The packaging material is usually metal or ceramic.
ガラス、あるいはプラスチック樹脂が用いられる。Glass or plastic resin is used.
金属パッケージの場合、リード間はガラスにより絶縁さ
れている。In the case of a metal package, the leads are insulated by glass.
セラ之ツタ、ガラス、プラスチック樹脂の場合、リード
を除くパッケージ外側表面は絶縁材料で構成されている
。これら材料を選ぶ重要な要素は、リード間の電気的絶
縁性である。一方パッケージは、パッケージの外部環境
、即ち空気あるいはパッケージを収容する容器(以下ケ
ースと呼ぶ)との接触、摩擦等により、パッケージ表面
に静電気を誘起する。パッケージ材料が高絶縁性であれ
ばあるほど、静電荷は斂電消失し離<、高電圧になる。In the case of ceramic ivy, glass, and plastic resin, the outer surface of the package, excluding the leads, is made of insulating material. An important factor in selecting these materials is electrical insulation between the leads. On the other hand, a package induces static electricity on the surface of the package due to contact with the external environment of the package, that is, air, or contact with a container (hereinafter referred to as a case) housing the package, friction, or the like. The more insulating the package material is, the more the static charge will be dissipated and the higher the voltage will be.
半導体装置において、とりわけMO8半導体装置では素
子が極めて薄い絶縁層で形成されており、前記静電気に
より発生する高電圧は素子を破壊させる原因となる。通
常この故障を避けるため、チ、プ上では静電保護回路が
設けられると同時に、装置を収納するケースの材料も導
電性材料が選ばれる。例えばMO8半導体装置の場合、
静電破壊耐圧は200〜300vである。In semiconductor devices, especially MO8 semiconductor devices, the elements are formed of extremely thin insulating layers, and the high voltage generated by the static electricity causes destruction of the elements. To avoid this failure, an electrostatic protection circuit is usually installed on the chip, and at the same time, a conductive material is selected for the case that houses the device. For example, in the case of MO8 semiconductor device,
The electrostatic breakdown voltage is 200 to 300v.
パッケージ材料のうち、セラミックの抵抗は1014g
・儲以上の固有抵抗をもち、エポキシ樹脂、シリコン樹
脂では10〜10 Ω・国である。Among the package materials, the resistance of ceramic is 1014g.
・It has a specific resistance that is higher than the average value, and is 10 to 10 Ω for epoxy resin and silicone resin.
パッケージ材料は絶縁性を向上させるため、あるいはチ
ップを不純物から保護するため、抵抗値は大きくなる傾
向にある。特に固有抵抗が1011を越すと、半導体装
置の取扱かいに際して、空気との摩擦あるいはケース、
あるいはその他の装置との摩擦により容易に数千Vの静
電気を発生する。Package materials tend to have higher resistance values to improve insulation or protect chips from impurities. In particular, if the resistivity exceeds 1011, it may cause friction with the air or damage to the case when handling the semiconductor device.
Otherwise, static electricity of several thousand volts can easily be generated due to friction with other devices.
パッケージと摩擦する相手が金属の場合は絶縁体の場合
より低電圧に保てるものの、300〜1000Vの電圧
になる。If the material that rubs against the package is metal, the voltage can be kept lower than if it is an insulator, but the voltage will be 300 to 1000V.
本発明はこの欠陥を除ぞくため、パッケージ表面のリー
ドの周辺を除いた領域に導電性処理を施こすことによっ
てパッケージ表面に誘起する静電荷をおさえようとする
ものである。In order to eliminate this defect, the present invention attempts to suppress static charges induced on the package surface by applying conductive treatment to the area of the package surface other than the area around the leads.
パッケージ表面を導電性処理することによって空気との
摩擦あるいはケースあるいは他の装置とのJ11線によ
って発生する静電荷はパッケージ表面の放電経路を経て
容易にリークし、チャージアップしない。By conducting conductive treatment on the package surface, static charges generated by friction with air or J11 wires with the case or other devices easily leak through the discharge path on the package surface and do not charge up.
導電性処理の方法としては、例えば金属を蒸着すること
が出来る。他の方法として界面活性剤水溶液を塗布し、
その後乾燥することにより1表面に親木基を付着せしめ
ることも出来る。他′の方法として金属微球子を混入し
たゴム、樹脂をm着することも出来る。他の方法として
金属性接着テープを接着することも出来る。As a method of conductive treatment, for example, metal can be vapor-deposited. Another method is to apply a surfactant aqueous solution,
After that, by drying, a parent wood base can be attached to one surface. As another method, it is also possible to apply rubber or resin mixed with metal microspheres. Alternatively, a metallic adhesive tape can be used.
導電性処理を施こす領域はリード周囲を除いたパッケー
ジ表面領域の一部分あるいは全部分に行なう。The conductive treatment is applied to a part or all of the package surface area excluding the area around the leads.
第1図、第2図に導電性処理を施こす領域の一例を示す
。FIGS. 1 and 2 show an example of a region to be subjected to conductive treatment.
半導体装置をソケットあるいは配線基板に実装する前に
導電性処理を落とすことも出来る。例えば金属を蒸着し
た場合は塩酸等の酸で洗い落としたり界面活性剤処理の
場合は水洗し表面に付着していた親水基を洗い落とす。It is also possible to remove the conductive treatment before mounting the semiconductor device on a socket or wiring board. For example, if metal is vapor-deposited, it is washed off with an acid such as hydrochloric acid, or if treated with a surfactant, it is washed with water to wash away the hydrophilic groups attached to the surface.
ゴム、l/M脂等を塗布した場合は有機溶剤等で洗い落
とす。半導体装置が実装状態ではパッケージ表面の導電
性処理を落とし、絶縁状態に戻す方が一般的には望まし
い。If rubber, l/m fat, etc. are applied, wash them off with an organic solvent, etc. When a semiconductor device is mounted, it is generally desirable to remove the conductive treatment on the package surface and restore the package to an insulating state.
第1図は本発明の一実施例の半導体装置の容器(表側)
の斜視図。
11樹脂
12 リード
13 導電性処理を施した領域
第2図は本発明の他の実施例の半導体装置の容器(裏側
)の斜視図。
21樹脂
22 リード
23 導電性処理を施した領域。
第 1 図
第Z区FIG. 1 shows a container (front side) of a semiconductor device according to an embodiment of the present invention.
A perspective view of. 11 Resin 12 Lead 13 Area subjected to conductive treatment FIG. 2 is a perspective view of a container (back side) of a semiconductor device according to another embodiment of the present invention. 21 Resin 22 Lead 23 Area subjected to conductive treatment. Figure 1 Ward Z
Claims (1)
、導電性処理を施こした半導体装置の客器。A semiconductor device container in which the surface area of the semiconductor device container, excluding the area around the external terminals, has been subjected to conductive treatment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11557281A JPS5816549A (en) | 1981-07-23 | 1981-07-23 | Housing for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11557281A JPS5816549A (en) | 1981-07-23 | 1981-07-23 | Housing for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5816549A true JPS5816549A (en) | 1983-01-31 |
Family
ID=14665880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11557281A Pending JPS5816549A (en) | 1981-07-23 | 1981-07-23 | Housing for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5816549A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60120541A (en) * | 1983-12-02 | 1985-06-28 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
JPS6327733A (en) * | 1986-07-21 | 1988-02-05 | Rabo Syst Kiki:Kk | Differential refractive index detector for liquid chromatography |
-
1981
- 1981-07-23 JP JP11557281A patent/JPS5816549A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60120541A (en) * | 1983-12-02 | 1985-06-28 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
JPS6327733A (en) * | 1986-07-21 | 1988-02-05 | Rabo Syst Kiki:Kk | Differential refractive index detector for liquid chromatography |
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