JPS58164308A - Binary coding circuit - Google Patents

Binary coding circuit

Info

Publication number
JPS58164308A
JPS58164308A JP57046904A JP4690482A JPS58164308A JP S58164308 A JPS58164308 A JP S58164308A JP 57046904 A JP57046904 A JP 57046904A JP 4690482 A JP4690482 A JP 4690482A JP S58164308 A JPS58164308 A JP S58164308A
Authority
JP
Japan
Prior art keywords
signal
frequency component
high frequency
binarized
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57046904A
Other languages
Japanese (ja)
Inventor
Takashi Kitagawa
喜多川 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57046904A priority Critical patent/JPS58164308A/en
Publication of JPS58164308A publication Critical patent/JPS58164308A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125Discriminating pulses
    • H03K5/1252Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To extract a low and a high freuency component signal and to eliminate a high frequency component noise, by separating a signal into the high and low frequency components, binary-coding them through threshold value circuits respectively, and mixing and outputting them. CONSTITUTION:The signal containing the noise is supplied from a terminal 38 to a low-pass filter 39 to separate the low frequency component, which is binary- coded by a comparator 41 and outputted as a signal component while inputted to a comparator 40 to be used to separate the high frequency component from the signal. The high frequency component separated by the comparator 40 is passed through comparators 42 and 43 to remove a small-amplitude noise component. Those signal are mixed by an OR circuit 47 and an AND circuit 48 to be outputted.

Description

【発明の詳細な説明】 本発明は2値化(ロ)路に関する。[Detailed description of the invention] The present invention relates to a binarization (b) path.

通常、アナログ信号を2値化する場合には、アナログ信
号の直流レベルと、スレッシ、−ルドレペルと呼ばれる
基準の直流レベルを比較器によって比較することがよく
行なわれている。しかしながらこのような従来の2値化
回路においては、前記アナログ信号に他の周辺回路から
の誘導あるいは干渉による高周波数成分の雑音が重畳さ
れることが多く、アナログ信号がスレッシか一ルドレペ
ルをよぎるところでは、雑音によって誤まりた2値化信
号が発生するという欠点があった。
Normally, when converting an analog signal into a binary value, a comparator is often used to compare the DC level of the analog signal with a reference DC level called a threshold level. However, in such conventional binarization circuits, high frequency component noise due to induction or interference from other peripheral circuits is often superimposed on the analog signal, and when the analog signal crosses the threshold level or one level, noise is often superimposed on the analog signal. The disadvantage of this method is that an erroneous binary signal is generated due to noise.

アナログ信号に含まれる高周波成分の雑音の影醤を除去
するため、アナログ信号をローパスフィルタに通して高
周波数成分を除去した後、直流のスレッシ冒−ルドレペ
ルと比較して2値化することも従来からよく行なわれ【
いる。しかしながらこのような2値化回路においては、
アナログ信号に含まれている本来2値化されるべき信号
の高周波数成分も除去されてしまうため、出力される2
値化信号において前記高周波成分の信号に対応する成分
が欠落するという欠点があった。
In order to remove the noise effects of high frequency components contained in an analog signal, it is conventional to pass the analog signal through a low-pass filter to remove the high frequency components, and then compare it with a DC threshold filter and binarize it. It is often practiced since [
There is. However, in such a binarization circuit,
Since the high frequency components of the analog signal that should originally be binarized are also removed, the output 2
There is a drawback that a component corresponding to the high frequency component signal is missing in the valued signal.

第1図は従来の2値化手順を説明するための波形図であ
る。
FIG. 1 is a waveform diagram for explaining a conventional binarization procedure.

高周波数成分の雑音4〜19および必要な高周波成分の
信号2および3を直流のスレッシ冒−ルドレペル20で
2値化すると、2値化信号21が得られる。2値化信号
21には必要な信号2および3に対応する2値化信号2
2および23は含まれているカ、スレッショールドレベ
ル20付近の雑音10〜12に対応する誤った2値化信
号24〜26が発生する。
When the high frequency component noises 4 to 19 and the necessary high frequency component signals 2 and 3 are binarized using a DC threshold filter 20, a binarized signal 21 is obtained. Binarized signal 21 corresponds to necessary signals 2 and 3.
2 and 23 are included, and erroneous binarized signals 24 to 26 corresponding to noises 10 to 12 near the threshold level 20 are generated.

アナログ信号1をローノくスフイルタに通ずると低域信
号27が得られ、これをスレッシ、−/レドレペル28
で2値化すると、2値化信号29が得られる。アナログ
信号1をローノくスフイルタに通すことによって雑音1
0〜12が除去されるため2値化信号29には誤った2
値化信号24〜26は発生しないが、必要な信号2およ
び30レベルが小さくなるため、必要な2値化信号22
および23が欠落する。
When the analog signal 1 is passed through the low frequency filter, a low frequency signal 27 is obtained, which is sent to the threshold, -/red level 28.
When the signal is binarized, a binarized signal 29 is obtained. Noise 1 is eliminated by passing analog signal 1 through a filter.
Since 0 to 12 are removed, the binary signal 29 contains an incorrect 2.
Although the digitized signals 24 to 26 are not generated, the required signal 2 and 30 levels are reduced, so the necessary binary signal 22 is generated.
and 23 are missing.

以上説明したように、従来の2値化回路にお(・ては、
高周波数成分の雑音および必要な信号を含むアナログ信
号をそのまま2値化すると、−った2値化信号が発生す
るという欠点があった。またアナログ信号より低域信号
を抽出して2値化すると、必要な高周波数成分の信号に
対応する2値化信号が欠落するEいう欠点があった。
As explained above, in the conventional binarization circuit (
If an analog signal containing high frequency component noise and a necessary signal is directly binarized, a negative binarized signal is generated. Furthermore, when a low-frequency signal is extracted from an analog signal and binarized, there is a drawback that the binarized signal corresponding to the necessary high-frequency component signal is missing.

本発明の目的は高周波数成分の雑音および必要な信号を
含むアナログ信号から雑音に対応する成分がなくかつ必
要な信号に対応する成分を含む2値化信号を得ることが
可能な2値化回路を提供することにある。
An object of the present invention is to provide a binarization circuit capable of obtaining a binarized signal containing no components corresponding to noise and components corresponding to the necessary signals from an analog signal containing high frequency component noise and necessary signals. Our goal is to provide the following.

本発明によれば、2値化されるべきアナログ信号の低周
波数成分を抽出する手段と前記低周波数成分を2値化す
る手段と、前記低周波数成分を2値化する手段および高
周波数成分を2値化する手段により得られる複数の2値
化信号を混合することKよって、高周波数成分の雑音の
影響がなく、しかも必要な全周波数成分の信号に対応し
た2値“化信号を出力する2値化回路が得られる・次に
本発明を図面を用いて説明する。
According to the present invention, there are provided a means for extracting a low frequency component of an analog signal to be binarized, a means for binarizing the low frequency component, a means for binarizing the low frequency component, and a means for extracting a low frequency component of an analog signal to be binarized. By mixing a plurality of binarized signals obtained by the binarizing means, a binarized signal that is not affected by noise of high frequency components and corresponds to signals of all necessary frequency components is output. A binarization circuit is obtained.Next, the present invention will be explained using the drawings.

アナログ信号に含まれる高周波成分のうち、雑音と必要
な信号を区別する完全な方法はない、しかしながら、か
なり有効な方法としてレベルの大きさで区別する方法が
考えられる。本発明による2値化回路においては、アナ
ログ信号より高周波数成分を抽出し、この高周波成分の
うちレベルの大きいものを必要な信号として2値化し、
他を雑音として除去する。
There is no perfect method for distinguishing between noise and necessary signals among the high frequency components contained in analog signals.However, a method that can be considered to be quite effective is to distinguish based on the magnitude of the level. In the binarization circuit according to the present invention, a high frequency component is extracted from an analog signal, and one of the high frequency components with a high level is binarized as a necessary signal,
Eliminate everything else as noise.

第2図は本発明による2値化手順を説明するための波形
図である。
FIG. 2 is a waveform diagram for explaining the binarization procedure according to the present invention.

第1図のアナログ信号1より高周波数成分を抽出すると
、第2図の波形30が得られる。高周波数成分の波形3
0のうち、信号31および32は各々、第1図の必要な
信号2および3に対応する。
When high frequency components are extracted from the analog signal 1 in FIG. 1, a waveform 30 in FIG. 2 is obtained. High frequency component waveform 3
0, signals 31 and 32 correspond to the required signals 2 and 3 of FIG. 1, respectively.

信号31および32は他の雑音に比ベレベルが大きいの
で、直流のスレッシ、−ルドレペル33および34各々
で2値化すると、2値化信号35および36が得られる
。高周波数成分の信号に対応する前記2値化信号35お
よび36を低周波数成分の信号に対応する低域信号の2
値化信号29に混合すると全周波数成分の信号に対応し
た2値化信号37が得られる。
Since the signals 31 and 32 have a higher level than other noises, when they are binarized using DC thresholds 33 and 34, respectively, binarized signals 35 and 36 are obtained. The binarized signals 35 and 36 corresponding to the high frequency component signals are converted into two of the low frequency signals corresponding to the low frequency component signals.
When mixed with the digitized signal 29, a binarized signal 37 corresponding to signals of all frequency components is obtained.

第3図は本発明の一実施例の回路図である。FIG. 3 is a circuit diagram of an embodiment of the present invention.

以下、第1図および第2図を参照し文、その動作を説明
する。
The text and its operation will be explained below with reference to FIGS. 1 and 2.

第1図に示すアナログ信号1を端子38より入力し、ロ
ーパスフィルタ39に通すと、第1図に示す低域信号2
7が得られる。比較器41において低域信号27を直流
電源44より供給されるスレッシ嘗−ルドレベ/L/2
8で2値化すると、2値化信号29が得られる。一方、
演算増幅器40において、アナログ信号1と低域信号2
7の差をとると、アナログ信号lの高周波数成分の波形
30が得られる。高周波数成分の波形30を比較器42
において直流電源45より供給されるスレッシ田−ルド
レペル33で2値化すると2値化信号35が得られ、比
較器43において直流電源46より供給さFLるスレッ
シ替−ルドレペル34で2値化すると2値化信号36が
得られる。2値化信号29.35および36をオア・ゲ
ート47およびアンド・ゲート48で混合すると端子4
9に2値化信号37が得られる。
When the analog signal 1 shown in FIG. 1 is inputted from the terminal 38 and passed through the low-pass filter 39, the low-pass signal 2 shown in FIG.
7 is obtained. In the comparator 41, the low frequency signal 27 is connected to the threshold level /L/2 supplied from the DC power supply 44.
When the signal is binarized by 8, a binarized signal 29 is obtained. on the other hand,
In the operational amplifier 40, the analog signal 1 and the low frequency signal 2
By taking the difference of 7, a waveform 30 of the high frequency component of the analog signal l is obtained. The waveform 30 of the high frequency component is transferred to the comparator 42.
When the signal is binarized by the threshold voltage drepel 33 supplied from the DC power source 45 in the comparator 43, a binary signal 35 is obtained. A valued signal 36 is obtained. When binary signals 29.35 and 36 are mixed by OR gate 47 and AND gate 48, terminal 4
9, a binarized signal 37 is obtained.

以上の説明のように、本発明による2値化回路において
は、2値化されるべきアナログ信号の低周波数成分を抽
出する手段と前記低周波数成分な2値化する手段によっ
て、アナログ信号の高周波数成分の雑音の影響のない2
 ifL化信号が得られ、アナログ信号の高周波数成分
を抽出する手段と高周波数成分を2値化する手段によっ
て、必要な尚周波数成分の信号に対応する成分を含む2
値化信号が得られ、複叙の2値化信号を混合して出力す
る2値化信号を得る手段によって、高周波数成分の雑音
の影響かなく、しかも必要な全周波数成分の信号に対応
した2値化信号が得られるという利点をもっている。
As described above, in the binarization circuit according to the present invention, the analog signal is high 2 without the influence of frequency component noise
An ifL signal is obtained, and by means of extracting high frequency components of the analog signal and means of binarizing the high frequency components, a 2-digit signal containing components corresponding to the necessary additional frequency components is obtained.
By means of obtaining a digitized signal and outputting a binary signal by mixing the compound binary signals, it is possible to avoid the influence of noise of high frequency components and to correspond to signals of all necessary frequency components. It has the advantage that a binary signal can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の2値化手順を説明するための波形図、第
2図は本発明による2値化手順を説明するための波形図
、M3図は本発明の一実施例の回路図である。 1・・・・・・アナログ信号、2.3・・・・・・高周
波数成分、4〜19・・・・・・雑音、20・・・・・
・スレッシ、−ルドレペル、21・・・・・・2値化信
号、22.23・・・・・・2値化信号の成分、24,
25.26・・・・・・誤った2値化信号、27・・・
・・・アナログ信号の低域信号、28・・・・・・スレ
ッシ、−ルドレベル、29・・・・・・2値化fjt号
、30・・・・・・アナログ信号の高周波数成分、31
゜32・・・・・・高周波数成分、33.34・・・・
・・スレッシ1−ルドレベル、35,36.37・・・
・・・2値化信号、38・・・・・・端子、39・・・
・・・ローパスフィルタ、40.41,42.43・・
・・・・比較器、44,45゜46・・・・・・直流電
源、47・・・・・・1了・ゲート、48・・・・・・
アンド−ゲート、49・・・・・・端子。 第2図 第3(!]
Fig. 1 is a waveform diagram for explaining the conventional binarization procedure, Fig. 2 is a waveform diagram for explaining the binarization procedure according to the present invention, and Fig. M3 is a circuit diagram of an embodiment of the present invention. be. 1...Analog signal, 2.3...High frequency component, 4-19...Noise, 20...
・Threshold, - level, 21...Binarized signal, 22.23...Binarized signal component, 24,
25.26...Incorrect binarized signal, 27...
...Low frequency signal of analog signal, 28...Threshold, -led level, 29...Binarization fjt number, 30...High frequency component of analog signal, 31
゜32...High frequency component, 33.34...
・Threshold level, 35, 36.37...
...Binarized signal, 38...Terminal, 39...
...Low pass filter, 40.41, 42.43...
...Comparator, 44,45゜46...DC power supply, 47...1 end/gate, 48...
AND gate, 49...terminal. Figure 2, Figure 3 (!)

Claims (1)

【特許請求の範囲】[Claims] 2値化されるべきアナログ信号から低周波数成分を抽出
する手段と、前記低周波数成分を2値化する手段と、1
5ft g己アナログ信号から高周波数成分を抽出する
手段と、前記高周波数成分を2値化する手段と、前記低
周波数成分を2値化する手段および高周波数成分を2値
化する手段より得られる複数の2値化信号を混合して出
力する2値化信号を得る手段を有することを特徴と祇る
2値化回路。
means for extracting low frequency components from an analog signal to be binarized; means for binarizing the low frequency components;
5ft g is obtained from a means for extracting a high frequency component from an analog signal, a means for binarizing the high frequency component, a means for binarizing the low frequency component, and a means for binarizing the high frequency component. A binarization circuit characterized by having means for obtaining a binarized signal by mixing and outputting a plurality of binarized signals.
JP57046904A 1982-03-24 1982-03-24 Binary coding circuit Pending JPS58164308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57046904A JPS58164308A (en) 1982-03-24 1982-03-24 Binary coding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57046904A JPS58164308A (en) 1982-03-24 1982-03-24 Binary coding circuit

Publications (1)

Publication Number Publication Date
JPS58164308A true JPS58164308A (en) 1983-09-29

Family

ID=12760339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57046904A Pending JPS58164308A (en) 1982-03-24 1982-03-24 Binary coding circuit

Country Status (1)

Country Link
JP (1) JPS58164308A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2622070A1 (en) * 1987-10-14 1989-04-21 Jaeger Device for shaping analogue frequency signals of top dead centre type
FR2622071A1 (en) * 1987-10-14 1989-04-21 Jaeger Device for shaping analogue frequency signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2622070A1 (en) * 1987-10-14 1989-04-21 Jaeger Device for shaping analogue frequency signals of top dead centre type
FR2622071A1 (en) * 1987-10-14 1989-04-21 Jaeger Device for shaping analogue frequency signals

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