JPS58164089A - Logical circuit - Google Patents

Abstract

PURPOSE:To prevent malfunctions of logical circuits, by realizing a logical circuit equipped with the 1st logical gate circuit which outputs signals having opposite logical values to those of input signals from a logical signal source and the 2nd logical gate circuit which outputs signals having the same logical values as the input signals. CONSTITUTION:In the logical circuit of an address buffer using an NOR gate, it is arranged that an output Vout2 having the same logic as an input logical signal Vin is obtained by means of two-stage inverters I2 and I2 and another output Vout1 having the opposite logic to that of the input logical signal Vin is obtained by means of an NOR gate NOR1 which uses the output Vout2 and the input logical signal Vin as the input. When this circuit configuration is applied, two logical output voltages having the same logical value and the opposite logical value are settled at levels opposite to each other after the voltages are once set to the same level when the voltage of a logical signal source varies from one logical level to the other level. Therefore, double selection can be avoided and malfunctions can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logic circuit, and more particularly to a logic circuit that outputs the same logic value and the opposite logic value from one logic value signal source.

[Technical background of the invention and its problems]

In an MO8 type storage device or the like, an address buffer circuit includes a logic circuit that outputs from one address input a signal having the same logic as that of the input signal and a signal having the opposite logic. FIGS. 1 and 3 show the circuit configuration of an address buffer having N+1 inputs, a subsequent decoder, and a selection line connected to a row or column serving as a decoder output in such a MOB type storage device. As shown in Figures 1 and 3, the output of the address buffer becomes the decoder input either directly or via the next stage logic circuit, so two output signals with opposite logic to each other are sent to the next stage circuit. It is not uncommon for either one of the 5-der logics to function at the same time, depending on the type of the 3-der circuit.

This is because the decoder section selects two or more rows or columns at the same time, causing malfunction.

The phenomenon that causes this malfunction will be explained with reference to FIG. The address buffer 1 of the circuit shown in FIG. 1 receives same logic signals aQ, al, °°°, and aH having the same and opposite logic levels as the respective address inputs, and an inverse logic signal "'-0+111+... +&st is output.

As one decoder input, either the same logic signal or the opposite logic signal from 0th to Nth is input, and a deco/2 corresponding to a total of 2N+1 combinations is provided. One is selected and one of the selection lines is activated. These decoders 2 are:

NOR dirt N0Ri (1=o, 1,...
2N+1s), the combination of signals in which all of the same logic signals or reverse logic signals from θth to Nth are at low level "L" is input. Only the decoder sets the uncorresponding selection line to high level "H", and all other selection lines become low level @L#. For example, NOR goo)
The inputs of NO'Ro and NOR1 are respectively (ao+lL1
, ""aN) and (h+ ILl 1 "'aN)
Tonatail.

Therefore, all the signals at ao-aNi are at low level 1L.
", the output S0 of NORr-to N0Ro becomes high level "H#", and the other outputs Sl', , B, N+
1 is the total terror level "L". In other words, address input (A6, AI + ・'JN)'' (Op
0''), the dart output So line becomes the active selection line. Here, it is assumed that the high level "H#HI11" corresponds to the level 2, and the low level "L" corresponds to the "O" level. Next, address force (Ao, -As) = (1, 0
-0), the output Sl becomes a high level "'1", and the other outputs S. , 82 to 82N+1-1 are all at low level "0". This is because the input of NOR dart NOR is ("0yal*'・'+aN), and the address input A
The inverse logic value signal of o (=1) - (=0) is NOR
This is because it is an input to the ORI.

Now, consider a case in which all address inputs A1 to AN other than Ao are at low level wOw in this circuit. At this time, input A. −“0# if NOR dirt N0
All inputs of Ro become "0", and its output So line becomes an active selection line. If Ao-"1#, then NORr-) N0
All inputs of R1 become "0", and its output Sl line becomes an active selection line. At this time, NOR gate N0Ro, N0
The inputs of R1 are ("0+01...0) and (stone,
0. ...0). Here, the input Ao is “O
” to “1#”.

At this time, the input (lL61 = o) is from (0, 1) to (
1oo), but the voltage during this input transition actually changes as shown in FIG. Even if the voltage during this transition is temporary as seen from the decoder input (ao, 'i
There must not be a situation where r ) = (0, 0). As can be seen from FIG. 2, the highest possibility of this is the voltage VC at which the address buffer output levels VaO and VaO intersect. When this voltage Vc acts as a low level @0'' for the next stage decoder input, there are times when all the inputs of NOR dirt N0R0 and N0R1 are considered to be '0#', and both the output 8o and the Sl line are active selection lines. As a result, two rows or columns are selected at the same time, causing a malfunction.In other words, at this time, the transition of input a6.lL6 is ('Oz &0)-
(0+1)→(0,0)→(1,0). This phenomenon is a requirement that must be avoided in memory design, and in order to avoid this phenomenon, the above voltage level ■. It is necessary to increase the cross voltage VC of +VaO. In this case, the input (, &6 + a6)"'(0+
The above voltage vc during the transition from ) to (1,0) acts as a T high level 1'' for the input of the next stage, and NOR
Only the "1" input to both N0Ro and N0R1, that is, aor "0" becomes a high level "1", and both the output So and Sl lines are inactivated. In other words,
The transition of input ao, η is (lLo, ao)=(0,1
)→(1,1)→(100). At this time, the output S
.

After the row or column corresponding to the output signal S1 is selected, no malfunction occurs because the row or column corresponding to the output Sl is finally selected without any row or column being selected next.

9- In the above explanation, we have described a decoder that is activated when all inputs are at low level "On," but conversely, as shown in Figure 3, it is activated when all inputs are at high level 11. There is also a decoder. In this case, consider, for example, a transition from a state in which the output SO2 line becomes an active selection line to an output S, / line becomes an active selection line y. That is, the address inputs A1' to AN/ are all at the high level "1#", and the input 'A o' is at the low level 10.
”, at this time NAND der) NAN
Do.

The input of NAND 1 is old (aot ] +'l
m・・'e 1 ) and (a6 * '1 + 1"+・
..., 1). Furthermore, in terms of the output of address buffer 1, (&oz; aQ”) − (1rO) → (
0, 1) transition is the decoder 20 input r-to NANDo,
Let's think about how it works with NANDl. As shown in Fig. 4, the voltage during this transition is the voltage of input a;
, o' and the voltage v crystal' of the input ro'.
Both 'sSl' lines are activated at the same time, and two rows or two columns are selected at the same time, resulting in malfunction. That is, the transition of input 'Or6 is (a(1
, IJl )−, (1,Q)−+(1,l)−+(01
1). In order to avoid this phenomenon, it is necessary to lower the cross voltage vc' of the voltage Va (3',%@').In this case, (ao/+aG')=(1,
The above voltage c' during the transition from 0) to (0, 1) acts as a low level 10'' for the input of the next stage, and the NAND
(Goo) NANDo, NAND, both ``0# input,
In other words, 1"O' * a, only / is low level "0"
At the same time, both the output So' and Sl' lines are inactivated. In other words, the transition of a o/ , a , / is (ao'
, io′)=(1,o)→(0,0)→(0,1). At this time, the output S. After the row or column corresponding to ' is selected, no row or column is selected, and finally the row or column corresponding to the output Sl is selected, so no malfunction occurs. In this way, by setting the crossover voltage Vc'k of the output voltage of the address buffer 1 to an appropriate voltage, malfunctions can be prevented.

Next, a description will be given of how the conventional circuit works in accordance with the above-mentioned solution method. FIG. 5 shows a typical conventional circuit that outputs the same logical value and the opposite logical value from one logical input in an address buffer. That is, the output signal ■. This is a circuit in which inverters 11 to 1m are connected so that utl*Voutz has the opposite logic and the same logic as the input signal Vin, respectively,
Output ■. utl yVOut2 is directly connected to the next stage decoder circuit. Here, for the sake of simplicity, assume that both inverters l and ~1s are ideal inverters whose input characteristics are the same no matter which power supply terminal they approach.
Address buffer output V. As shown in FIG. 6, utl HVout2 exhibits a voltage characteristic that is symmetrical about the cross voltage Vc'l, and Vc = -! -Voo (VDD: electric field voltage). In this case, in order to avoid double selection in the next stage decoder section, if this decoder is active for high level "1", the above voltage vc should be set to low level 'O' ( !: t.

Conversely, when the next stage decoder is active for low level 10'', the voltage vc must work at the next stage decoder as high level "1".Therefore, conventionally, In the former case, as shown in FIG. 7, the cross voltage Vc with the output V.utl +Vout!
In the latter case, as shown in Fig. 8, the cross voltage V
A method is being used to increase c. Therefore, in the former case, the output V to the vBB (Ov power supply) side. In order to increase the driving capability of utl, the driving transistor on the vs8 side of the inverter 11 is made larger, and the output V is increased. Similarly, for ut mushrooms, the V811 side drive transistor of the inverter 13 is made relatively large so as to increase the driving ability to the V88 side, and the output ■. utl+VOut! A method was used to create asymmetry in the driving capacity.

As a result, the output V. The output characteristic of utl+Voutt becomes as shown in FIG. 7, and the cross voltage VC decreases.

On the other hand, in the latter case, VDD (e.g. 5v power supply)
Output V to the side. In order to increase the driving capacity of utl, the inverter 1.0VDD side drive transistor is made relatively thick,
Similarly, for the output Vout+t, a method is to make the inverter 1s13-OvDD side driving trannoster relatively thick so as to increase the driving ability to the VDD side, and to make the driving ability asymmetrical with respect to the output VouLt +"0ut2. As a result, the output ■.u
The output characteristic of tl +vOut2 is as shown in FIG. 8, and the cross voltage Vc increases.

However, in the method described above, the inverter's inversion voltage does not change much even if there is some asymmetry in the drive capability, so the cross voltage Vc is sufficiently shifted to the V2O side or VD
It is difficult to avoid double selection by approaching the D side, and furthermore, this cross voltage vc easily changes due to changes in the threshold value of the vO8) runnostar due to variations in manufacturing conditions. For example, the 9th
The figure shows the characteristics when the VaS side drive transistor of inverters 11+13 is enlarged. (2) The threshold value of the 88 side drive transistor becomes high due to variations during manufacturing, and the inverter 11. When the inversion voltage of i3 (this is defined as the input voltage at which the output voltage of inverter 1m and 13 becomes AVDD) increases by Δvl, the output characteristic of inverter il,i, changes from Voutl + vout2 to vOut 1 + vOut'2, the cross voltage Vc immediately becomes TVDD, and there is a risk of double selection in the decoder section. Here, ΔV
, means the voltage obtained by converting the margin voltage of the cross voltage vc to avoid double selection in the decoder section into the inverter input voltage, and when its magnitude is calculated, the voltage gain of the inverter 1'+F is expressed as G. Suppose then. Here, VDD=5V to estimate Δvl.

Let Vc=IV. The voltage gain G is that the inverter is CMO8
It varies depending on whether it is shaped like a turtle or a turtle, but [10 to 1]
It is about 000J. Therefore, ΔV+! 0.15V
~0.0015V. Next, let us consider the fluctuation of the threshold value that causes the fluctuation ΔV of the second-in-harter inversion voltage.

The variation in threshold required to produce this variation will vary depending on the configuration of the in mark, but in any case ΔvI to 2ΔV
, with a voltage value between . Therefore, if the threshold value of the drive transistor changes by about 0.003V to 0.3V, there is a risk of double selection in the decoder section.

This degree of threshold voltage variation is common, and therefore the conventional method of avoiding double selection in the decoder section by changing the size of the transistors in the inverter as described above is not very effective.

[Purpose of the invention]

The present invention has been made in view of the above points, and provides an output signal supply circuit that uses fluctuations in the threshold voltage of transistors constituting the circuit in a logic circuit that outputs a signal having the same logic value as an input signal and a signal having the opposite logic value. An object of the present invention is to provide a logic circuit that can prevent malfunctions in the circuit.

[Summary of the invention]

In order to achieve the above object, the present invention provides a logic circuit that outputs the same logic value and the opposite logic value from one logic signal source, in which the voltage of the logic signal source changes from one logic level to the other logic level. When changing to logic level, NOR
A circuit is constructed by combining gates or NAND gates so that after the two logic output voltages reach the same logic level, they settle to opposite logic levels.

Therefore, if such a logic circuit is used, for example, in an address buffer, it becomes possible to prevent double selection in the decoder section.

[Embodiments of the invention]

FIG. 10 shows a logic circuit of an address buffer using N0RI"-)ffi. In this circuit, an output V.utz'i of the same logic as the input logic signal Vln is obtained by a two-stage inverter 11.I2, NOR key with the above output V.uH and input logic signal Vin as inputs N0R
1, the output V has a logic opposite to that of the input logic signal Vin.

I'm trying to get uH.

FIG. 11 shows the input/output characteristics of the circuit of FIG. 10.

Now, the input Vin is low level "0" Karano Inbel"
Let us consider the case of transitioning to 1''.Here, for simplicity, as shown in FIG. Assume that we are waiting for a threshold voltage with the same driving ability and absolute value. First, when the input Vin is the V88 side voltage (ov), the output V.utt is the VDD potential, and the output V.utl is the VB+! potential. .Next, by gradually increasing the input Vln, the NOR dirt NoR
On the other hand, the input v person of 1 goes up as shown in FIG.

As can be seen from the circuit configuration of the NOR dart shown in FIG.
=Vss, the effective driving capability of the P-channel transformer TP is approximately halved when the output is set to about vo k Vpn'ft. On the other hand, since the N-channel transistor TN is connected in parallel, the input vil=Vn
The driving capability of the N-channel side transnoster TN when n or viz = VDD is not reduced by half. 'Currently, it is assumed that both the N-channel transistor TN and the P-channel transistor TP have the same driving ability and have the same threshold value in absolute value, so the NOR der)
NOR.

The effective driving capability of the P-channel transistor TH is approximately half that of the N-channel transistor TH.

Therefore, the P-channel transistor TP and the N-channel transistor TN, which have the output characteristics shown by the broken line in FIG. NOR
The output of Dart N0R1 is inverted. On the other hand, in
t-ta Il.

11 has the same driving ability as the P-channel transistor and the N-channel transistor, so the human power Vin is 2.
It is only reversed when it becomes VDD. Therefore, the output V.

As can be seen from Fig. 11, the cross voltage VC with utl +"0uL2 is much smaller than 2 vDD.
l r Vout! )=(VDD+V8B)→(V
The voltage transition from Cr Vc ) to (Vss + VDD) is (1,0) → (0,0) for the next stage decoder.
→ (0, 1), and the circuit in FIG. 10 constitutes an address buffer for the decoder activated at the high level shown in FIG. 3 without the risk of malfunction due to double selection. Become. In addition, in this circuit, even if the threshold value of the transistor changes, the effective relative value of the driving ability of the P-channel transistor TPO of N0Rr-)NOR1 to the driving ability of the N-channel transistor is approximately half of each in mark. Even if the inverting voltages of inverters I, , I, vary somewhat due to variations in the threshold voltages, the inverting voltage of NOR dart N0R1 will always vary at a voltage value υ lower than the variation of the inverting voltage of inverter I3.
=V88 →NORf-tN must be applied to the change of VDD
OR1 is inverted before inverter ■2, and the cross voltage Vc
1) It is now kept at a voltage close to Vss and there is no risk of double selection in the decoder.

FIG. 13 shows a logic circuit according to another embodiment of the invention. This circuit consists of inverters l and I4 that output the inverse logic of the input logic signal Vin, and these inverters I
It has a NOR dart N0R2 which inputs the output of 3+I4, and the output of inverter 3 is the output V of the opposite logic to the input. u
tI and fi, NOR key order-thoth, NOR,
The output of is the output vout2 which has the same logic as the input. Here, consider the voltage transition of input Vin=Vs, →vDD.

FIG. 14 shows the input/output characteristics of the circuit of FIG. 13. That is, when the input Vln=V, , the output voutl
-Vnns N0RI') N0R2(D One input VB""VDD + vOutl ""0 input which is VBB") Output V in inverter month 3 at 4VDD.

The output is reversed. At this time, NORr −) NOR
, when the output ``ouH'' is inverted, the cross voltage VC is 2 Vn
Since there is a risk of double selection in the next stage decoder, one input VB of the two inputs of NOR Dart NOR is set to Vin -! VDD Te is still VDD D
Keep the side mold pressure K h-. In this way, ■N with 1n-ivDD
ORr-NOR, is inverted and the output Vouts becomes VDD
Lateral pressure has not yet occurred. Then, the inverter 4 is inverted at a voltage v2 that is larger than the input Vin or 2 vD D, and the input Vin further increases to VB.
However, the voltage Vl becomes lower than that of VDD (NOR
r-t, NOR, is inverted and outputs V. utll is VDD
The side voltage is the voltage.

In the above circuit, in order to invert I4 later than the inverter, the relative driving ability of the P-channel transistor to the N-channel transistor is set so that I4 is larger than the inverter I3. It is necessary to make the relative size of the P-channel transistor larger in inverter I3 than inverter I3. This results in an output V as shown above. utl and V. Utz voltage transitions can be caused by these outputs V. As can be seen from FIG. 14, the cross voltage vc of utl +Voutl is much smaller than 2"DD.Then, the input v1n=v88→v
Output (voutt *Voutl
) = (VDD r VBB ) → (”C+ vc) →
(v8a l vDD) A chisel pressure change occurs, and for the next stage decoder, (1, 0) → (o, o) → (0
, 1), the circuit shown in Fig. 13 becomes a circuit that constitutes an address buffer for the decoder activated at the high level shown in Fig. 3, without the risk of malfunction due to double selection. .

Furthermore, in this circuit example, even if the threshold value of the transistor changes, the inverting voltage V of the inverter I4 is the inverting voltage of the inverter ■, -! If the voltage is equal to or slightly smaller than -vDD, the crossover voltage Vc can be maintained at the Vllll side potential, and double selection can be avoided.

This is because the NOR dart N0R2 is inverted and the output vou
t2 becomes the vDD side voltage after the output voltage Vm of the inverter 4 reaches the v1 potential, which is lower than 7VDD, as explained in FIG. 11 above. Then, the inversion potential V of the inverter 4 is the inversion potential of the inverter 3 -
! The condition of being equal to or slightly larger than -vDD is a condition that can almost be maintained if the relative size of the P-channel transistor to the N-channel transistor is larger in I4 than inverter 3, and in the worst case Even if the output V. Since uts is also the input of NOR (NOR), its voltage value is 1! Only when the value becomes smaller than -vDp, the NOR gate NOR is inverted and the output Vout* goes to VDD. Therefore, like the above-described embodiment, this circuit is not affected by variations in the threshold values of the transistors and does not pose the risk of double selection in the decoder.

Shows the circuit. This circuit replaces the circuit of FIG. 10 with an output V. Output V only when utl becomes low level “0#”
. Output V so that ut2 does not reach high level "1#".

ut2 k output V. This is a modified example using utl as a condition.

Therefore, the output characteristics of this circuit are almost the same as those in FIG. 0) → (0,0) → (0,1
), and the circuit of FIG. 15, like the circuit of FIG. 10 described above, provides an address for the decoder activated at the high level shown in FIG. 3 without the risk of malfunction due to double selection. This circuit constitutes a buffer.

FIGS. 16, 18, and 20 show two inverters (I6 r'6) l (I7118 L') in the circuits shown in FIGS. 10, 13, and 15, respectively.
Add (Is + Ito), input vin=■口→■D
Output for voltage fluctuation of D (Vouts 1VOutl
) to the next stage decoder (011) →
This is a circuit that works as (1, 1) → (1, 0).

Due to this voltage transition, the circuits shown in FIGS. 16, 18, and 20 are at risk of malfunction due to double selection compared to the decoder shown in FIG. 1, which is activated by the low level. (address without address) This is a circuit that constitutes a 4th buffer.

FIG. 17 shows the input/output characteristics of the circuit shown in FIG. 16, and the circuit shown in FIG.
, I, so the output Voutl+
Voutz is completely opposite to the output characteristic shown in FIG.
Reverse to voltage.

FIG. 19 shows the input/output characteristics of the circuit shown in FIG. 18. Since the circuit shown in FIG. 18 is the circuit shown in FIG.
The output characteristics shown in FIG.
The side voltage is reversed. Similarly, the circuit in FIG. 20 is a circuit in which an inverter Illl0 is added to the circuit in FIG. 15, and its output characteristics are as shown in FIG. become that way. These figures 16 and 18
The circuits shown in Figures 20 and 20 have one stage of input gates to reverse the output logic, but they also have one stage of input gates.
By adding an inverter and a total of two stages of series inverters, the output logic is not changed, but the output voltage transition can be shaped and the voltage can change even more sharply. The driving ability for the next stage circuit is improved.

In each of the embodiments described above, N
We have shown the case using 0Rr-t, but next we will use NANnr-
Here is an example using FIG. 21 shows an embodiment of the present invention using a NANII'' circuit. In this circuit, an output V.utz having the same logic as the input logic signal Vin is outputted by a two-stage inverter ``11+■l□. This inverter l1i
NAND r which inputs the output of 1 and the above input "in"
-) NAND 1 input Vin and output V with opposite logic
. I am trying to output utl from 96. Figure Mg2 shows the input/output characteristics of the circuit in Figure 21. Now, let us consider the case where the input Vin transitions to low level - 0 "kara high level 1" H. For simplicity, as shown in FIG. 23, NANI) r-1
It is assumed that the P-channel transistor ``rp'' and the N-channel transistor TN constituting ``-'' have the same driving ability and threshold voltage with the same absolute value.
When in is the VSS side voltage, that is, 070, the output V. ut
l is VDD potential, output V. utt is about Vss'it. Next, when the input Vin is gradually increased, the human power vA of NANDf''-)NANDl becomes the second
It goes up as shown in Figure 2. As can be seen from the circuit configuration of NANL) dart shown in FIG.
In NDI"-), the N-channel transistors 27 and TN are connected in series, and when the input υi1-υ?:2=VDD and the output tlQtVss potential, the effective driving ability of the N-channel transistor TN is approximately It will decrease.

On the other hand, since the P-channel trunk transistor TP is connected in parallel, the input τzl = V8B or τ12 = Vs
The driving capability of the P-channel transistor TPO in a is not reduced. Now, N channel Tran Zosta T
Since it is assumed that the N and P channel transistors TP have the same driving capacity and have the same threshold value in absolute value, the effective driving capacity of the N channel transistor TN constituting NANDr-) NANDl-i is approximately half that of the P-channel transnoster TP. Therefore, the P-channel transistor TP and the N-channel transistor TN, whose output characteristics with respect to the V input voltage are shown by the broken line in FIG.
The output of NΔD1 is finally inverted.Since the P channel tonostar TP and the N channel tonostar TN have the same driving ability, the input Vin becomes an inversion voltage of 7Vno. Invert. Therefore, 11 output V.ut1+Vou
As can be seen from Fig. 22, the cross voltage of l is 2 V p
The voltage υ is much closer to vDD than D, and the input Vin
=Vss-+Von output (Voutl+”Ou
T! ) :(VDD r va B )→(Vc
The voltage transition of r Vc ) → (Vs a 4VDD) is (1,0) → (itD → (0,
1). Therefore, the circuit shown in FIG. 21 constitutes an address buffer for the decoder activated at the low level shown in FIG. 1 without the risk of malfunction due to double selection. Further, in the above circuit, even if the threshold value of the transistor changes, the effective relative value of the driving ability of the N-channel transistor TN of the NAND 1 to the driving ability of the P-channel transistor TPO is approximately half of that of the inverter. Even if the inversion voltage of the inverter 112 changes somewhat (due to threshold voltage fluctuation)
-) NAND, the inversion voltage must be the inverter ■11
Since it fluctuates at a higher voltage value than the fluctuation of the inversion voltage of +11m, N
Since the AND dirt NAND 1 is inverted after passing the inverter Ill, the cross voltage Vc is kept at a voltage close to VDD, and there is no risk of double selection in the decoder.

FIG. 24 shows a logic circuit 29 according to another embodiment of the invention. In this circuit, a signal V having the opposite logic to the input logic signal Vin. utt to the inverter 113, and inputs the output of the inverter l111 and the output of the inverter I14 which outputs the inverse logic of the input Vin.
AND ) fa-) NAND, same as multi-input logic.
■ Signal of logic signal. utt is output. Here, as before, the input Vin ``'Va, -→V
Consider the voltage transition of DD. FIG. 25 shows the input/output characteristics of the circuit of FIG. 24. In the figure, input vln=v
8II, output vOut 1 =VDDsNAND
Dart NAND, one input vl=vDD1 output v
outa = V-mouth. Assuming that the P-channel transistor and the N-channel transistor constituting the inverter 113 have the same ability, the output of the inverter 113 at input 1 Mln- and VDD. ut
l is inverted. At this time, NANDI'-) NA
Output V of ND2. When utt is inverted, the output V. utl
The cross voltage Vc of yvout2 is 2 vD D,
Because there is a risk of double selection in the next stage decoder, NA
One of the two inputs of NDf-)NAND, VB
(Invert -Ql'l-- so that the input vl n '' 2 V
Set the input V to the V88 side voltage at Bg. Before the voltage source 114 enters the inverting state, the NAND gate NAND, inverts and outputs ■ if the input VB only goes to a voltage v1 higher than 100 VDD. utz becomes the VDD side voltage.

In the above circuit, in order to invert the inverter 14 earlier than the inverter 13, the relative driving ability of the N-channel transistor to the P-channel transistor is set so that the inverter 14 is larger than the inverter 11. The relative size of the N-channel transistor to the inverter 113
It is necessary to make the width 114 larger. This results in an output V as described above. utl 5Vo
It is possible to make a voltage transition of ul, and the output voutt
As can be seen from FIG. 25, the cross voltage VC of +vOut2 is close to VDD. And input v1n″
Output for v8B+vDD transition (vOutl+■o
ut2) = (vDD, v8a) → (vc, vc) → (v
88. vDD) voltage transition occurs, and the logic (1, 0) → (1, 1) → (011) occurs for the next stage decoder. Address bar with no risk of malfunction due to double selection for decoders activated at level.

This is the circuit that makes up the fa. Furthermore, in this circuit example, even if the threshold value of the transistor changes, as long as the inversion voltage v2 of the inverter 114 is equal to or slightly smaller than the inversion chamber pressure 2VD of the inverter 11s, the cross voltage VC remains constant.
can be maintained at the VDD side voltage, and double selection can be avoided. Because NAND r −) NA
ND is inverted and outputs Vout! becomes the VDD side voltage because the output voltage vn of the inverter 14 already occurs at Vl'#[ which is higher than TVDD as described above. The condition as to whether the inverted voltage v2 of the bark 114 is equal to or slightly smaller than the inverted voltage TVDD of the inverter 130 is that the relative size of the N-channel transistor to the P-channel transistor is Ta114
This is a condition that can almost be followed as long as is larger, and even in the worst case, the output vout1 is NAND (NAN)
Since its voltage is the input of D, the NAND gate NΔD3 is already inverted at a voltage value higher than 2'D, and the output V. Utz is heading towards VDD tt. Therefore, like the previous embodiments, this circuit is also unaffected by threshold fluctuations of the transistors and does not pose the risk of double selection in the decoder.

FIG. 26 shows a further different embodiment circuit of the present invention. This circuit example outputs the circuit of the embodiment shown in FIG. 21 described above. Output Vout for the first time after utz became No\Irepel
The output V is output to the output voutl' so that l can be at a low level. It is conditioned by utm. In other words, this circuit consists of a two-stage inverter 111+1 that inverts the input Vin.
12, the output of this inverter I12, and the input Vtn& are input. An inverter 115 that inverts the output of the inverter Ilj, an output of the inverter 33-11B, and an output of the NAND circuit NORr-) NOR4, Kono N
Inputter 1 that inverts the output of NOR4
1g. Therefore, the input/output characteristics of this circuit are approximately the same as those shown in FIG. 22, and the input V l n-'V s
Output (Voutl +V
The voltage change of (out2) is ('
The circuit in FIG. 26 is activated at the low level shown in FIG. 1, similar to the circuit in FIG. 21. This circuit forms an address buffer for a decoder that does not have the risk of malfunction due to double selection.

Figure 27 shows the in-gutter Ita' in the circuit of Figure 26.
This shows a circuit in which r is deleted and the wiring is changed so that the output of inverter Ill is input to NOR dart N0R4, and its operation and effect are the same as the circuit of FIG. 26.

28, 30, 32, and 33 are the aforementioned FIGS. 21, 24, and 26, respectively.

Two inverters (I17, Its
)+(119+120),(Its+,5m)
, (Its nI24) respectively, and input ■
In response to the voltage transition of ln-■ss-+vDD, the voltage transition of the output (舊gat, +VOut2) is applied to the next stage decoder as (0, 1) → (0, 0) → (1, 0). This shows the circuit.

Due to such voltage transitions, these circuits constitute address buffers without the risk of malfunction due to double selection for the decoder activated at the high level shown in FIG. Become.

FIG. 29 shows the input/output characteristics of the circuit shown in FIG. 28 above. The circuit of FIG. 28 includes an inverter 117. Since it is a circuit with l5se added, 1 output vou
tl and vout2 are completely opposite to the outputs shown in FIG. 22, and the output cross voltage Vc is the vDD side voltage v8.
The voltage is reversed to the 11 side voltage.

Figure 31 shows the input/output characteristics of the circuit in Figure 30.
The circuit in Figure 30 is the circuit in Figure 24 with an inverter 119+
■Since it is a circuit with 20 added, the output V. utr+
Voutz is completely opposite to the input/output characteristics shown in FIG. 25, and the output cross voltage vc is reversed to the VDD side voltage and the v86 side voltage. Figure 32.

The circuit of FIG. 33 also has an inverter ('', 1 + I22) + (I
islI24)e is added to the circuit, and its output characteristics are as shown in FIG. 29 above.

Note that FIGS. 28, 30, and 32 above.

In Figure 33, the multi-output logic of a single-stage inverter is reversed, but one more stage of inverter is added, resulting in a total of two stages of series inverters.Although the output logic remains unchanged, the transition of the output voltage is shaped. It is also possible to make the voltage change more steeply, and the addition of such an input circuit improves the driving ability for the next stage circuit.

In addition, although the above-described example circuit is explained using a CMO8 logic circuit, the present invention is applicable to each inversion of an inverter, a NOR gate, and a NAND r-).
The difference in the inversion voltage of these three logic darts is due to the logic using the so-called small-type MO8) runnostar configuration, in which the enhancement tight transistor is the drive transistor and the degradation type transistor is the load transistor. f-).

〔Effect of the invention〕

According to the present invention, in a logic N path in which one logic signal source outputs the same logic value and the opposite logic value, when the voltage of the logic signal source changes from one logic level to the other logic level, NOR r- or NAND r-
The circuit configuration is such that the two logic output voltages become the same logic level and then settle to opposite logic levels. Therefore, by using the circuit of the present invention in an address buffer, double selection in the decoder section can be prevented and malfunctions can be prevented.

[Brief Description of the Drawings] Fig. 1 is a circuit configuration diagram showing a conventional address buffer and decoder circuit, Fig. 2 is an input/output characteristic diagram of the circuit shown in Fig. 1,
FIG. 3 is a circuit configuration diagram showing a conventional address buffer and decoder circuit, FIG. 4 is an input/output characteristic diagram of the circuit in FIG. 3, and FIG.
Figure 6 is an input/output characteristic diagram of the circuit in Figure 5. Figures 7 and 8 are improved input/output characteristic diagrams of the circuit in Figure 5. FIG. 10 is a logic circuit diagram showing an address buffer according to an embodiment of the present invention, and FIG. 11 is the circuit of FIG. 10. Fig. 12 is a detailed circuit diagram of the NOR gate in Fig. 10, Fig. 13, Fig. 15, Fig. 16, Fig. 18, Fig. 20, Fig. 21, Fig. 24. , FIG. 26, FIG. 27, FIG. 28, FIG. 30, FIG. 32, and FIG. 33 are logic circuit diagrams showing address buffers according to other embodiments of the present invention, respectively, and FIG. Figure 17 is the input/output characteristic diagram of the circuit in Figure 16, Figure 19 is the input/output characteristic diagram of the circuit in Figure 18, and Figure 22 is the input/output characteristic diagram of the circuit in Figure 21. Figure 23 is a detailed circuit diagram of the NAND gate shown in Figures 38-21, Figure 25 is the input/output characteristic diagram of the circuit in Figure 24, and Figure 29 is the input/output characteristic of the circuit in Figure 28. 31 is an input/output characteristic diagram of the circuit shown in FIG. 30. N0Ror "' y N0R2" -1, N0R4
~N0R4...NOR dirt, NAND6
#-, NAND2N+1-1, NAND
I, NANDI °°. NANDr-t,' nO+ tnl *”'s I
HzN+'-1+ It r h +13.11~
I 114 ”'Inverter%vinlυi11νiz
=. Input・υQ + VOutl + Vout2 J−
Vout voltage...output, vc...output cross voltage, VDD t vss...power supply voltage.

Claims (9)

[Claims] (1) In a logic circuit that outputs an input signal from one logic signal source, a signal with the same logic value and a signal with the opposite logic value, the input signal from the logic signal source and the opposite logic value are output. A logic circuit comprising: a first logic gate circuit that outputs a signal; and a second logic f-) circuit that outputs a signal having the same logic value as the input signal from the logic signal source. circuit. (2) The second logic f-) circuit is composed of an even number of series inverters that receive the input signal, and the first logic dart circuit is configured of the same inverter as the input signal among the series inverters. a first NOR, f −, which receives the output of an inverter that outputs a logical value signal and all input signals;
) The logic circuit according to claim 1, characterized in that the logic circuit is comprised of: (3) The first logic dart circuit is composed of one or an odd number of stages of inverters connected in series to which the input signal is input, and the second logic dirt circuit is composed of one or odd stages of inverters to which the input signal is input. and a second NOR1' gate which receives as inputs the output of this inverter and the output of an inverter that outputs a signal with a logical value opposite to the input signal among the inverters of the first logic dart circuit. The logic circuit according to claim 1, characterized in that it is configured. (4) The second logic dart circuit includes an even number of series inverters that receive the input signal, an output of an inverter of the series inverters that outputs a signal with a logical value opposite to that of the input signal, and 3. The logic circuit according to claim 2, further comprising a third NOR dart whose input is the output of the first NOR' dart. (5) According to any one of claims 2 to 4, further comprising an odd number stage or an even number stage series inverter on each output side of the first and second logic dart circuits. The logic circuit described. (6) The second logic dart circuit is composed of an even number of series inverters that receive the input signal, and the first logic dart circuit is composed of an even number of series inverters that receive the input signal, and the first logic dirt circuit has an inverter that has the same logical value as the input signal among the series inverters. a first NAND gate that receives the output of the inverter that outputs the signal and the input signal;
- Claim 1 consisting of
Logic circuit described in section. (7) The first logic r-) circuit is composed of one or an odd number of series inverters that receive the input signal, and the second logic dart circuit includes one or more inverters that receive the input signal as an input. an inverter connected in odd number stages in series, the output of this inverter, and the output of the inverter that outputs a signal with a logical value opposite to the input signal among the inverters of the first logic dart circuit; 2. The logic circuit according to claim 1, wherein the logic circuit is comprised of: 2 NAND darts. (8) The first logic dart circuit has one or an odd number of stages of inverters connected in series to which the output of the second logic dart circuit is input, the output of this inverter, and the first N inverter.
A fourth NORff-) whose input is the output of the AND dart, and one or an odd number of serially connected input gates whose input is the -1 (7) output from the fourth NOR) I'. A logic circuit according to claim 6, characterized in that the logic circuit is characterized by: (9) The first logic dart circuit includes an output of an inverter that outputs a signal having a logical value opposite to that of the input signal among the input signals and the first NA of the second logic dart circuit.
a fourth NOR dart that receives the output of the ND dart;
7. The logic circuit according to claim 6, further comprising one or an odd number of series inverters that receive the output of the fourth NOR dart. (lO) Each of the first and second logic dart circuits
10. The logic circuit according to claim 6, further comprising an odd-numbered stage or an even-stage inverter connected in series on the h output side.