JPS58164045U - integrated circuit device - Google Patents
integrated circuit deviceInfo
- Publication number
- JPS58164045U JPS58164045U JP2607183U JP2607183U JPS58164045U JP S58164045 U JPS58164045 U JP S58164045U JP 2607183 U JP2607183 U JP 2607183U JP 2607183 U JP2607183 U JP 2607183U JP S58164045 U JPS58164045 U JP S58164045U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- register
- time signal
- word time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Calculators And Similar Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案集積回路装置のブロック図、第
′２図はその要部ブロック図、第３図は動作説明に供す
るタイムチャートである。
Ｘ：数値記憶用レジスタ、〔Ｔｏ〜Ｔ１８〕′、〔Ｔ２
〜Ｔ１８〕′、〔Ｔ４〜Ｔ１８，１’ ：有効桁容量
を指示するワードタイム信号、ＮＣ１，ＮＣ２：外部端
子、ＣＯ：タイミングカウンタ、ＫＤＣ：切換え用デコ
ーダ。Figure 1 is a block diagram of the integrated circuit device of the present invention.
2 is a block diagram of the main part thereof, and FIG. 3 is a time chart for explaining the operation. X: Numerical storage register, [To~T18]', [T2
~T18]', [T4~T18,1': Word time signal indicating effective digit capacity, NC1, NC2: External terminal, CO: Timing counter, KDC: Switching decoder.
Claims (1)
するワードタイム信号を発生する信号発生手段とを含む
演算装置用の集積回路装置において、 上記ワードタイム信号のパルス幅を切り換えるための外
部端子を設け、該外部端子への入力によって上記信号発
生手段を制御して上記ワードタイム信号のパルス幅を切
り換え、上記レジスタの有効桁容量を増減できるように
したことを特徴とする集積回路装置。[Claims for Utility Model Registration] An integrated circuit device for an arithmetic unit including a register for storing numerical values and a signal generating means for generating a word time signal specifying the effective digit capacity of the register, comprising: a pulse of the word time signal; An external terminal for switching the width is provided, and an input to the external terminal controls the signal generating means to switch the pulse width of the word time signal, thereby increasing or decreasing the effective digit capacity of the register. integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607183U JPS58164045U (en) | 1983-02-23 | 1983-02-23 | integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607183U JPS58164045U (en) | 1983-02-23 | 1983-02-23 | integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58164045U true JPS58164045U (en) | 1983-11-01 |
Family
ID=30038023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2607183U Pending JPS58164045U (en) | 1983-02-23 | 1983-02-23 | integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58164045U (en) |
-
1983
- 1983-02-23 JP JP2607183U patent/JPS58164045U/en active Pending
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