JPS58163994A - Drive circuit for electrochromism display cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a drive circuit for a lectrochromism display cell.

As display cells for digital display devices, liquid crystal display cells have been widely used, especially in small display devices, because they are of a light-receiving type and consume very little power. However, since liquid crystal display cells use polarizing plates, the display surface is dark, and the contrast changes sharply depending on the viewing angle, so the range of viewing angles that can be viewed well is narrow, and beauty and display quality are also required. This was insufficient as a display cell for a clock or the like. As an alternative display cell, an EC cell is being developed in which an electrochromic (hereinafter abbreviated as EC) material, which develops and fades color through an electrochemical reaction, is used for the display electrode. EC cell does not require a polarizing plate, so the display surface is bright, and if a white reflector is used, a vivid display of blue and other colors on a white background can be obtained.It also has a high quality display surface, such as good viewing angle characteristics, and is suitable for watches. It is also being developed as a display cell for. By the way, EC cells require a drive circuit different from that of liquid crystal cells due to characteristics such as the display density changing depending on the amount of charge flowing in, the display having memory properties, and slow response speed. Although much progress has been made in the development of drive circuits, the problems that arise during mass production remain unsolved. In other words, in order to complete the display device, at the final stage of the manufacturing process, is it necessary to perform display checks to ensure that each display electrode is operating 1'' and that there are no leaks between the display electrodes?I6C cell Since the response speed is slow, it would take too much time to change the display using conventional liquid crystal display cells.

FIG. 1 is a plan view showing the general appearance of a digital watch as a small digital display device. The display cell 12 in the case 11 has a display electrode 16 that displays a four-digit number in a Japanese letter-shaped pattern consisting of seven segments and a part of the pattern. FIG. 1 shows the time display state in the normal display mode, and 12:38 is displayed. By simultaneously operating the button 14 and the button 15, which are external operating members, the normal display mode and the display check mode are switched.

FIG. 2 is a block diagram showing a display cell drive circuit in a conventional digital display timepiece. A 32768 Hz signal generated by a reference oscillation unit 21 using a crystal oscillator is frequency-divided by a frequency dividing circuit 22, and a 1-minute clock signal is input to a 1-minute counter 26 to count 11 minutes. The carry signal from the 1 minute counter 26 is input to the 10 minute counter 24 to measure 110 minutes, and the carry signal from the 10 minute counter 24 is input to the hour counter 25 to measure the hour. An input circuit 29 that processes signals from the externally operated switch 8118 and switch S219 outputs a signal to the check mode switching circuit 60 to change the state of the check mode switching circuit 60 when the switches S, 18 and switch S219 are operated at the same time. Switch from normal display mode to display check mode. When the display check mode is entered, the time counter gates 62, 66, and 64 that control the transmission of signals to the one-minute counter 23 and beyond are turned off, and the transmission of time signals is cut off. At the same time, the fast forward clock gate 61 is turned on, and the 2t from the middle of the frequency dividing circuit 22 is turned on.
lz fast forward clock signal is 1 minute counter 26.10
Input to the minute counter 24 and 1 o'clock counter 25, and increment the contents by 1. Each counter 26.24.
The contents of 25 are converted into a 7-segment drive...11 signal that displays numbers by the decoder driver 26, 27, and 28, and then displayed in the hour digit 67, 10 minute digit 68, and 1 minute digit 39 of the display cell 66.
to drive. Therefore, in the display check mode, each digit of the display cell 66 is incremented simultaneously by the 05 second clock, allowing the display function of the display cell to be checked in 5 seconds.

Above, the fast forward clock signal was input to the time counter, but the same function can be provided by inputting it to the alarm counter or chrono counter in a multi-function watch.

FIG. 3 is a pattern diagram showing a change in display at an arbitrary display digit of the display cell in the display check mode. 0
By sequentially changing the display from 9 to 9, it is possible to check whether there are any disconnected segments or short-circuited segments.

In the conventional display check method described above, if the display cell has a quick response such as a product display cell, the display can be sufficiently identified even if the fast-forward clock signal is set to 2 Hz, so the display check is performed. can be done. However, EC cells have a slow response time and require 1 second to turn on and off, and furthermore, due to voltage limitations inside the EC cells and power supply constraints for small display devices such as wristwatches, there are restrictions that make it impossible to turn on and off at the same time. The fast-forward clock signal is about 0.5Hz, and it takes 2 times to check the display once.
0 seconds is required. Display checks in the inspection process are
Since it depends on the inspector's visual inspection, it takes 20 seconds to check the display of one display cell, which is a big burden in terms of man-hours, which causes the cost to be higher than that of liquid crystal display cells. This was an obstacle in the practical application of the technology.

The present invention aims to provide an EC cell drive circuit that can complete a display check in a short time in a display device using an EC cell with a slow response speed.

FIG. 4 is a block diagram showing an embodiment of a display cell drive circuit in a digital display timepiece according to the present invention. Reference oscillator 21, frequency divider circuit 22.1 minute counter 26.10
The construction and function of the minute counter 24, hour counter 25, and time counter gates 32, 63, and 34 are the same as in the conventional example shown in FIG. Furthermore, the externally operated switches 5118 and S219, the input circuit 29, and the check mode switching circuit 60 are the same as in the conventional example, but the output of the check mode switching circuit 30 is sent to the fast forward clock gate 61 and the time counter gate 62, 66, 64. In addition to the input, in this embodiment, the decoder drivers 46, 47 .
48 is also entered. When the state of the check mode switching circuit 30 becomes the display check mode, the time counter gates 32, 66, 64 are turned off, and at the same time the fast forward clock gate 61 is turned on, so that the fast forward clock signal from the middle of the frequency dividing circuit 22 is applied to the time thread. Each counter 26.2
4. Input to 25 and increment the contents by 1 at the same time. The contents of each counter 26, 24, 25 are input to the decoder driver 46, 47, 48, or when there is an input of the display check mode state from the check mode switching circuit 30, the contents are not displayed as numbers but in the shape of a Japanese character. The decoder driver 46.4 sequentially turns on or off the seven segments according to the progress of the contents of each counter 26.24.25.
It consists of 7.48. These decoder drivers 4
Each display digit of the EC display cell 49 is driven by the drive output of 6.47.48.

Figure 5 shows the EC in the display check mode in the present invention.
6 is a pattern diagram showing a change in display at an arbitrary display digit of a display cell 49. FIG. Figure 5(a) shows the case where the seven segments of the Japanese character are lit up in sequence according to the progress of the contents of the time counters 23, 24, 25, and the numbers in parentheses indicate the contents of the counters. The corresponding display patterns are shown below. The contents of the counter are r8J r
The display pattern for 9J is set so that the counter content is equal to "7" or equal to "0". If each segment is driven '1-' as shown in this embodiment, only the write drive is performed sequentially.

Therefore, even for an EC display cell where write and erase times require approximately 1 second each, the fast-forward clock pulse can be set to IHz, meaning that it only takes 7 seconds to check all segments. Therefore, the time can be significantly reduced compared to the conventional display check drive.

Furthermore, if the display density is reduced and the display check is performed, the fast forward chronograph can be set to 2 Hz, so that the display check can be performed in an even shorter time.

FIG. 5(b) shows the case where the seven segments of the Japanese character shape are turned off one after another. The numbers in parentheses indicate the contents of the counter, and the corresponding display number turns are shown below. It is clear that the display check can be done in exactly the same amount of time in this case as well.

FIG. 6 is a block diagram showing another embodiment of the display cell drive circuit in the digital display timepiece according to the present invention. In this embodiment, when the state of the check mode switching circuit 60 becomes the display check mode, a signal is sent to the fast-forward clock gate 31, the fast-forward clock gate 6°1 is turned on, and the fast-forward clock signal from the middle of the frequency dividing circuit 22 is output. is input to a check counter 61 consisting of three stages of Frisoge flops, and the contents are incremented by one. The contents of the check counter 61 are converted by a check decoder 62 into on/off state signals for each display segment. On the other hand, the contents of the time counters 26, 24, 25 are converted by time decoders 63, 64, 65 into on/off state signals for each display segment for each display digit. The output signals of the check decoder 62 and the time decoders 63, 64, 65 are input to display switching circuits 66, 67, 68, and one of them is selected here according to the signal from the check mode switching circuit 30. That is, when the check mode switching circuit 60 is in the time display mode, the time decoders 66, 64, 6
The signal from the check decoder 62 is selected and transmitted to the drivers 69.70, 71 in the display check mode.
I'll tell you. Here, the check decoder 62 decodes the Japanese character 7 according to the progress of the contents of the check counter 61.
It has the function of generating a signal to turn on or off segments in sequence. With this configuration, even in this embodiment, each segment can be turned on or off in sequence as shown in FIG. 5, and the speed can be set arbitrarily by selecting the frequency of the fast-forward clock signal. .

As explained above, if the EC display cell drive circuit according to the present invention is used, the display check of the EC display cell with slow response speed can be completed in a short time, so that the display during the manufacturing process of a display device using the EC display cell can be completed in a short time. This greatly reduces the burden of the checking process, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a general example of a small digital display device;
FIG. 2 is a block diagram of a conventional drive circuit, FIG. 3 is a plan view showing a display pattern in a conventional display check, FIG. 4 is a block diagram of a drive circuit implementing the present invention, and FIG.
FIG. 6 is a plan view showing a display pattern in a display check in a drive circuit embodying the present invention, and FIG. 6 is a block diagram of another drive circuit embodying the present invention. 60... Check mode switching circuit 61...
Fast-forward clock gate 46.47.48... lever driver 61.
...Check counter 62...Chain decoder 66.64.65 Old...Time decoder ~66.67.
68...--Display switching circuit 69.70.71...
...Driver 49... EC display cell Fig. 2 Fig. 3 θ4・l, χry, ′,, (5,'6.U, friend'9° Fig. 4 Fig. 5

Claims (1)

[Claims] In the drive circuit of an electrochromism display cell, which is composed of an electrochromimem material that changes color and disappears through electrochemical reactions, and which displays numbers using 7-segment display electrodes in the shape of a Japanese letter, there are two modes: normal display mode and display check mode. 1. An electrochromic display cell characterized in that the decoder driver is configured to sequentially turn on or off the seven segments at regular time intervals when in the display check mode. drive circuit.