JPS5816342B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 type field effect transistor (hereinafter simply KMO).
8) Logic gate circuit, RO using transistors)
The present invention relates to a semiconductor device for configuring a decoder and the like.

Figures 1 to 3 show the configuration of a mask ROM using a conventional silicon gate E/D (enhancement/teflation) transistor. Figure 1 shows a partial pattern of an integrated circuit that constitutes the ROM. Floor plan, 2nd
The figure is a sectional view taken along the line ■--■ in FIG. 1, and FIG. 3 is an equivalent circuit diagram of FIG. 1.

In the figure, ■1 to ■4 are input lines made of polycrystalline silicon (
0□ is an output line (readout line) made of aluminum.

Further, 1 is a P-type silicon substrate, 2, 3, and 4 are N0 type source layers, 5.6 is an N0 type drain layer, 7 is a gate insulating film made of SiO2, 8 is a thick insulating film made of 5i02, and 9 is a Insulating film made of PSG, 1o and ii are output lines 0□
This is a contact hole for connecting the drain layer 6 and the drain layer 6.

That is, in the configuration of FIGS. 1 and 2, as shown in FIG. 3, the drains of enhancement type transistors T1 to T4 are connected in parallel between the output line 01 and the ground, and the output line 01 is connected to the depletion type load MO8). 12 to form a NOR circuit connected to the power supply VDD.

The transistor T3 has a high gate threshold voltage due to the thick insulating film 8, and is rendered inoperable.

However, the mask ROM having the above configuration has transistors T, , T2 . Contact holes 10 and 11 are required to connect T4, which often causes breakage of the output line 010 made of aluminum and contact failure, and also causes an increase in the area occupied by the chip.

By the way, at present, the capacity of ROM is increasing, and in order to improve the yield etc., the contact hole 10.1 is
1 to eliminate wiring breaks and contact failures, as well as to reduce the chip area. Therefore, it is necessary to fundamentally change the configurations shown in FIGS. 1 to 3.

The present invention has been made in view of the above circumstances, and by using the channel regions of a pair of depletion type MOS transistors as the source and drain of an enhancement type MOS transistor, the chip area can be reduced, and It is possible to omit the contact hole between the type MOS transistor and the enhancement type MO8) transistor, and when it is incorporated into the ROM etc., the pattern configuration of the ROM etc. can be simplified,
In this respect as well, the present invention aims to provide a semiconductor device in which the chip area of a ROM or the like can be reduced.

An embodiment of the present invention will be described below with reference to the drawings.

4 is a pattern plan view showing a part of an MO8 integrated circuit constituting a mask ROM using the semiconductor device of the present invention; FIG. 5 is a cross-sectional view taken along line X-X in FIG. 4; 6
The figure is a sectional view taken along the Y-Y line in FIG. 4.

In the figure, 21 is a P conductivity type silicon substrate, and on one side of this substrate 21 is an N+ (N type high concentration) type layer 22, 2
2. . . . are arranged in a matrix.

These N-type layers 22.22. . . . depression type channel regions 23° 23, . . . are formed between the row direction (lateral direction).

These channel regions 23, 23 . . . . are formed by ion implantation, and are adjacent and opposing N in the row direction with the channel region 23 in between.
This is for forming depletion type transistors in the row direction, with one of the soil layers 22 and 22 serving as a source and the other as a drain.

The depression type channel regions 23, 23. ...
. . . A thin gate insulating film 24□ is provided on each of the channel regions 23, 23 .・・・・・・
. . ., a thin gate insulating film 241 or a thick insulating film 24□ is provided on the substrate 21 between the channel regions adjacent to each other in the column direction.

and the insulating film 24. On 24□ is a gate electrode wiring layer 25□ made of polycrystalline silicon that passes over the film in the column direction.
, 252, 253°...... are provided.

Under these wiring layers, between the depression type channel regions 23 and 230 adjacent to each other in the column direction, one of the regions is a source, the other is a drain, and the substrate 21 located between these regions is a gate region.・Form an MO8) transistor.

However, since the threshold voltage becomes high in the portion where the thick insulating film 242 is formed, it does not operate as an enhancement type transistor.

In the figure, 26.degree.26, . . . is a thick field insulating film forming portion, and 27 is an insulating film made of PSG.

FIG. 7 is a circuit diagram of one output line of a ROM formed using the above structure.

That is, depletion type MOS transistors T2□ to T2 formed in the row direction as shown in FIGS. 4 to 7
The n series circuit 28 is an enhancement type N-channel transistor (load MO) whose gate is supplied with a clock signal.
8) It is connected to the power supply VDD via 29, and the series circuit 30 of depletion type MO8) transistors T3□ to T3n is grounded.

And enhancement type MOS transistor T41~
T4n is configured to bridge between the series circuits 28 and 30.

Further, the series circuit 28 is configured to send out a readout output via an inverter 31.

In FIG. 4, the series circuit 32 of depletion type MO8) transistors T51, T52s... is a circuit for the adjacent output line, and the next depletion type MOS transistor T61 j T
The series circuit 33 of a2 j...... may be used as an adjacent output line, and the series circuit 30 serving as the ground may be shared by the series circuits 28 and 32, but the series circuit 3
3 may be used as the ground line, the series circuits 28 and 30 may be used as a pair, and the series circuits 32 and 33 may be used as a pair.

In this case, the wiring layer 25. between the series circuits 30.32. ．． 25□
At the bottom of ,...... is the enhancement type M.
O8) Since there is no need to form a transistor, the gate insulating film in that portion can be made thicker.

Furthermore, since the gate insulating film of the transistor T43 is formed thickly as shown by the dotted line in FIG. 7, it does not actually form an enhancement type MO8) transistor and is inoperable.

Since this circuit constitutes a ROM, a plurality of the circuits shown in FIG. 7 are arranged in parallel, and the gate electrodes of the corresponding enhancement type transistors between these circuits are not commonly connected. This can also be seen from Figure 4.

Note that in FIG. 7, C is a capacitance parasitically generated at the output end of the MO8 circuit.

Next, a method of manufacturing the ROM having the above structure as an N-channel E/D MO8 integrated circuit will be described with reference to FIG.

First, an insulating film (for example, 5102) 24 is formed on a PW silicon substrate 21 by thermal oxidation or low-temperature vapor phase growth.
There will be 15,000 people (Figure 8a).

Next, the wiring in the ROIVI and the insulating film in the region that will become the transistor are removed using the photoresist as a mask (8th
Figure b).

Next, a thermal oxide film with a thickness of 50% is applied to form a gate insulating film 24□.
After providing 0 to 1200 A (FIG. 8C), in order to obtain a depletion type MO8) transistor, the area that is to become an enhancement type MO8) transistor is covered with a photoresist 41 as a mask, and an N-type impurity (for example, p Perform ion implantation of 13t ions (Fig. 8d). Next, remove the resist 41, and form wiring for address input (drive line) and gate electrodes of enhancement type and depletion type MO8) transistors. For example, after vapor-phase growth of polycrystalline silicon 25, necessary patterning is performed (Fig. 8e: Using this polycrystalline silicon pattern as a mask, unnecessary portions of the gate insulating film 24□ are removed and N-type impurities are formed. A diffusion region is formed.

and a protective film (for example, PSG) 27 for the substrate and wiring area.
is formed by vapor phase growth (FIG. 8f) to complete the formation of the ROM matrix section.

Next, in the circuit operation of FIG. 7, the transistor 29 is turned on by a clock input, and the parasitic capacitance C is precharged. When an address input, for example 254, is selected, the input becomes on level. At the same time, the clock input is turned off.

All of the address inputs of this Shisen are off level, but due to transistor T44 being turned on, the parasitic capacitance C
The charges stored in transistors T21 and T22
T23 T24 T44 Ta2-T3 n
is discharged through the thread path.

FIG. 9 is a timing waveform diagram showing the operation at this time.

on the other hand. When address input 253 is selected, the gate insulating film of the transistor T43 is thick, so the transistor T43 does not turn on level, and the charge stored in the parasitic capacitance C is not discharged and the power supply voltage VDD level.

In the above embodiment, the address input lines 251 to 25n constituting the gate wiring layer of the device of the present invention are made of polycrystalline silicon, but a metal such as aluminum may also be used.

Furthermore, in the embodiment, the ion isoplantation for forming the channel region of the depletion type MOS transistor was performed before the formation of the polycrystalline silicon layer 25, but even if the ion isoplantation is performed after the formation of the layer 25, if the ion acceleration voltage is increased. It is possible.

Further, in the embodiment, the depression type MO8) transistor and the enhancement type MO8) transistor are N-channel type, but they may be P-channel type.

As explained above, according to the present invention, the channel region of the pair of depletion type MO8) transistors is also used as the source and drain of the enhancement type MO8) transistor. This eliminates the need for a contact hole to connect the Enhanced Mendl type transistor and the Enhanced Mendl type transistor, which eliminates disconnections in the wiring, contact failures, and
In addition, when the device of the present invention is incorporated into a ROM, etc. as in the embodiment, a simplified pattern as shown in FIG. It is possible.

[Brief explanation of drawings]

FIG. 1 is a pattern plan view showing a conventional mask ROM, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, FIG. 3 is an equivalent circuit diagram of FIG. A pattern plan view showing one embodiment, FIG. 5 is a sectional view taken along line X-X in FIG. 4, FIG. 6 is a sectional view taken along line Y-Y in FIG. 4, and FIG. 7 is a sectional view taken along line Y-Y in FIG. 4. Figure 8 is a circuit diagram showing a part of the ROM obtained from the same R.
FIG. 9, which is an explanatory diagram of the manufacturing process of the OM, is a timing chart. 21...P-type substrate, 22...N-type diffusion layer, 23...depression type channel region, 24,...gate insulating film, 25□ , 253・
......Gate wiring layer, T2□~T2n,
T3□～T3n・・・・・・Depression type M
O8) Transistor, T41~T4n------
Enhancement type MO8) transistor.

Claims (1)

[Scope of Claims] 1. Enhancement comprising first and second depletion type MO8) transistors, with the channel region of the first depletion type MOS transistor as the source and the channel region of the second depletion type MO8) transistor as the drain. A semiconductor device characterized by comprising a type MO8) transistor. 2- a first conductivity type semiconductor layer, and first and second semiconductor layers of a second conductivity type provided opposite to each other on one side of the layer;
third and fourth semiconductor layers of a second conductivity type provided opposite to each other in the first conductivity type semiconductor layer along with the first and second semiconductor layers; and the first and second semiconductor layers. a depression type channel region provided between the layers, with one of these layers serving as a source and the other serving as a drain; and a depression type channel region provided between the third and fourth semiconductor layers, having one of these layers serving as a source and the other serving as a drain. and a gate insulating film provided on each of the channel regions and the first conductivity type semiconductor layer between these channel regions, and a conductor layer provided to pass over the insulating film. semiconductor device.