JPS58163298A - Method and apparatus for controlling frequency of driving pulse for pulse motor - Google Patents

Abstract

PURPOSE:To eliminate the errors of the quantity of the pulse motor moved by slowly reducing the frequency of driving pulses up to the same extent as that in case of starting just before stopping and stopping driving pulses while stopping the pulse motor. CONSTITUTION:Pulse number corresponding to the total quantity of the pulse motor 24 moved is set to a register section 1. Half the number of pulses set is registered to a register section 2. When start pulses are applied to an input terminal 3, an up-down counter 4 starts up-count, and outputs from the counter are inputted to a pulse motor drive circuit 23 through a converting circuit 11 and an AND circuit 21. The frequency of pulses from a V/f converting circuit 10 is reduced slowly just before stopping, the AND circuit 21 is closed by outputs from a comparator 8 when the total quantity of the pulse motor 24 moved reaches set value, and outputs to the pulse motor drive circuit 23 are stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for controlling the frequency of drive pulses for driving a pulse motor. More specifically, the frequency of the drive pulse of the pulse motor is increased sequentially at startup, constant at steady state, and Fi
This relates to a frequency control method and device in which the frequency is gradually decreased.When driving a pulse motor with drive pulses, if a drive pulse with a large frequency is suddenly supplied at the time of startup,
Due to the characteristics of a pulse motor, it is not possible to perform an operation corresponding to the drive pulse until a predetermined rotational speed is reached. In general, as shown in Figure 1, when starting at 10 o'clock, for example, f=
A low frequency drive pulse of about 200 pps is supplied, and f is increased sequentially to reach, for example, 5000 ppm at 11 o'clock.

However, even if the supply of drive pulses is stopped to stop the motor at 12 o'clock, the pulse motor does not stop immediately, but due to the rotational inertia of the rotor, it stops at t8 after a certain period of time has elapsed.

At this time, the total amount of movement of the pulse motor is the first @ diagonal part (
Since it corresponds to the sum of the areas of AJ (however), the shaded area 1) and 3) from time t3 to time t3 is the amount of movement without the drive nozzle, resulting in a difference in wA.

In order to eliminate this slight difference, the present invention uses a simple circuit to adjust the frequency of the drive pulse to the same t as at the time of starting even just before stopping.
= 200 ppm It is gradually decreased to 81t, and the Norx motor is stopped at the same time as the drive pulse is stopped.

Hereinafter, one embodiment of the present invention will be explained based on FIG. 2, FIG. 3, and FIG. 4. In FIG. The second register section (1) is used to convert a number into a binary code and shift the number one digit to the right, that is, convert the set pulse number into a binary code. o(3) to which the second register section (2) for storing
) is an input terminal for inputting a start pulse, and this input terminal (3) is connected to the reset side of an up/down counter (4) that outputs the contents of the counter as a binary code, and is also connected to the flip-flop circuit +51. connected to the reset side input terminal of the The Q output and the Q output of the flip-flop circuit (5) are the first and second outputs, respectively.
First and second NAND circuits as gate circuits +61 (
The output sides of the first and second NAND circuits +61 (7) are connected to the input terminals of the up/down counter (4) for the up command and the down command, respectively. The output side of the up/down counter (4) and the output side of the second register section (2) are connected to the input side of a comparator (8).
The output side of 8) is connected to the set side input terminal of the flip-flop circuit (5). On the output side of the up/down counter (4), there is a D/A converter (9) that converts the digital output into an analog lid, and a D/A converter (9) that converts the output voltage of the D/A converter (9) into a frequency. A conversion circuit 6D consisting of a V/f conversion section Q (I) which clamps and outputs at a certain upper limit frequency is also connected. current source a'
aas, a changeover switch α for selectively switching these constant current sources HI, a capacitor, and a ■/f conversion circuit αQ. oQIJ, which is configured to be switched to contacts +II and (II) by the Q and Q outputs of the pull-up circuit (5), respectively, is a constant voltage supply terminal from the D/A converter (9).

The output side of the pulse signal of the conversion circuit αυ is sequentially connected to the pulse motor drive circuit @ and the pulse motor Q4 via an AND circuit 60 as a third gate circuit. The output side of the AND circuit r2υ is also connected to the input sides of the first and second NAND circuits (61(7)). This is an output stop section that detects that the gate has been turned off and sends a rounded signal that closes the gate of the AND circuit.This output stop section is connected to the NOR circuit ( 2), and a NAND circuit (b) whose inputs are the output of this NOR circuit (2) and the Q output of the flip-flop circuit (5), and the output side of this NAND circuit is connected to the AND circuit. It is configured by connecting to the input side of @.

Next, the present invention will be explained in detail.

The number of pulses corresponding to the general IMJ amount of the pulse motor is set in advance. For example, a pulse motor with 1 pulse (2
) is 10 μm and the i-moving lid is 10 steps, the set number of pulses is 1000 pulses. Following this example, the set number of pulses is determined and converted into a binary code 'R', which is an n+1 digit binary code "D duck, D
Assuming that it is represented by DoJ, s-1, D8, . . . D,, DoJ, this is placed in the register section (1). Then, the second register section (2) contains [DIl,D
I%-1,...D6 N-digit binary code [D%, D%-1,...DnsJ] with one digit shifted to the right
is set. For example, if you set the K22 evolution code "ll0IOJ (26 in decimal) in the second register part (1), the binary code 1'-1101" is set in the second register part (2).
J (13 in decimal) is set. That is,
The set number of pulses T is set in the second register section (2) using a binary code. Here, when a start pulse is applied to the input terminal (3), the up/down counter (4) and the flip-flop circuit (5) are reset, and the Q output of the flip-flop circuit (5) is transferred to the first NAND circuit (6). sent to. At the same time, the oscillator of the V/f converter αQ is also detected at the minimum frequency (for example, 200 ppm) with a start pulse, and this pulse signal is sent to the up/down counter (4) via the first NAND circuit (6), where it is Start counting.

The counter output is input to the pulse motor drive TGL via the conversion circuit aυ and the AND circuit, and
Since it is input to the first NAND circuit (6), up-counting is continued. Here, in the conversion circuit aυ, the movable piece αη of the 0-cut switch a4, in which the digital signal is converted into a DC voltage in the D/A converter (9), is a flip-flop circuit (
Since the Q output of 5) is connected to the -10,000 contact rod, the DC voltage from the D/A converter (9) is supplied, and this is charged to the capacitor 0 via the constant current source aa. 0 Therefore, this capacitor a! 9 charging voltage (b)
As shown by the dotted line in Figure 4, 0 increases linearly from Va to Vc in proportion to the passage of time from 1 o'clock at the start.
This charging '#11 voltage M is applied to the frequency (
f), and from the output side of the AND circuit (c), f =
A drive pulse rising linearly from 200 ppm is output, which enters the pulse motor drive circuit (to) to start the pulse motor (2). Charging 4 from T8:00 The drive pulse gradually rises in proportion to the voltage (A), and at 18:00, h hours have passed, f is the highest at 5ooopps K
, l, the output frequency of the v/f conversion circuit ae is 0.
It is clamped at 5000ppm and stabilized at f=5000ppm. On the other hand, the charging voltage (G) of the capacitor aCj is shown by the dotted line in the figure, and the output of (4) is the second register part (2).
If it matches the set number [D%, D s-1, .
When Q disappears, the first NAND circuit (6) is closed and Q output appears. For this reason, the movable piece αη of the changeover switch Q4 of the D/^ conversion part Q(I switches to the other contact wire, the capacitor a!9 starts discharging, and the photovoltaic section 4- voltage (b) is the same as that during charging. At this time, the Q output opens the second NAND circuit ()), so the up/down counter (4) counts down the 8-force drive pulse that enters the down side input. r and decrements the count. It's been 9 T since T1 o'clock.
At 1 o'clock, the charging voltage M becomes Vc, and after passing T, it gradually decreases to less than 1 voltage, which was clamped, and accordingly, the frequency of the drive pulse output from the conversion circuit (Ill) also changes. OT begins to fall below $000ppm
At 2:00 p.m., which is a long time after winning, the charging voltage becomes VS.
, the frequency of the drive pulse becomes 200 ppS and becomes 1, and the content of the up/down counter (4) becomes 0, and the output of the NOR circuit (e) of the output stop S@ becomes "1", so the output of the NAND circuit punishment becomes "0", the AND circuit a is closed, and the output to the pulse motor drive circuit Q1) is stopped. Therefore, the pulse motor immediately stops moving.

In the above embodiment, the number of set pulses is relatively large, and the frequency of the drive pulse is clamped before counting the maximum value of T! We have explained nine cases in which the frequency reaches 5000pp@, but even after counting the set number of pulses, the frequency of the drive pulse is clamped at the highest value of 5000pp.
m fC If not delayed, drive pulse frequency (f)
varies in proportion to the charging voltage (g) in a symmetrical mountain shape centered on time T@ in FIG.

In the above embodiment, the output stop section includes a NOR circuit coupled to the output side of the up/down counter, and a NAND circuit whose inputs are the output of this NOR circuit and the Q output of the flip-flop circuit for opening the second gate. However, with such a configuration, when the set drive pulse number is an odd number, an error will occur in the second register section (2), and an error will also occur at the 12 o'clock position of T, and as a result, the amount of movement will be 1 It becomes shorter by the amount of pulse. This degree of error is not a problem in practice, but in order to make it even more accurate, for example, as shown in Figure 5, the output pulse signal of the conversion circuit αυ is reset by the start pulse from the input terminal (3). An up counter (to) that counts up, a comparator (2) that compares the contents of this up counter (to) and the number set in the register section (1) and outputs a coincidence signal, and an output side of this comparator. The output stop section (25a) is connected to the inverter (to) connected to the output stop section (25a).
It may be configured such that a signal for closing an AND circuit is sent from the output side of this inverter. With this configuration, the time when the output is stopped completely coincides with the time when all the set number of pulses have been counted. For example, in the above embodiment, when the set number of pulses is an odd number,
l'-10114 (
The last digit bit is 1, as in decimal number 11), and the binary code placed in the second register section (2) is rlol.
J (5 in decimal), and the output stop signal is l'-10
It came out when it was twice 1J (10 in decimal), and 1
However, in the embodiment shown in FIG. 5, the output stop signal [011J
(11 in decimal) and is a perfect match.

9, T in FIG. 4 is T obtained by subtracting one pulse from the set pulse number, that is, (11-1)XT=5, and the countdown side is reversed earlier than the total movement amount T by T Hals. Also, when the set number of pulses is an odd number, T,
T, which is the addition of 1 pulse to the set number of pulses, i.e. (
11+1) It is almost the same even if you set XT = 6 and reverse to the countdown side T Hals later than T of the candy transfer I amount〇In addition, if the set number of pulses is large, T,
Even if T is made larger or smaller than the total moving amount T by several pulses, it will actually fall within the difference range, so T should be set to be about a fraction of the total set number of pulses.

In addition, in the example of the edging, the case where the frequency change is linear has been explained, but it may be curved like the one-dot chain line or the two-dot chain line in FIG.

Since the present invention is configured as described above, the frequency of the pulse motor driving pulse can be controlled to have predetermined characteristics. That is, the frequency of the drive pulse and its rate of increase and decrease can be made the same when starting and stopping the pulse motor, and the maximum frequency can be controlled to a predetermined frequency characteristic.

Moreover, since no microcomputer is used, ferrous acid is simpler, easier to operate, and less expensive than conventional methods.

[Brief explanation of the drawing]

Figure 1 shows the drive 1 when the conventional pulse motor stops.
FIG. 2 is a block diagram showing an embodiment of the pulse motor drive pulse frequency control device according to the present invention, and FIG. 3 is an electrical diagram showing a specific example of the D/f converter shown in FIG. 2. FIG. 4 is a frequency characteristic diagram of a device according to the present invention, and FIG. 5 is a block diagram showing another embodiment of the present invention. (1)...Second register section, (2)...Second register section, (3)...Start signal input terminal, (4)...
・Up-down circuit, (5)...Flip-flop circuit, (6)...First gate circuit, (7)...Second
Gate circuit, (8)...converter 7 (lator, (9)...
・D/A converter, (IQ...V/f converter, al...
・Conversion circuit, al @a...constant current source, 0◆...changeover switch, a9...capacitor, α...V/f
Conversion circuit, a...movable piece, al0...contact, (to)...voltage supply terminal, Qt...third gate circuit, (c)...pulse motor drive circuit, ... Pulse motor ~ (c) (2sa) ... Output stop section, wire ... Noah circuit, wire ... NAND circuit, - ... up counter, (2) ... comparator, (to )...Inverter〇Applicant General Co., Ltd. Agent Patent Attorney Toshima Furusawa

Claims (1)

[Claims] (1) The drive pulses of the pulse motor are counted, and the voltage increases until it reaches approximately T, which is the number of drive pulses, and thereafter decreases at the same rate. , the drive pulse is increased sequentially from the low frequency to the tube frequency in response to the voltage characteristics during the rise, and when stopped, the drive pulse is increased in response to the voltage characteristics during the fall.1. A method for controlling the frequency of a pulse motor drive pulse in which the drive pulse is sequentially lowered from a low frequency to a low frequency. (2. A method for controlling the frequency of a pulse motor drive pulse, as set forth in claim 1, in which the drive pulse is clamped at a predetermined frequency except for a certain period of time when starting and a certain period of time when stopping. (3) ) In claim 1 or 2, -C1 (T) means that when the number of driving pulses is an even number, that T.
, if the number is odd, add or subtract one pulse and make a round ■
A method for controlling the frequency of a pulse motor driving pulse, comprising: (4) A digitizer section that converts and sets the set drive pulse number set in accordance with the total travel distance of the pulse motor into a binary code, and shifts down the number set in the digitizer section so as to exclude the first digit. an up/down counter that counts as a 7-tup counter in response to a start signal, counts down when it reaches approximately the set number of drive pulses, and outputs the contents of the counter as a binary code; A first gate circuit and a second gate circuit coupled to the up-side input and the down-side input of the up-down counter, respectively, compare the number set in the second register section and the output of the up-down counter to generate a match signal. a flip-flop circuit that sends a signal to selectively open the first iron gate circuit with the start signal and the second gate circuit with the output of the comparator; and an analog output of the up-down counter. exchange to the amount,
A conversion circuit that outputs a pulse motor drive pulse that changes at a frequency corresponding to this analog quantity and is clamped at a constant upper limit frequency is connected to the input side of the conversion circuit, and the output side of the conversion circuit is connected to the output side of the first and second pulse motor drive pulses. A third gate circuit coupled to the input side of the second gate circuit detects that the number of output pulses of the conversion circuit reaches a set number of pulses and sends a signal to the third gate circuit to "close" the gate. a frequency control device for pulse motor drive pulses, comprising: an output stop section that stops the output when the output is stopped; Output 1 1 of the A converter and the D/A converter
A pulse motor drive pulse frequency control device 0(6) comprising a V/f conversion section that converts pressure into frequency and outputs the clamped signal at a certain upper limit frequency. In the description in Section 1, the output stop section includes a NOR circuit coupled to the output side of the up/down counter, and an output of the NOR circuit and (I!T) for opening the second gate circuit.
A pulse motor drive pulse wave number control device consisting of a pulse motor drive pulse and a Nando circuit whose input is a signal and a Nando circuit. (7) Range of % Permission Requests In paragraphs 4 and 5, the output stop section includes an up counter that is reset by a start signal and counts the output signal of the conversion circuit, and the contents of the up counter and the output of the first register section. A frequency control device for pulse motor drive pulses, which comprises a comparator that compares the number of flits and outputs a matching signal, and an inverter coupled to the output side of the comparator. (8) In the claims 4, 5, 6, or 7, the up/down counter is configured to up-count with a start signal, and when the set number of driving pulses is an even number, the number of driving pulses is an even number, or an odd number. When , 1 pulse is added or subtracted, and when T of 9 is reached, the counter is counted down and the contents of the counter are output as a binary code.9 pulse motor drive pulse frequency control device 0