JPS58162149A - Method for encoding error correction - Google Patents

Abstract

PURPOSE:To omit a data period necessary for transmitting a control signal, by using a redundancy code necessary for the encoding and decoding of error correction of main digital data in common. CONSTITUTION:In case of forming parity bits Qm, Pm, a block counter 15 outputs m=0 at first. Subsequently a mode selector for forming Pm is supplied to an ROM14. Synchronously with a word address from a word counter, block addresses 36, 54-126, 18 are successively generated from the ROM14 and applied to an RAM6 through an adder 16. PCM data consisting of 6 words in a total W(36,0), W(54, 1)-W(126, 5) are read out from the RAM16 and a parity P18 is formed in an encoder 11 and written in the RAM6. Subsequently the mode selector is switched to the formation of Qm and block addresses 29, 35-92, 1 are generated and applied to the RAM6 through the adder 16. The encoder 11 forms Q1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction encoding method that makes it possible to transmit control information in addition to main digital data.

A type of signal that is recorded when digital data such as an audio POM signal is recorded and played back by a rotary head tape recorder.

Control information indicating usage etc. is often added. The control information includes a control signal indicating whether the audio signal is stereo broadcasting or Koke Japanese language broadcasting, a control signal indicating whether or not noise reduction processing is applied, and whether or not noise reduction processing is performed and its type. A control signal indicating the number of times the audio channel has been rewritten, a control signal indicating the number of times the audio channel has been rewritten, and a control signal including information for music selection or display.

Conventionally, a control signal is inserted separately from the main digital data, and since the control signal is also relatively important, the control signal is subjected to unique error correction encoding. Therefore, it is necessary to provide a special transmission area separate from the main data, and a unique error correction encoder and decoder are provided for the control signals, resulting in a complicated configuration. Ta.

The present invention is intended to solve these conventional problems. The present invention is an error correction encoding method having an arbitrarily defined redundancy code that is necessary for encoding and decoding.

Hereinafter, an encoding method that uses feedback type cross interleaving and completes with /block, which is an example of such an error correction encoding method, will be described.

For example, an audio POM signal sequence is divided into a predetermined number of samples (
A redundant code for error correction is added to each word (word), a redundant code for error correction is added to this code, an interleazo operation is performed to give a different delay to each of the predetermined number of POM data and the error correction code, and an error detection code is further added. Recording and reproducing with additional information is being carried out. As one such interleaving, a predetermined number of PCs in the first arrangement state
A first redundancy code is added to the M words, a seventh redundancy code is added to a predetermined number of PCM words in the first arrangement state after the interleaving operation, and a seventh redundancy code is added to the second arrangement state after the interleaving operation. Cross-interleaving has been proposed in which a first redundancy code is added to a predetermined number of PCM words in the state and a first redundancy code. Cross-interleaving can improve error correction capability compared to simple interleaving because each word of POM data is included in two sequences that generate a first redundancy code and a first redundancy code, respectively. Feedback type cross interleaving is to feed back the first redundant code to the first arrangement state so that the sequence that generates the first redundant code also includes the first redundant code, and further performs error correction. Your abilities will improve.

Further, by having a block-contained configuration, the recording position is not different for each interleave block, and editing in units of interleave blocks is facilitated.

In other words, the feedback cross-interleaving block-complete error correction encoding method blocks continuous P(3M data in units of (mXn) words) and
Each word of the POM data in the block is included in both the first error correction redundancy code generation sequence and the first error correction redundancy code generation sequence, and each word of the POM data in the block is The generation sequences of the first and first redundant codes for error correction of each word are made to be different from each other, and furthermore, In addition, the first error correction redundancy code is included in the generation series of the first error correction redundancy code.

The error correction encoding method will be described below. FIG. 1 shows the configuration of a feedback cross-interleave block-complete encoder. POM data such as audio POM data is divided into (n words×m blocks)/interleap blocks. W(m +
n ), m indicates the block number within the interleaved block, and n indicates the word number within the interleaved block. First parity data Pm is formed from the data of each block in this interleaved block and the first parity by a (mod, 2) adder (indicated by a white circle).

Further, in FIG. 7, 1 indicates a memory for interleap processing. Memory 1 has a capacity that can store data for /interleaved block,
w (m, o) + W (m, 1)...W (m
. The first parity P is formed including the first parity Q.

-0 The first parity Q is formed including the first parity P.

k=0 However, the block number is calculated as (mod, m). The above two equations define the cross-interleaving conditions.

k=.

That is, (Q, m@Qm+d) is uniquely determined regardless of h. Similarly, (Pm$Pm+d) is uniquely determined regardless of Qm.

is defined by the difference between each term, and the relationship between Pm and Qm is defined by the loss interleave condition. Therefore, each term is determined by substituting the initial value into the 7 terms.

In the above-mentioned cross-interleave condition, if the initial value Qo is set to 0, for example, each parity is determined word by word in the following manner.

-0 to k=0 Here, since the block is complete, the block number is (mod, n), and Ad(mod,
m) = 0! d (block number) exists. At this time, (Q, -gd = Qo, P-gd = P o
). This proof is done as follows.

Here, since (1-θ~(-e-i>>), both 1d and 1d-(k+/)a necessarily contain the same block number seven times. Therefore, (ud, = Q, = 0. Also, since (,8d=0), it becomes =0.

Furthermore, for n POM data series and co POM data series, 0. (D-d), J (D-d) ---
...-1n (D-d), (n0/) (D
-d) A memory 2 is provided which provides each delay (block). This delay also means that the block number is (rn
od, m). Then, (n
+2) Word data is fed to ORO generator 3 and O
An RO code is formed. The ORO code is (n+2)
This is for error detection regarding words.

As mentioned above, in feedback type cross interleaving, λ
The two parities Pm and Qm are determined to be separated by d. Therefore, if d and m are relatively prime, md =
0 (mod, m), m each of Pm, Q, and m are determined. Figure 2 shows (n words x m blocks) /
It shows the relationship between data in feedback cross interleaving when used as an interleaved block.

As described above, in feedback cross-interleaving, the two parities, Pm and Qm, are determined sequentially at intervals of d blocks. Therefore, if the unit delay amount d and the number m of interleaved blocks are relatively prime, (md=0(mod, m)), and m each of Pm and Qm are determined.

In the above description, the initial value Qo is set to 0 for simplicity, but any arbitrary value can be used as the initial value Qo. Therefore, in the present invention, a code representing control information as described above is used as the initial value Qo. In this case, the initial value of the / word is not limited to being made to correspond to the / word of the control signal, but the / unit of the control signal is configured by the initial values of a plurality of words existing in each of a plurality of consecutive interleaved blocks. You can also do it.

Note that if d and m are not relatively prime, that is, (m=aXm
', d=aXd') (m'd=0 (moa, m)), only m' pieces of each parity are determined. However, in this case, a feedback cross-interleaving of a series may be performed by determining a initial values.

Furthermore, as mentioned above, the distance between the word sequences that respectively generate two parities is not limited to the linear feedback type cross interleaving where the word sequences that respectively generate two parities are separated by a distance that is an integral multiple of the unit delay amount d. A nonlinear feedback type cross-interleave configuration may also be used in which the cross-interleaving is not regular.

An embodiment of the present invention will be described below with reference to FIG. 3 and FIG. q. An example of this is the case of nonlinear feedback type cross interleaving.

As shown in Figure 3 (m-θ~/7'1.n=0~S)
C/7! ;xb=10! ;θ word) is an interleaved block. and λ parities Pm r Q
m is determined as follows.

Qm-Pm+ 18$ W (m+3a, o)e W
(m+54+ 1)eW (m+y2,2)(9'
W (ITI+oo, a) $ W GTl+108.4
) of w (il+t'26+ 5) Pm+ls = Qm+1 ■W (m+2s, o)C9W
(m+as, +)eW(m+s1.2)eW(m+66
．． 3) eW (m+vs, eW (m+92.5) and the initial value Q. Finally, use the control data written to the corresponding address in the memory. 2 expressed by the above formula
To form two parities, first write all the PCM data of the /interleaved block to RAM (Random Access Memory), change the block number (block address) m sequentially from 0 to /7'l, A block address that satisfies the cross-interleave condition of the above formula is generated in association with word number n (word address), and the PCM data of the above formula is sequentially read out. Then, the formed parity is written again to the corresponding address in the RAM. Furthermore, when forming an ORO code, parity data and PCM data are read from the RAM to generate the ORO code.

FIG. 9 shows the configuration of the encoder according to the above-described embodiment, and in the same figure, the PCM data of /yg2' is supplied to the input terminal indicated by 4. Further, each of 5 and 6 indicates a RAM having a capacity of (g×/ 7 &) words or more, for example, bits in Cgx2. RAM 5, 6
In one, the block address and word address are incremented and the PCM data from input terminal 4 is taken in. In the other, the address is controlled so as to satisfy the cross interleaving condition and the previous operation is performed. It outputs the PCM data written in the cycle and also takes in, for example, two pieces of parity data formed by the encoder 11. An aRa code formed by a CRC generator in the encoder 11 is added to the PCM data and parity data read from one side of the RAM 5.6, and outputted to the output terminal 12 thereof. In this example,
An ORO code of /B bits is added to 6 words of PCM data and coword parity for each block.

The RAM 5.5 includes a data selector 7. for data switching.
8 and address selectors 9 and 10 for address switching are provided.

Address counter 13 to which word clock OK is supplied
Thus, a block address that increments from 0 to /7'l and a word address that increments from 0 to 5 at each block address are formed. In the illustrated example, RAM
This address is supplied to 5, and the PCM data is stored in RAM.
5 is written.

In addition, when forming two parity data, the initial value, for example, Q, as shown in the above formula. using (P
18→Q1→P19→Q2→P2o-+Q3→p21
``song'' and two parities of 77S each are determined in order. Each parity is written to the corresponding address of one side of RAM 5.6. In this way, when loss interleaving is performed, the block address is the ROM. 14.
(mod, /7!; ) That is, a /7s block counter 15. (mod, /'75) is formed by the adder 16, and the word address is
It is formed by a g-adic word counter 17 fed with X. The upper g♂ bits of the //♂ bit address code supplied to the 1M5.6 are used as a block address, and the lower 3 bits are used as a word address.

The carry output of the word counter 1γ is supplied to the block counter 15 at a ratio of 7 to a number, and the word address is supplied to the ROM 14. When forming the parities Qm and Pm expressed by the above-mentioned formulas, first, an output of (m-θ) is generated from the block counter 15. At the same time, K and another mode select for forming parity Pm are supplied to the ROM 14. Then, in synchronization with the word address generated from the word counter 17 changing to (θ~7), the data is transferred from the ROM 14 to C3b, left 11.
The block addresses ゜7.2, 90.10g, /2Otsu, /g) are generated in this order and are stored in the RAM via the adder 16.
5 and 6 (RAM 6 in the illustrated example). As a result, W(3s, o), W(54,t
)...W(128,5)(7) A total of 6 words are read out from 6 RAMs, a parity P18 is formed in the encoder 11, and this parity P18 is the corresponding one of the R person M6. written to the address.

This parity P□8 is stored in a register within the encoder 11.

Next, the mode select for ROM 14 is switched to form parity Qm. In this state, the output of the block counter 15 is still O. Then, in synchronization with the change of the word address, (29, 3!;
, 5/, 6 o, 7 g, 92°/) and are given to RAM (i) via the adder 16. As a result, W(29, o), W(311,
1) The POM data of the total word I--.W (92, s) is read from the RAM f3, and in the encoder 11 it is written as (Ql=Pu+$W(29,o)■...mountain-ew(
Parity Q1 is formed by the operation of 92°5)),
This parity Q1 is written to the corresponding address.

Next, the block counter 15 is incremented by the carry output of the word counter 17, so that (m=/). In this state, parity P19 is first formed and then parity Q2 is formed by the same operation as described above. Furthermore, (m=-2) (m=3)... (m=
/'71I), the above operations are repeated and all parities are determined.

Then, the POM data and parity for two interleaved blocks are sequentially read out from the RAM 6, a cRc code for each block of data is formed in the kneader 11, and the transmission data to which this ORO code is added is sent to the output terminal. It will be taken out on 12th. In the next operation cycle, the operations of RAM 6 and RAM 6 are alternated, and the same operation is performed again.

The decoder for the transmission data encoded 11 as described above is not shown in the figure, but regarding its address control,
It is done in the same way as for the encoder. However, in the decoder, a CRO check is first performed, and the result is set as a / bit, and this / bit is written to the RAM for dinterleaving together with the data.

In addition, the second figure is used to explain another embodiment in which the invention is applied to nonlinear feedback type cross interleaving, and as shown in the same figure, (7×/!;0) words / Configure interleaved blocks. Still, two parities are formed using the following formula.

Qm =Pm+t 6$W(m+32.O) W(m+
4s, 1)eW(m+a4.z)(9W('m+so
, a) eW(m-+-96,4)eW(m+x 12.
5) W(m+12s, a)Pm+xa =Qm+2
$W(m+24.o)eW(m-+-zs, 1)('9
W(m+4z, 2)(9W(m+54.a) W(
W(rl+y2.s)eW(m+sa
, a) This parity formation method begins with an initial value Q. Using (P, 6 → Q2 → P18 → Q4 →...
) and determine the parity of even block numbers. Next, using the initial value Ql (P17→Q3→P1.→Q5→...
) and determine the parity of odd block numbers.

That is, another embodiment of the present invention is a case where two cross-interleaved sequences exist. At this time, a control signal can be used as the initial value QOIQI.

As can be understood from the description of the embodiments above, according to the present invention, the redundancy code necessary for error correction encoding and decoding of main digital data is used as a control signal. There is an advantage that it is not necessary to provide a necessary data period, and that powerful error correction encoding can be performed in exactly the same way as for main data without providing an encoder and a decoder only for control signals.

In the embodiment of the present invention described above, parity is used as the error detection and correction code, but other error detection and correction codes such as BOH codes may be used. Furthermore, the write address when writing POM data to the RAM may be controlled so that the arrangement of data in the interleave block is different from the original order to facilitate interpolation and the like.

[Brief explanation of drawings]

1 and 2 are route diagrams showing the relationship between the encoder and data used to explain the present invention, FIG. FIG. 1 is a block diagram showing the configuration of an encoder according to one embodiment of the present invention, and FIG. S is a route diagram showing a data set of interleaved blocks according to another embodiment of the present invention. 1 is a memory for cross interleaving, 4 is an input terminal for POM data, 5.6 is a RAM, 7.8 is a data selector, and 9 and 10 are address selectors. Agent Masato Sugiura 19- 256-

Claims (1)

[Claims] An error correction encoding method having an arbitrarily determined redundancy code necessary for encoding and decoding, characterized in that control information is represented by the redundancy code.