JPS58162116A - Limiter circuit - Google Patents
Limiter circuitInfo
- Publication number
- JPS58162116A JPS58162116A JP57045804A JP4580482A JPS58162116A JP S58162116 A JPS58162116 A JP S58162116A JP 57045804 A JP57045804 A JP 57045804A JP 4580482 A JP4580482 A JP 4580482A JP S58162116 A JPS58162116 A JP S58162116A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- voltage
- transistor
- limiter
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/02—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general by means of diodes
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はディジタル通信方式の自己タイミング形再生中
継器に用いるリミッタ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a limiter circuit used in a self-timing type regenerative repeater of a digital communication system.
従来、リミ、り回路としては、ダイオードのスイッチン
グ作用のみで行なうものや、トランジスタのカットオフ
作用のみで行なうものがある。しかし、前者は、増11
m機能を持たないので、増幅器をカスケードに接続して
使用しなければならず、後者は、2段のカットオフ回路
を通さなければならないので累子数が増え、回路規襖が
大きくなυ、実装面積、消費電力に制限が厳しい線路中
継器等においては望ましいものではない。Conventionally, there are limit circuits that use only the switching action of diodes and those that use only the cutoff action of transistors. However, the former increases 11
Since it does not have the m function, amplifiers must be connected in cascade and used, and the latter has to pass through a two-stage cutoff circuit, which increases the number of cumulators and increases the circuit regulation. This is not desirable for line repeaters, etc., where mounting area and power consumption are severely limited.
不発明の目的は上述した欠点を改良することにあ)、簡
単な回路構成で増幅作用全方するリミッタ回路を提供す
ることにある。The object of the invention is to improve the above-mentioned drawbacks, and to provide a limiter circuit that performs all amplification functions with a simple circuit configuration.
本発明の構成について述べると、本発明は、エミッタが
接地されたトランジスタのコレクタと正電源間に負荷が
接続され、前記正電源とアース間に2個の抵抗が同列に
接続され、前記2個の抵抗の接続点が前記トランジスタ
のベースに接続されるとともにダイオードのアノードに
接続され、前記ダイオードのカソードとアース間に抵抗
が接続され、前記ダイオードのカソードが入力端子に、
また前記トランジスタのコレクタが出力端子に接続され
たリミッタ回路である。Describing the structure of the present invention, a load is connected between the collector of a transistor whose emitter is grounded and a positive power supply, two resistors are connected in parallel between the positive power supply and the ground, and the two resistors are connected in parallel between the positive power supply and the ground. A connection point of the resistor is connected to the base of the transistor and an anode of the diode, a resistor is connected between the cathode of the diode and ground, and the cathode of the diode is connected to the input terminal,
Further, the collector of the transistor is a limiter circuit connected to an output terminal.
以下本発明を実施例によシ図面を鯵照して説明する。The present invention will be explained below by way of examples and with reference to the drawings.
第1図は本発明の実施例回路図を示し、第2図は第1図
中の各点の波形を示す図である。FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms at each point in FIG.
第1図において、ダイオード2は抵抗1と抵抗3を介し
正電源によシ順方向にバイアスされているので、入力無
信号の時は常時オン状態である。In FIG. 1, diode 2 is forward biased by a positive power supply via resistor 1 and resistor 3, so it is always on when there is no input signal.
次に入力端子に接続されたa点の電圧をv&、ダイオー
ド2のアノードに接続されたb点の電圧をvbとする。Next, let the voltage at point a connected to the input terminal be v&, and the voltage at point b connected to the anode of diode 2 be vb.
まず第2図aの実線または破線で示すような波形の入力
電圧が入力信号となった時には、vaはその入力信号波
形と同じに変化する。First, when an input voltage having a waveform as shown by a solid line or a broken line in FIG. 2a becomes an input signal, va changes in the same way as the input signal waveform.
この時%vEL<vbなる時間飴域ではダイオード2は
オン状態であシ、va≧vbなる時間知識ではダイオー
ド2はオフ状態である。入力信号は。At this time, the diode 2 is in the ON state in the time range where %vEL<vb, and the diode 2 is in the OFF state in the time range where va≧vb. The input signal is.
ダイオード2がオン状態の時には、ダイオード20順方
向電圧降下分だけクランプされてb点に表われ、b点の
電圧波形は第2図すに示すようになる。次にb点の電圧
波形はトランジスタ6の入力3−
信号となる。ここでトランジスタ6の動作点は。When the diode 2 is on, the forward voltage drop of the diode 20 is clamped and appears at point b, and the voltage waveform at point b becomes as shown in FIG. Next, the voltage waveform at point b becomes the input 3- signal of transistor 6. Here, the operating point of transistor 6 is:
抵抗3,4によ、6b点の電圧波形が任意のレベル以下
になるとカットオフになるように設定されているので、
そのレベル以上の波形電圧のみが増幅されて負荷5に表
われる。従って0点のtIE波形は第2図Cのようにな
る。Resistors 3 and 4 are set so that the cutoff occurs when the voltage waveform at point 6b falls below a certain level.
Only waveform voltages above that level are amplified and appear on the load 5. Therefore, the tIE waveform at point 0 is as shown in FIG. 2C.
以上に説明したように5本発明によれば、トランジスタ
6の増幅、カットオフ作用とダイオード2のスイッチン
グ作用によシ、増幅作用を有するリミッタ回路を簡単な
回路で構成できるので1回路の笑装面積、消費電力等に
制限の厳しい線路中継器等にきわめて適したリミ、り回
路が得られる。As explained above, according to the present invention, a limiter circuit having an amplification effect can be constructed with a simple circuit due to the amplification and cutoff effect of the transistor 6 and the switching effect of the diode 2, so that it can be implemented as a single circuit. A limit circuit can be obtained that is extremely suitable for line repeaters, etc., which have severe restrictions on area, power consumption, etc.
第1図は本発明の実施例回路図を示し、第2図は第1図
中のa点、b点、0点の電圧波形を示す。
なお、図面に使用した符号はそれぞれ以下のものを示す
。FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 shows voltage waveforms at points a, b, and 0 in FIG. Note that the symbols used in the drawings indicate the following.
Claims (1)
間に負荷が接続され、前記正電源とアース間に2個の抵
抗が直列に接続され、前記2個の抵抗の接続点が前記ト
ランジスタのベースに接続されるとともにダイオードの
アノードに接続され、前記ダイオードのカソードとアー
ス間に抵抗が接続され、@記ダイオードのカソードが入
力端子に、また前記トランジスタのコレクタが出力端子
に接続されていることを特徴とするリミ、り回路。A load is connected between the collector of the transistor whose emitter is grounded and a positive power supply, two resistors are connected in series between the positive power supply and the ground, and a connection point of the two resistors is connected to the base of the transistor. and is connected to the anode of the diode, a resistor is connected between the cathode of the diode and ground, the cathode of the diode is connected to the input terminal, and the collector of the transistor is connected to the output terminal. The limit, the circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57045804A JPS58162116A (en) | 1982-03-23 | 1982-03-23 | Limiter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57045804A JPS58162116A (en) | 1982-03-23 | 1982-03-23 | Limiter circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58162116A true JPS58162116A (en) | 1983-09-26 |
Family
ID=12729448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57045804A Pending JPS58162116A (en) | 1982-03-23 | 1982-03-23 | Limiter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58162116A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8482831B2 (en) | 2008-03-14 | 2013-07-09 | Fuji Xerox Co., Ltd. | Optical scanning device and image forming apparatus |
-
1982
- 1982-03-23 JP JP57045804A patent/JPS58162116A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8482831B2 (en) | 2008-03-14 | 2013-07-09 | Fuji Xerox Co., Ltd. | Optical scanning device and image forming apparatus |
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