JPS5816155B2 - Electronic alarm clock stop device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ring-stopping device for an electronic alarm clock equipped with an external operating member, particularly a push button switch, for adjusting the time.

Generally, an electronic alarm clock detects a match between the time content of the clock device and the memory content preset in a storage device, and notifies the user's hearing by emitting a sound from a sounding device such as a buzzer. Conventional ring-stopping devices for stopping the sound of the ringing device include the following.

(b) Equipped with a timer circuit that controls the operation of the ringing device,
The ringing device is configured to set a time span from the operation of the ringing device to the end of the operation of stopping the sound by the timer circuit, and to stop the operation of the ringing device when the time span is exceeded.

(b) A ring stop device that includes a switch that is linked to an external operating member that controls power supply to the ringer, and that stops the operation of the ringer when the switch is opened.

(c) A reference switch is provided in cooperation with a wheel train system that controls power supply to the sounding device, and the operation of the sounding device is stopped by the opening operation of the reference switch as the wheel train system rotates. A noise-stopping device.

Here, in the ring stopping device according to (a) and (c) above, the ringing device continues to emit the sound for a predetermined period of time from the operation of emitting the sound to the end of the operation in which the sound stops. For example, When an electronic alarm clock suddenly emits a sound in a place where it should not disturb others, such as during a meeting or a lecture, it has the disadvantage that it cannot stop the sound at the constellation. 1. Also, in the case of the ringing device described in (b) above, when the user confirms the sound coming from the electronic alarm clock, the user opens the switch linked to the external operating member to stop the ringing device. The practice was to stop the movement, that is, to stop the sound.

Even in this case, when the electronic alarm clock suddenly emits a sound in a place where it should not disturb others, such as during a meeting or lecture, it is still desirable for the constellation to stop the sound by operating the external operating member. Ta.

As a noise suppressing device that satisfies such demands, attention can be paid to the excellent operability of the one-touch operation of the push-button type external operation member.

However, a conventional electronic alarm clock equipped with a push-button external operating member for adjusting the time, but with a dedicated push-button external operating member placed in the watch case as a ring-stopping device, has the following drawbacks: .

In other words, when the electronic alarm clock emits a sound and operates the external operating member for stopping the sound, the user visually confirms the position of the external operating member for time adjustment and the external operating member for stopping the sound. It is necessary to press the external operation member for stopping the sound, which requires a certain amount of time, and it is not possible to press the external operation member after confirming the sound in the constellation.

It is clear that if the user were to press a constellation for visual confirmation of sufficiency, this would cause an erroneous operation in which the external operating member for time adjustment would be pressed by mistake.

In addition, it goes without saying that providing an external operating member specifically for stopping the alarm clock from ringing would be costly.
Particularly in the case of a wristwatch, there is a drawback in that the space is severely limited, and the arrangement of each external operating member becomes narrow, resulting in significantly poor operability.

In view of the above-mentioned drawbacks, an object of the present invention is to provide an electronic alarm clock that has excellent operability by using a push-button external operation member for adjusting the time without providing a dedicated external operation member for stopping the ringing. The purpose is to provide a locking device.

Hereinafter, specific examples of the present invention will be explained based on the drawings.

FIG. 1 is a plan view showing the electronic alarm wristwatch of the present invention.

In Fig. 1, reference numeral 1 indicates the entire electronic alarm wristwatch, and this electronic alarm wristwatch 1 includes a display section 2 composed of a liquid crystal display device, an external operating member A for adjusting the time, and an external operating member A for adjusting the minutes. An external operation member B and an external operation member C for selection for switching between an alarm operation display and a clock operation display are arranged.

These external operating members A, B, and C are all push buttons of a self-returning mechanism, and are interlocked with push button switches A i, B-1, and C-1, which will be described later in FIG.

Further, the display section 2 includes an hour display section 2a, a minute display section 2b, and an alarm operation display section 2c indicated by an (ALM) mark in the figure that is selectively displayed by operating an external operation member C.
and a colon display section 2d that blinks for 1 second.

FIG. 2 is a circuit diagram of the electronic alarm wristwatch 1 according to the present invention.

In FIG. 2, 3 is an oscillation circuit including a relatively high frequency crystal resonator as a frequency standard, and in this embodiment, the oscillation frequency of the oscillation circuit 3 is 32768 Hz.

4 is a frequency dividing circuit, which outputs 32768Hz from oscillation circuit 3.
Fifteen stages of dividers (FFI) to (FFts) are connected in cascade to reduce the frequency of the oscillation signal of IHz to the frequency-divided signal φI of IHz.

Reference numeral 5 denotes a sexagesimal counting circuit which inputs and counts the frequency divided signal φ1 from the frequency dividing circuit 4, and the counting signal φ2 output from the sexagesimal counting circuit 5 normally emits a counting signal with a period of one minute. .

Note that the counting circuit 5 is equipped with a reset terminal indicated by R in the figure.

6 is a gate circuit group for prohibiting carry, and this gate circuit group 6 includes an AND gate 6a including a negative input terminal, and an O
It is composed of an R gate 6b and an AND gate 6C, and in normal clock operation, the count signal φ1 from the counting circuit 5 is
is supplied from the AND gate 6a to the input of the counting circuit 7 via the OR gate 6b.

Reference numeral 7 denotes a sexagesimal counting circuit configured by cascadingly connecting a decimal counting circuit for counting in units of 1 minute and a hexadecimal counting circuit for counting in units of 10 minutes. φ3 emits a count signal with a period of one hour during normal clock operation.

8 is a gate circuit group for prohibiting carry, and this gate circuit group 8 includes an AND gate 8a including a negative input terminal and an OR gate 8a.
It is composed of a gate 8b and an AND gate 8c, and in normal clock operation, the counting signal φ3 from the counting circuit 7 is supplied from the AND gate 8a to the input of the counting circuit 9 via the OR gate 8b.

Reference numeral 9 denotes a hexadecimal counting circuit including a decimal counting circuit that counts in units of 1 hour and a binary counting circuit that counts in units of 10 hours.

In addition, the gate circuit groups 6 and 8 supply the frequency-divided signal φl of the frequency dividing circuit 4 to the counting circuit 7 or the counting circuit 9, and also supply the frequency-divided signal φl from the frequency dividing circuit 4 to the counting circuit γ from the counting circuit 5 to the counting circuit γ. The negative input terminals of the AND gates 6a and 8a are connected to one end of each input terminal of the AND gates 6c and 8c so as to prohibit the supply of the counting signal φ2 from the counting circuit 7 to the counting circuit 9 or to prohibit the supply of the counting signal φ3 from the counting circuit 7 to the counting circuit 9. and is also connected to the reset terminal of the counting circuit 5.

Note that the other ends of the respective input terminals of the AND gates 6c and 8c are connected to be supplied with the frequency-divided signal φ1.

Reference numeral 10 denotes a display switching circuit which, depending on the logic level [0 or (1)] of the designated terminal 10a, displays the time contents inputted by the line group γa from the counting circuit 7 and the line group 9a from the counting circuit 9, and the memory described later. Line group 29a from circuit 29
and the storage contents inputted from the line group 31a from the storage circuit 31, and the output thereof is sent to the line 10c.

11 is a decoder, a driver, and a display section 2 shown in FIG.
A display means consisting of a liquid crystal display device consisting of:
This display means 11 includes a line 11a connected from a designated terminal 10a to supply a frequency-divided signal φl for blinking the colon display section 2d for one second, and for lighting and extinguishing the alarm operation display section 2c; The display sections of the decoder and driver are connected in series so that the time display section 2a and the minute display section 2b display the time contents or the stored contents by connecting the group 10c.

A-1 is a push button switch that is linked to external operating member A for adjusting the time, and B-1 is an external operating member B for adjusting minutes.
The push button switch C-1 is a push button switch that is linked to the external operating member C for selection, and the push button switches A-1, 13-1, and C-1 are The contact piece is connected to the logic level [the power supply side of the moon, that is, the positive pole side.

Further, the contacts are connected to the negative pole side of the power supply at logic level [0] via resistors 12, 13, and 14, respectively.

Furthermore, each contact point is connected to each input terminal of the three-man power OR gate 15, and a push button switch A- when sound is generated.
Counting circuit 5. γ, 9 and memory circuit 29
．． The output of the OR gate 15 is connected to one of the input terminals of the AND gates 16, 17, and 18, which constitute prohibition means for prohibiting the contents of 31 from being destroyed. Connected to reset terminal R.

Furthermore, the set terminal S of the R-8 type flip-flop 19
is connected to the other of the input terminals of the AND gates 16, 17, and 18.

In addition, OR gate 15, flip-flop 19 and AN
The D gate 36 constitutes an alarm control means, and when the output signal φ4 based on the coincidence detection from the comparison circuit 32 is output, the push button switches A i, B-1,
C-1 or a combination thereof is configured to stop the sound emitted from the piezoelectric buzzer 40. 20.21.22 is a three-man power A including two negative input terminals.
ND gate, when the electronic alarm watch 1 is in normal watch operation with no sound being emitted, the user accidentally presses multiple external operating members A, B, and C at the same time.
Time contents of counting circuits 6 and 9 or memory circuit 29 to be described later
．． In order to eliminate so-called malfunctions that prohibit the memory contents of 31 from being corrupted, each output terminal of AND gates 16, 17, and 18 and each input terminal of AND gates 23, 24, and 25 are connected as shown in the figure. .

23.24, 25.26 are AND gates, AND
The output terminal of the gate 20 is connected to one end of the input terminal of the AND gates 25 and 26, the output terminal of the AND gate 21 is connected to one end of the input terminal of the AND gates 23 and 24, and the output terminal of the AND gate 22 is connected to one end of the input terminal of the AND gates 23 and 24. The terminal is a T-type flip.
It is connected to the input terminal T of the flop 27, and the positive output terminal Q of this T-type flip-flop 21 is connected to the other end of the input terminal of the AND gate 2325 and also to the designated terminal 10a.

Also, the negative output terminal Q of the T-type flip-flop 27 is A
28 connected to the other ends of the input terminals of the ND gates 24 and 26 is an AND gate; one of the input terminals of this AND gate 28 is connected to the output terminal of the AND gate 23; Frequency divider circuit 4 on the terminal
It is connected to the final stage output terminal of , and is configured to be supplied with the frequency-divided signal φ1.

29 is a sexagesimal storage circuit including a decimal counting circuit and a hexadecimal counting circuit, which stores the memory contents of the minute and time of the alarm. configured to be set.

Reference numeral 30 denotes a gate circuit group for prohibiting carry, and this gate circuit group 30 is composed of an AND gate 30a including a negative input terminal, an OR gate 30b, and an AND gate 30c. The output terminal of the AND gate 23 and the AND gate t'30a are connected so that the carry is prohibited by the AND gate t'30a when the memory is set by φl.
It is connected to the negative input terminal 0a.

31 is a decimal memory circuit including a decimal counting circuit and a binary counting circuit, and is used to store the memory contents of alarm time and time, and the output terminal of the AND gate 25 is connected to one end of the input terminal of the AND gate 30c. connected to AND gate 3
The other end of the input terminal 0c is connected so as to be supplied with the frequency divided signal φl, and further configured so that the frequency divided signal φl from the AND gate 30C is used to set the memory in the memory circuit 31 via the OR gate 30b. ing.

Reference numeral 32 denotes a comparison circuit, which compares the minute time contents of the counting circuit 7 and the minute memory contents of the memory circuit 29, and further compares the hour time contents of the counting circuit 9 and the time memory contents of the memory circuit 31. The specific configuration of this comparison circuit is shown in FIG.

Here, the time contents of the counting circuits 7 and 9 and the memory circuit 29゜31
When the stored contents match, a logic level (monthly output signal φ4) is generated from the output terminal of the comparator circuit 32 for one minute.

The output terminal of the comparison circuit 32 is connected to one end of the input terminals of an inverter 33 and an AND gate 34.

The output terminal of the inverter 33 is connected to the set terminal S of the R-8 type flip-flop 19, and the other end of the input terminal of the AND gate 34 is connected to the output terminal of an AND gate 35. The input terminals are connected so that the frequency division signal φl and the 1024 Hz division signal φ5 are supplied.

36 is an AND gate, which connects the output terminal of the AND gate 34 and the positive output terminal Q of the R-8 type flip-flop 19.
are connected to each input terminal of the AND gate 34.

Furthermore, the output terminal of the AND gate 36 is connected to the base of a transistor 38 via a resistor 37.

The collector of this transistor 38 is a booster coil 39.
A piezoelectric buzzer 40 is connected in parallel to this booster coil 39, and is connected to the positive pole side of the power supply.

On the other hand, the emitter of the transistor 38 is grounded to the negative pole side of the power supply.

FIG. 3 is a circuit diagram showing a specific configuration of the switching circuit 10 shown in FIG. 2. In FIG.

In FIG. 3, the switching circuit 10 is a minimum unit switching circuit 10 that is a combination of an AND gate 10e, an AND gate NOf including a negative input terminal, and an OR gate 10g.
d is provided for each bit of the counting circuit 7 and the counting circuit 9.

7a-1, 7a-2 partially shown in the figure...
・The input terminals 7a-n indicate connections with each bit line of the line group 7a of the minute counting circuit 7, and the input terminals 29a1.29a-
2...29a n input terminal is minute memory circuit 2
Connections with each bit line of the line group 29a of 9 are shown, and 9a 1, 9a-2...9
The input terminals a-n indicate connections with each bit line of the line group 9a of the time counting circuit 9, 31 a-1, 31
The input terminals of a-2 .

10cm1, 10c 2・-・・・・10cm
The output terminal is line group 1 of the switching circuit 10 in FIG.
It shows 0c.

Therefore, the logic level of the instruction terminal 10a [1 or [0]
Accordingly, the contents of either the counting circuit 7.9 or the memory circuit 29.31 are switched.

FIG. 4 is a circuit diagram showing a specific configuration of the comparison circuit 32 shown in FIG. 2.

In FIG. 4, the comparator circuit 32 includes a gate 32a and INCLUSIVE-OR gates (hereinafter referred to as 1N-OR gates) 32b-1, 32b-2, . . . 32b-m. ), and the input terminals 7a L7a 2...7a-n partially shown in the figure indicate connections with each bit line of the line group 7a of the minute counting circuit 7, 29a-1, 29a-2...2
The input terminals of 9a-n are line group 2 of the minute storage circuit 29.
9a-1 shows the connection with each bit line of 9a.
, 9a2...9a n indicates connection with each bit line of the line group 9a of the time counting circuit 9, 31a-1, 31a-2...31a-n
The input terminals of the time storage circuit 31 indicate connections with the respective bit lines of the line group 31a of the time storage circuit 31.

Therefore, since the time contents and the memory contents of the minute counting circuit γ and the minute memory circuit 29, and the hour counting circuit 9 and the time memory circuit 31 match, the output terminal of the AND gate 32a outputs a one-minute logic level ( The output signal φ4 of 1) is generated.

Based on the above configuration, the operation of the electronic alarm wristwatch 1 will now be described.

First, when the output signal φ4 is not generated from the comparator circuit 32, that is, the time contents of the counting circuits 7 and 9 and the stored contents of the memory circuits 29 and 31 do not match, and the comparator circuit 32 Consider the case where the output is at logic level [0].

At this time, the intermittent ringing signal created by the frequency-divided signal φl and the frequency-divided signal φ5 by the AND gate 35 is
4 is closed, the output terminals of AND gate 34 and AND gate 36 are fixed at the logic level [0].

Therefore, the transistor 38 does not operate and the piezoelectric buzzer 40 does not emit sound.

Furthermore, since the output terminal of the inverter 33 at this time is fixed at the logic level [1], the R-8 type flip-flop 19 is in the set state, and the AND gate 1
6.17.18 will be held.

Therefore, when the push button switch is turned on by operating the external operating member C that is indirectly involved in modifying the contents of the counting circuits 5, 7.9 and the memory circuits 29.30, the AND gate 22 is activated from the AND gate 18. T-type flip-flop 27 is triggered through the T-type flip-flop 27.

By this trigger operation, the logic level of the positive output terminal of the T-type flip-flop 27 becomes the inverse of the logic level before the trigger operation.For example, if the logic level before the trigger operation is [0], the logic level is changed to [1] by the trigger operation. ]
becomes.

As a result, the designated terminal of the switching circuit 10 is at logic level [1
], the stored contents of the memory circuit 29.31 are switched to be displayed by the display means 11, and since the line 11a is also at the logic level (1), the alarm indicated by the (ALM) mark in FIG. Operation display section 2c
is displayed.

This state is the stage before storage is set in the storage circuits 29 and 31.

Next, when the push button switch A-1 is turned on by operating the external operating member A, the AND gates 16, 20, 25
, 30c are both open, and the frequency-divided signal φl is connected to the AND gate 3.
Time memory circuit 31 from 0c via OR game 1-30b
is supplied to the input terminal of the external operating member A.
Since the time memory circuit 31 counts the frequency divided signal φl only during the period in which the user continues to press , the user performs the counting while checking the display contents of the time display section 2a, and when the user's desired display contents are displayed, For example, the pressing operation of the external operating member A is stopped.

This operation completes the time storage setting in the storage circuit 31.

Next, when the push button switch B-1 is turned on by operating the external operating member B, the AND gate 1γ is activated.

21. Both 23 and 28 are open and the branch signal φl is AND
The signal is supplied to the input terminal of the minute memory circuit 29 via the gate 28. At this time, the minute memory circuit 31 counts the frequency divided signal φ1 only during the period when the external operation member B is kept pressed. This is done while checking the display contents on the display section 2b, and when the display contents desired by the user are displayed, the pressing operation of the external operation member B is stopped.

This operation completes the memory settings for the memory circuit 29.

From this state, when the push button switch is turned on again by operating the column operating member C, the T-type flip-flop 2γ is triggered via the AND gate 18, 22, and the positive output terminal Q becomes a logic level (0). The negative output terminal is inverted to logic level [1].

At this time, the switching circuit 10 is switched to display the time contents of the counting circuits 7 and 9 on the display means 11, and the display on the alarm operation display section 2c disappears.

This state is the normal usage state of the electronic alarm wristwatch 1, and if the time contents displayed on the hour display section 2a and minute display section 2b are different from the standard time at this time, the time adjustment is as follows. It is done as follows.

That is, when adjusting the time, when the push button switch A-1 is turned on by operating the external operating member A that is indirectly involved in the time adjustment, the AND gates 16, 20, 26 are turned on.
．． 8c is opened, and the branch signal φl is supplied from the AND gate 8c to the input terminal of the time counting circuit 9 via the OR gate 8b. In order to count the frequency-divided signal φl, the user stops pressing the external operating member A when the display content that matches the standard time is displayed.

This operation completes the time correction of the time counting circuit 9.

Next, for minute correction, when the push button switch B-1 is turned on by operating the external operating member B, the AND gates t17, 21, 24, and 6c open, and the AND gate 24
When the second counting circuit 5 is reset by Since the minute counting circuit 7 counts the branch signal φl during the period, the user stops pressing the external operating member B when the display content that matches the minutes of the standard time is displayed.

This operation completes the minute correction of the minute counting circuit 7.

By the above operations, for example, if the memory contents of the memory circuits 29 and 31 are set to 10:35 as shown in FIG.
9 is a counting circuit 7. The counting progresses as time passes.
When the time content of 9 becomes 10:35, an output signal φ4 of logic level [1] is generated from the output terminal of the comparator circuit 32 for one minute.

Therefore, the intermittent ringing signal created by AND gate 35 is supplied from AND gate 34 through AND gate 36 to the base of transistor 38 through resistor 37.

Therefore, the transistor 38 is switched by this ringing signal, and a back voltage large enough to drive the piezoelectric buzzer 40 is generated in the boosting coil 39, and the piezoelectric buzzer 40 is driven by this back voltage and generates a sound.

At this time, the inverter 33 causes the R-8 type flip
Flop 19 is unset and AND gates 16, 17 and 18 are closed.

When the electronic alarm wristwatch 1 emits a sound in this manner, the following operation is performed to stop the sound.

That is, any one of the external operation members A, B, and C is pressed individually or in combination without selection.

By performing this operation, each external operating member A, B,
Each pushbutton/switch AI, B-1, C1 linked to C
is turned on either singly or in combination, and the R-8 type flip-flop 19 is reset via the OR gate 15, and the R-8 type flip-flop 1
The positive output terminal Q of No. 9 becomes logic level [0].

Therefore, the AND gate 36 is closed, the ringing signal is no longer supplied to the transistor 38, and the piezoelectric buzzer 40 stops sounding.

In addition, each AND gate 16°17.1 constituting the prohibition means
8 has already been connected from the output terminal of the comparison circuit 32 to the inverter 3.
Since the gate is closed via the gate 3, the counting or memory contents of the counting circuits 7, 9 and the memory circuits 29, 31 will not be corrupted due to the above-mentioned ringing stop operation.

On the other hand, the signal at the output terminal of the comparator circuit 32 closes the AND gate 34 after one minute regardless of the presence or absence of the above-mentioned ringing operation, and the signal is sent to the R-8 type flip-flop circuit via the inverter 33.
The flop 19 is set and the memory circuit 29.3 is turned on again.
The timing state is taken until the time contents of 1 and the count contents of counting circuits γ and 9 match.

Although this embodiment has been described with respect to a wristwatch, it is obvious that the present invention can also be applied to electronic alarm clocks such as table clocks.

As described above, according to the electronic alarm clock sound stopping device of the present invention, when the electronic alarm clock emits a sudden sound in a place where it is prohibited to disturb others, such as during a meeting or a lecture, the electronic alarm clock is activated. It is possible to perform a quick and simple operation by pressing multiple external operating members arranged on the clock without selection, making it possible to stop the sound of an electronic alarm clock on a single seat, and also to adjust the time when the sound stops. Even if a switch is pressed in conjunction with each of the multiple external operation members involved in adjusting the clock or alarm time, the inhibiting means prevents the contents of the counting circuit and memory circuit from being corrupted, and the alarm time is not sounded for the first time. It is now possible to use both the stop function and a switch that is involved in corrections and settings.

In addition, since the electronic alarm watch does not require an external operating member or space dedicated to stopping the ringing, design flexibility is given to the arrangement of other external operating members for time adjustment, etc. Even in a wristwatch with restrictions, it is possible to arrange the external operating members at intervals suitable for their operability.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an electronic alarm wristwatch according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an electronic alarm wristwatch according to an embodiment of the invention, and FIG. 3 is a switching circuit 10 shown in FIG. 2.
FIG. 4 is a circuit diagram showing the configuration of the comparator circuit 32 shown in FIG. 1...Electronic alarm watch, A, B, C...
...External operation member, A-1, B-1, C-1...
...Push button switch, 15...OR gate, 10...Switching circuit, 11...Display means, 16-18...AND gate, 19 ...
...R-8 type flip-flop. 20-22...AND gate including negative input terminal, 23-26...AND gate, 32...
...Comparison circuit, 27...T-type flip-flop, 34-36...AND gate, 38...
...transistor, 39...boost coil,
40...Piezoelectric buzzer.

Claims (1)

[Scope of Claims] 1. An oscillation circuit, a frequency dividing circuit that divides the frequency of the oscillation signal from the oscillation circuit, a counting circuit that counts the frequency-divided signal from the frequency dividing circuit, and the contents of the counting circuit are modified. a storage circuit for storing the alarm time; a comparison circuit for detecting coincidence between the contents of the storage circuit and the contents of the counting circuit; and an output signal from the comparison circuit based on the detection of the coincidence. In the electronic watch, the electronic watch is equipped with an alarm means that emits a sound by pressing the plurality of switches alone or in combination when the output signal based on the coincidence detection from the comparison circuit is output. Alarm control means for stopping the emitted sound; and when an output signal based on the coincidence detection from the comparison circuit is being output, the contents of the counting circuit are destroyed by pressing the plurality of switches alone or in combination thereof. What is claimed is: 1. A device for stopping a ringing of an electronic alarm clock, characterized in that it is provided with a prohibition means for prohibiting the alarm clock from ringing. 2. An oscillation circuit, a frequency dividing circuit that divides the frequency of the oscillation signal from the oscillation circuit, a counting circuit that counts the frequency-divided signal from the frequency dividing circuit, a memory circuit that stores alarm time, and a memory circuit that stores the alarm time. a comparison circuit for detecting a match between the content and the content of the counting circuit; an alarm means for emitting a sound based on an output signal based on the detection of the match from the comparison circuit; and a part involved in modifying the content of the counting circuit and the storage circuit. an electronic timepiece equipped with a plurality of switches, in which a sound is emitted from the alarm means by pressing the plurality of switches alone or in combination when an output signal based on coincidence detection is being output from the comparison circuit; an alarm control means for stopping the
Prohibition means for prohibiting the contents of the counting circuit and the memory circuit from being destroyed by pressing the plurality of switches alone or in combination when an output signal based on coincidence detection is being output from the comparison circuit. A device for stopping an electronic alarm clock from ringing, characterized by comprising: