JPS58159353A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a highly reliable wiring for the titled semiconductor device by a method wherein, after the second insulating film has been formed on the back side of a substrate immediately before or immediately after the processing wherein a metal layer will be coated on the first insulating film provided on the surface of the substrate, an unnecessary metal layer is removed, and a desired metal wiring is formed. CONSTITUTION:A metal 9 such as aluminum and the like is coated on the insulating film 8 such as an SiO2 and the like which will be provided on the semiconductor substrate 1 by performing a vapor-deposition method, for example, while at this time, the second insulating film 12 is present on the back side of the semiconductor substrate 1. Then, a resist film 10 is formed using the photoresist such as OMR (negative type) or AZ (positive type) or the like, for example. Subsequently, the unnecessary part of the metal is going to be removed by performing dry etching method, but as the second insulating film 12 exists on the back side of the semiconductor substrate 1, no current coming from the battery flows on the wiring connected to a P<+> insulating region 3, and a desired metal wiring pattern can be formed without accompanying abnormal over-etching or corrosion being in progress. Subsequently, the resist film 10 is removed, and the formation of the metal wiring is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor ff&casing, and relates to a structure and a method for forming a semiconductor integrated circuit on an object before forming an interconnect.

Generally, aluminum mixed with a few percent of aluminum or copper-silicon impurities is used for the metal layer, but as a method for forming this wiring, only one method as shown in Figure 6c has been used in the past. .

That is, in FIG. 1, 1 is a P world conductor substrate, 2 is an n-type epitaxial layer, 3 is a P+ insulating region, and 4Fin+
Collector region, 5 is a P space region, 6 is an n emitter region, 7 is a P+ low resistance space region, 8 is an insulating group such as 8 Ioz, and impurities such as aluminum, copper, silicon, etc. are added on top of this. Aluminum 9 mixed in several percent is deposited by vacuum evaporation or the like (FIG. 1(a)). Next, for example, O
A resist film 10 is formed using a resist such as MR (negative type) or AZ (positive type) (Fig. 1(b)).
), and then unnecessary portions of the gold II& are removed by a wet etching method using a solution such as hot phosphoric acid or a dry etching method using a chlorine gas (FIG. 1(C)).

After that, 10 resist films are removed and the formation of the metal wiring is completed (Figure 1 (a)) @Here, a voltage of several mV to several square meters is generated on the surface where the aluminum metal and the silicon substrate are in contact. occurs (called the battery effect).

For this reason, since the substrate is of P type, the wiring connected to the P+ insulating region 3 receives a current of 11 due to battery action during etching.
flow, aX corrosion etch or corrosion progresses, and in extreme cases, it causes wire breakage.

The present invention aims to eliminate the above-mentioned drawbacks and form highly reliable wiring.

That is, a second insulating film tube is formed on the back surface of the semiconductor substrate immediately before or after the step of depositing a metal layer on the first insulating film provided on the front surface of the semiconductor substrate, and then an unnecessary metal layer is removed. Half body i! which is characterized by removing and forming desired metal wiring! The present invention relates to a method for producing wrinkles.

Hereinafter, embodiments of the present invention will be described with reference to Fig. 2 of the irises. That is, in Fig. 2, 1 is the P conductor board, and 2 is the n
type epitaxial layer, 3 is a door insulating region, 4 is an n+ collector region, 5 is a P base placement, 6 is an n emitter region, 7 is a P+ low resistance base region, 8 is an insulating film such as 8μO1, A metal 9 such as aluminum is deposited on top of this by, for example, a vacuum evaporation method. A feature of the present invention is that the second insulating film 12 is present on the back surface of the semiconductor substrate at this time (FIG. 2(a)). This second insulating film may be formed before the metal 9t. Next, for example, OMR (negative type) or A
Resist film 10 with 7 photoresist such as Z (positive type)
(#I2 figure (b)).

Thereafter, unnecessary parts of the metal are removed by wet etching using a solution such as hot phosphoric acid or dry etching using chlorine-based gas (Fig. 2(C)). ! 12, no current due to the battery action flows through the wiring connected to the P insulating region 3, so that a desired metal wiring pattern is formed without abnormal contact etching or corrosion progressing. Thereafter, the resist film 10 is removed to complete the formation of the metal wiring (FIG. 2(d)).

In this way, it has become possible to form highly reliable metal wiring.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of a conventional wiring metal forming method, in which (a) is a metal deposition process, (b) a resist film formation process, (C) is an unnecessary metal removal process, and (d) is a resist film formation process. This is a film removal process. FIG. 2 is an explanatory diagram showing a wiring metal forming process according to an embodiment of the present invention. (1) is a metal layer deposition process, (b) is a resist film forming process, and (C) is an unnecessary metal removal process. , (d) is a resist film removal step. The symbols in the diagram are 1...P guard conductor board, 2...
...N-type epitaxial layer, 3...P+ insulation region, 4.
...n+collector region, 5...P pace region, 6°...n emitter region, 7...P+low resistance pace region, 8...Pace region of irises 1 Insulating film, 9...
...Metal layer such as aluminum, 10...Resist film, 11...Current flowing due to battery action, 12.
・・・Second insulating film・Static 1 diagram=229

Claims (1)

[Claims] Immediately after direct cutting or Fi to deposit a metal layer on the insulating film provided on the surface of the medium conductor substrate, #I2 is applied to the back surface of the semi-integrated substrate with scissors.
A method for manufacturing a semiconductor device, which involves forming an insulating layer, then removing a metal layer, and forming a metal layer m.