JPS58159068A - Video reproducing device provided with speed modulating circuit - Google Patents

Video reproducing device provided with speed modulating circuit

Info

Publication number
JPS58159068A
JPS58159068A JP4076182A JP4076182A JPS58159068A JP S58159068 A JPS58159068 A JP S58159068A JP 4076182 A JP4076182 A JP 4076182A JP 4076182 A JP4076182 A JP 4076182A JP S58159068 A JPS58159068 A JP S58159068A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
speed modulation
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4076182A
Other languages
Japanese (ja)
Inventor
Hideo Shimizu
志水 秀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4076182A priority Critical patent/JPS58159068A/en
Publication of JPS58159068A publication Critical patent/JPS58159068A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/30Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical otherwise than with constant velocity or otherwise than in pattern formed by unidirectional, straight, substantially horizontal or vertical lines
    • H04N3/32Velocity varied in dependence upon picture information

Abstract

PURPOSE:To reduce considerably the power loss of an output-stage transistor (TR), by deciding the presence or the absence of a synchronizing signal to detect the presence or the absence of a video signal and controlling the operation of a speed modulating circuit by the detection output in a video reproducing device. CONSTITUTION:Only a vertical synchronizing signal is taken out from the synchronizing signal from an input terminal 19 by an integration circuit of a signal deciding circuit 7; and when the video signal exists, a capacitor 30 is charged and discharged, and its potential becomes low; but when the video signal does not exist, the capacitor 30 is held in a high potential because a TR25 is not turned on, and TRs33 and 39 of a controlling circuit 8 are turned off and on respectively, and the output voltage becomes the earth potential, and the base potential of a TR45 of an amplifying circuit 3 of the speed modulating circuit becomes the earth, and the amplifying operation is stopped, and a driving amplifying circuit 4 and an output amplifying circuit 5 in the next stage are stopped. When the synchronizing signal exists, the video signal of an input terminal 1 is supplied to the amplifying circuit 3 through a differentiating circuit 2.

Description

【発明の詳細な説明】 本発明は、速度変調回路を備えた映像再生装置tに関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video reproducing device t equipped with a speed modulation circuit.

速度変調回路で十分な画面の輪郭補償効果を得るために
は、変調コイルに高電圧、大゛蝋流の変a14鴫流8流
す必要があり、変調コイルを駆動するための速度変調回
路出力トランジスタの電力損失は大きなものさなる。特
に、入力映像信号がない場合(無信号入力時)には、速
度変調回路入力信号は高周波成分を含んだノイズ慴号の
みとなり、出力段では前出のノイズ信号を微分した波形
を増幅するため出力段トランジスタの′電力損失はきわ
めて大きなものとなる。また、無信号状態での画面は、
ぎらぎらした好ましくないものとなる。
In order to obtain a sufficient screen contour compensation effect with the speed modulation circuit, it is necessary to flow a high voltage and a large current into the modulation coil, and the speed modulation circuit output transistor to drive the modulation coil. The power loss is significant. In particular, when there is no input video signal (no signal input), the input signal to the speed modulation circuit is only a noise signal containing high frequency components, and the output stage amplifies the waveform obtained by differentiating the noise signal. The power loss of the output stage transistor becomes extremely large. Also, the screen when there is no signal is
The result is an undesirable glare.

従来より無信号入力時の速度変調出力トランジスタの過
大な電力損失および画面のぎらつき現象を防止する手段
としては、出力段の電流を検出し電圧変換することによ
り、この電圧を帰還電圧として用い、速度変調(9)路
のドライブ段に4還をかける方法が行なわれている。こ
の従来の方法では、速度変調回路に負帰還をかけ、変a
l1回路のループゲインが下がるため帰還電圧が大きす
ぎると通常の映像信号入力時に十分な輪郭補償効果が得
られないという問題がある。
Conventionally, as a means to prevent excessive power loss and screen glare in the speed modulation output transistor when no signal is input, the current in the output stage is detected and converted into voltage, and this voltage is used as a feedback voltage. A method of applying a quadruple return to the drive stage of the speed modulation (9) path has been used. In this conventional method, negative feedback is applied to the speed modulation circuit, and a
Since the loop gain of the l1 circuit decreases, there is a problem that if the feedback voltage is too large, a sufficient contour compensation effect cannot be obtained when a normal video signal is input.

また、帰還電圧が小さすぎると無イぎ号入力時に出力段
トランジスタの過大な電力損失を防止できないのは言う
までもない。このため帰還ル−プにリミッタ回路を付加
し、沸還域圧がある設定値以上になった場合のみ負帰還
をかける方法が特公昭56−13064  号公報に示
されている。
Furthermore, it goes without saying that if the feedback voltage is too small, excessive power loss in the output stage transistor cannot be prevented when no signal is input. For this reason, Japanese Patent Publication No. 56-13064 discloses a method in which a limiter circuit is added to the feedback loop and negative feedback is applied only when the boiling region pressure exceeds a certain set value.

しかし、この方式では速度変調回路内で帰還ループを構
成し、無信号入力時の出力トランジスタの過大−力損失
、画面ぎらつきを防止しているが、この方式では無信号
入力時も出力段トランジスタは速度変調動作を行なって
いるため、無駄な峨力が消費されている。
However, in this method, a feedback loop is configured within the speed modulation circuit to prevent excessive power loss and screen glare in the output transistor when no signal is input. Because it performs speed modulation operation, unnecessary force is consumed.

本発明の目的は、速度変調動作が充分になさnるととも
VCwL力損失が低減さnた速度変i91回路を備えた
映像再生装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a video reproducing apparatus equipped with a speed change i91 circuit that can sufficiently perform speed modulation operation and reduce VCwL power loss.

本発明では映1#1^号の有無を判定する手段として同
期信号の有無を判定する回路と、上記偏号判定回路の出
力信号に応じて速度変調回路を動作状態又は非動作状態
に制御する制御回路とが設けられ、これにより映像信号
がないときは速度変調回路が非動作状態となるようにし
たものである。
In the present invention, a circuit for determining the presence or absence of a synchronizing signal is used as a means for determining the presence or absence of the video signal 1#1^, and a speed modulation circuit is controlled to be in an operating state or a non-operating state according to the output signal of the polarization determining circuit. A control circuit is provided so that the speed modulation circuit is inactive when there is no video signal.

以下図とともに本発明を説明する。The present invention will be explained below with reference to the drawings.

図は本発明の一実施例を示す回路図である。The figure is a circuit diagram showing one embodiment of the present invention.

図において、1は映像信号が入力される入力端子、2は
微分回路、6は増幅回路、4は駆動増幅回路、5は出力
増幅回路、6は速度変調用コイル、7は信号判別回路、
8は制御回路である。
In the figure, 1 is an input terminal into which a video signal is input, 2 is a differentiation circuit, 6 is an amplifier circuit, 4 is a drive amplifier circuit, 5 is an output amplifier circuit, 6 is a speed modulation coil, 7 is a signal discrimination circuit,
8 is a control circuit.

まず、信号判別回路7の動作を説明する。入力端子19
からの同期信号は抵抗20、コンデンサ21で構成され
る積分回路22に入力さn1積分回路22の時定数を適
当に選ぶことにより水平同期信号は積分回路22で除去
され、抵抗26を介してトランジスタ250ベースには
垂直同期信号のみが分離され、入力される。垂直同期信
号はトランジスタ25で位相反転され、トランジスタ2
5がオフの期間は電源端子27より抵抗26.28.4
7  を介してコンデンサ30が光重さnl トランジ
スタ25がオンの期間はコンデンサ30の電荷はダイオ
ード29、抵抗47を介して放電される。コンデン  
 4す30の数域時定数を充電時定数より十分小さく選
ぶようにすわば、トランジスタ25のオン期間にコンデ
ンサ30の電荷は全んど抵抗47、ダイオード29ヲ介
して放電されるため、コンデンサ50の電位は比較的低
・−位となる。以上は映像入力信号がある場合の信号判
別回路7の動作である。
First, the operation of the signal discrimination circuit 7 will be explained. Input terminal 19
The synchronizing signal from N1 is input to an integrating circuit 22 composed of a resistor 20 and a capacitor 21. By appropriately selecting the time constant of the n1 integrating circuit 22, the horizontal synchronizing signal is removed by the integrating circuit 22, and then passed through a resistor 26 to a transistor. Only the vertical synchronization signal is separated and input to the 250 base. The phase of the vertical synchronization signal is inverted by transistor 25, and the phase of the vertical synchronization signal is inverted by transistor 25.
5 is off, the resistor 26, 28, 4 is connected to the power supply terminal 27.
During the period when the transistor 25 is on, the charge in the capacitor 30 is discharged via the diode 29 and the resistor 47. condensation
If the time constant in the range of 4 to 30 is selected to be sufficiently smaller than the charging time constant, all of the charge in the capacitor 30 will be discharged through the resistor 47 and the diode 29 during the ON period of the transistor 25, so that the capacitor 50 The potential of is relatively low. The above is the operation of the signal discrimination circuit 7 when there is a video input signal.

次に、無信号入力の場合の動作を説明する。Next, the operation in the case of no signal input will be explained.

無信号入力時には高周波成分のノイズは積分回路22で
除去されるが、周期的な垂直同期信号は得られないため
トランジスタ25はオンしない。
When no signal is input, high-frequency component noise is removed by the integrating circuit 22, but the transistor 25 is not turned on because no periodic vertical synchronization signal is obtained.

従ってコンデンサ30の電位は電源端子27と同電位葦
で充電される。以上により映像入力信号ありの場合、コ
ンデンサ50の電位は比較的低電位に、無信号入力時に
は電源端子27と同電位(高電位)となる。この1圧は
信号判別回路出力信号として次段の制御@路8に入力さ
れる。
Therefore, the potential of the capacitor 30 is charged at the same potential as the power supply terminal 27. As described above, when a video input signal is present, the potential of the capacitor 50 is a relatively low potential, and when no signal is input, the potential of the capacitor 50 is the same potential as the power supply terminal 27 (high potential). This 1 voltage is input to the next stage control line 8 as the signal discrimination circuit output signal.

制御回路8は以下の様に動作する。最初に映像入力信号
ありの場合について説明する。この場合信号判別回路7
の出力電圧が比較的低電位であり、トランジスタ5Sの
ベース電位は判別回路7の出力゛電圧より高く、ダイオ
ード3261オフ状態にある。この結果トランジスタ3
3がオンし、トランジスタ39がオフするためトランジ
スタ39のコレクタ電圧は電源端子55と同電位になる
Control circuit 8 operates as follows. First, the case where there is a video input signal will be explained. In this case, the signal discrimination circuit 7
The output voltage of the transistor 5S is relatively low, the base potential of the transistor 5S is higher than the output voltage of the discrimination circuit 7, and the diode 3261 is in an off state. As a result, transistor 3
Since the transistor 39 is turned on and the transistor 39 is turned off, the collector voltage of the transistor 39 becomes the same potential as the power supply terminal 55.

次に無信号入力時には、既に説明した通りコンデンサ3
0の電位が高電位となる。この時の′1圧がトランジス
タ35のエミッタ・−圧より^くなる様に端子27.3
5の電源電圧を決定しておけば、ダイオード52がオン
となりトランジスタ33はオフ状態となる。この結果、
トランジスタ39がオンとなり、トランジスタ39のコ
レクタ′亀位はアース載位となる。以上の動作により、
制御回路8の出力電圧は、映像入力信号ありの場合電源
端子55の一位に、無信号入力時にはアース載位となる
Next, when there is no signal input, capacitor 3
A potential of 0 becomes a high potential. Connect the terminals 27.3 so that the '1 voltage at this time is higher than the emitter voltage of the transistor 35.
5, the diode 52 is turned on and the transistor 33 is turned off. As a result,
The transistor 39 is turned on, and the collector level of the transistor 39 is grounded. With the above operation,
The output voltage of the control circuit 8 is at the first level of the power supply terminal 55 when there is a video input signal, and at the ground level when no signal is input.

速度変調回路の増幅回路3は抵抗4444.4へ47.
4?、)ランラスタ4飄48で構成される。
The amplifier circuit 3 of the speed modulation circuit is connected to the resistor 4444.4 by 47.
4? , ) Consists of 4 run rasters and 48 pieces.

今までの説明により、映像入力信号がある場合はトラン
ジスタ39の出力域圧が電源端子55の一位となるため
ダイオード40がオフ状態となり、増幅回°路3はトラ
ンジスタ48のベース端より入力される映像信号微分波
形の増4!i!4b作を行なう。
According to the explanation so far, when there is a video input signal, the output range voltage of the transistor 39 becomes the first level of the power supply terminal 55, so the diode 40 is turned off, and the amplifier circuit 3 receives the input signal from the base end of the transistor 48. Increase in video signal differential waveform 4! i! Perform 4b production.

菫た、無信号入力時にはダイオード40がオンとなりト
ランジスタ45のベース電位がアース電位となるため、
増幅回路3は増幅動作を停止する。この結果、次段の駆
動増幅回路4、出力増幅回路5も動作を停止することに
なり、無信号入力時の速度変調回路の動作が自動的に停
止される。
Additionally, when no signal is input, the diode 40 turns on and the base potential of the transistor 45 becomes the ground potential.
The amplification circuit 3 stops its amplification operation. As a result, the drive amplifier circuit 4 and output amplifier circuit 5 at the next stage also stop operating, and the operation of the speed modulation circuit when no signal is input is automatically stopped.

この実施例では制御回路8の出力を増幅回路3に接続し
ているが、接続箇所は増幅回路3に限らず、微分回路2
、駆動増幅回路4、出力増幅回路5のいずれでも同様の
動作が可能であることは百うまでもない。
In this embodiment, the output of the control circuit 8 is connected to the amplifier circuit 3, but the connection point is not limited to the amplifier circuit 3, but also the differentiating circuit 2.
, drive amplifier circuit 4, and output amplifier circuit 5, it goes without saying that the same operation is possible.

以上述べたように本発明によnば無信号入力時には速度
変調回路は動作を停止するため出力段トランジスタの電
力損失は直流バイアス分による損失のみとなり、電力損
失を者しく低減することかり能となる。
As described above, according to the present invention, the speed modulation circuit stops operating when no signal is input, so the power loss of the output stage transistor is only the loss due to the DC bias, which makes it possible to effectively reduce power loss. Become.

また、無信号入力時に速度変調回路が動作を停止するた
め画面のぎらつき障害が発生しない。
Furthermore, since the speed modulation circuit stops operating when no signal is input, screen glare problems do not occur.

さらに、本発明では変調回路出力電流検出による帰還ル
ープを速度変調回路内部に持たないため、映儂信号入力
時に速度変調回路のループゲイン低下により十分な輪郭
補償効果が得られないという弊害もない。
Furthermore, since the present invention does not have a feedback loop inside the speed modulation circuit based on the detection of the output current of the modulation circuit, there is no problem that a sufficient contour compensation effect cannot be obtained due to a decrease in the loop gain of the speed modulation circuit when a video signal is input.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明による速度変調回路を備えた映像再生装置の
一実施例を示す回路図である。 t19・・・入力端子、2・・・微分回路、5・・・増
幅回路、4・・・駆動増幅回路、5・・・出力増幅回路
、6・・・速度変調用コイル、7・・・信号判別回路、
8・・・制御回路。
The figure is a circuit diagram showing an embodiment of a video reproducing device equipped with a speed modulation circuit according to the present invention. t19... Input terminal, 2... Differentiating circuit, 5... Amplifying circuit, 4... Drive amplifying circuit, 5... Output amplifying circuit, 6... Speed modulation coil, 7... signal discrimination circuit,
8...Control circuit.

Claims (1)

【特許請求の範囲】[Claims] 速度変調コイルを用いて電子ビーム走査速度を変調する
ことにより画面輪郭補償を行なう速度変調回路を備えた
映像再生装置において、同期信号の有無を検出する判別
回路と速度変調回路の動作・非動作を制御回路とを設け
、同期信号が検出さnない場合に速度変調動作を停止さ
せることを特徴とする速度変調回路を備えた映像再生装
置。
In a video playback device equipped with a speed modulation circuit that performs screen contour compensation by modulating the electron beam scanning speed using a speed modulation coil, the operation/non-operation of the discriminator circuit that detects the presence or absence of a synchronization signal and the speed modulation circuit is determined. 1. A video reproducing device equipped with a speed modulation circuit, characterized in that the speed modulation circuit is provided with a control circuit, and stops speed modulation operation when a synchronization signal is not detected.
JP4076182A 1982-03-17 1982-03-17 Video reproducing device provided with speed modulating circuit Pending JPS58159068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4076182A JPS58159068A (en) 1982-03-17 1982-03-17 Video reproducing device provided with speed modulating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4076182A JPS58159068A (en) 1982-03-17 1982-03-17 Video reproducing device provided with speed modulating circuit

Publications (1)

Publication Number Publication Date
JPS58159068A true JPS58159068A (en) 1983-09-21

Family

ID=12589599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4076182A Pending JPS58159068A (en) 1982-03-17 1982-03-17 Video reproducing device provided with speed modulating circuit

Country Status (1)

Country Link
JP (1) JPS58159068A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160875A (en) * 1990-10-24 1992-06-04 Matsushita Electric Ind Co Ltd Contour compensation device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613066A (en) * 1979-07-11 1981-02-07 Kansai Paint Co Ltd Production of can for food

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613066A (en) * 1979-07-11 1981-02-07 Kansai Paint Co Ltd Production of can for food

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04160875A (en) * 1990-10-24 1992-06-04 Matsushita Electric Ind Co Ltd Contour compensation device

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