JPS58159046A - Digital phase modulator - Google Patents
Digital phase modulatorInfo
- Publication number
- JPS58159046A JPS58159046A JP4213982A JP4213982A JPS58159046A JP S58159046 A JPS58159046 A JP S58159046A JP 4213982 A JP4213982 A JP 4213982A JP 4213982 A JP4213982 A JP 4213982A JP S58159046 A JPS58159046 A JP S58159046A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- output
- circuit
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/2057—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases with a separate carrier for each phase state
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発−はディジタル過信方式の通信装置に用いられるデ
ィジタル位相変調器Ｋｔ１４するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a digital phase modulator Kt14 used in a digital overconfidence type communication device.
〔従来技ｌｌ０１ｍ判〕
ディジタル過信方式で、位相変調方式は高品質高装置伝
送に適しているため非常によく用いられる方式である。[Prior art 1101m size] In the digital overconfidence method, the phase modulation method is suitable for high quality and high equipment transmission, and is therefore a very frequently used method.
ディジタル位相変調器は回路規模が小さく調整箇所が少
ない等の利点を有するが、従来ＩＣ内部等における遅延
時間のばらつきが出力変調液の位相誤差となる欠点があ
った。従来のディジタル位相変調器を１１１図及び第２
図によってａＷｉ４する。第１ＩＩ０１０１は発振周波
数Ｎ／＊［１ｚ）（搬送周波数Ｉ・の翼僑）なる発振器
であり、その出力信号ｌはムを振幅、−を位相角、ｔを
時間として
マ、＝ム一（２ｔＮ／ｓ重＋リ ・曲間（１）と表わす
ことができる。この信号ｌはＮ分周回路１０２に供給さ
れ、舅分周されて２φ（ｒａｄ）づつ位相の異なる周波
数ｆ・〔厘２〕なるＮ列の信号群２ｔ出力する。第２図
（ａｌ、（ｂ）はそれぞれ４分周回路とその出力波形を
示す。上記Ｎ列（ＩＩ−４）ｊ）からなる信号群２は、
選択回路１０３ Ｋ第１群の入力信号として供給され、
第２群の一一列（＃１〜５ｌａｓｈ ）の入力信号（デ
ータ列）３により、制御され上記１ａ１群の入力信号の
Ｎ列のうち１つが選び出され位相変調波出力信号４とな
る。こうして入力信号データ列に対応した位相変調波４
が出力される。第２図（ａ）、（ｂ）中の図面符号◎は
、４分周回路の２つのフリップ７０ング（Ｖりのトリガ
端子テに印加される所のタイミング（クロック）パルス
を示し、又＊／２（ｒａｄ）づつ位相の変わる位相変調
波■、■、■、■のタイムチャートを示している。一方
前記の位相変調波ｖ４は、
ｖａ ”＝ Ｉｌｓｉｍ（２ｒ／ａｔ ＋２ｚ／ｎ十）
θＥ１）−−−・−（２）と表わすことができ、その振
＠１は、ＩＣ出力であるためほぼ一定となるが、分周回
路および選択回路内部の遅延時間差等による余剰位相項
ノーｍを生じて出力変調波の位相誤差となるので、特に
高速、為密度伝送時に伝送品質の劣化をもたらし問題と
なる。Digital phase modulators have advantages such as a small circuit scale and fewer adjustment points, but conventionally they have the disadvantage that variations in delay time within an IC or the like cause a phase error in the output modulating liquid. The conventional digital phase modulator is shown in Fig. 111 and Fig. 2.
AWi4 according to the diagram. The 1st II0101 is an oscillator with an oscillation frequency N/*[1z) (carrier frequency I), and its output signal l is expressed by M, = M1 (2tN It can be expressed as /s + ri ・song interval (1). This signal l is supplied to the N frequency divider circuit 102, and is divided into two frequencies to obtain a frequency f. A signal group 2t of N columns is outputted. FIGS. 2(a) and 2(b) respectively show the 4 frequency divider circuit and its output waveform. The signal group 2 consisting of the above N columns (II-4)j) is
Selection circuit 103 K is supplied as an input signal to the first group,
It is controlled by the input signals (data strings) 3 of the 11 columns (#1 to 5lash) of the second group, and one of the N columns of input signals of the 1a1 group is selected and becomes the phase modulated wave output signal 4. In this way, the phase modulated wave 4 corresponding to the input signal data string
is output. The drawing symbols ◎ in FIGS. 2(a) and 2(b) indicate the timing (clock) pulses applied to the trigger terminals of the two flipping circuits (V) of the divide-by-4 circuit, and * A time chart of phase modulated waves ■, ■, ■, ■ whose phase changes by /2 (rad) is shown.On the other hand, the phase modulated wave v4 mentioned above is as follows: va ''= Ilsim (2r/at +2z/n +)
It can be expressed as θE1) ---・-(2), and the amplitude @1 is almost constant because it is an IC output, but the surplus phase term no m due to the delay time difference inside the frequency dividing circuit and selection circuit, etc. This causes a phase error in the output modulated wave, which causes deterioration in transmission quality and becomes a problem, especially during high-speed, high-density transmission.
本発明の目的は、従来の欠点１除去するため、新たに、
正しいタイミングを４えるリタイミング−路を付加する
ことによって出方変Ｉｌｌ波の位相を正しく補正して伝
送品質を高めたディジタル位相変調器を提供することで
ある。The purpose of the present invention is to eliminate the conventional drawback 1, and to newly:
It is an object of the present invention to provide a digital phase modulator which can correctly correct the phase of an output variable Ill wave and improve transmission quality by adding a retiming path to obtain correct timing.
本発明は、Ｉｌ送周絖数ｆ・のＮ倍の発振周波数Ｍ／・
〔厘２〕なる発ｍ器と、この発振器の出方信号の周波数
を２以上の２の倍数であるＮ分周し、がっ２ｇ／ｋ（ｒ
ｅｄ）づつ位相の異なるＮ列の信号を出方するＮ分周回
路と、そのＮ分周回路のＮ列の出方信号をＩＩＩＩＦの
入力信号とじかつ一２Ｎ列のデータ【ｍｚＨｏ入力信号
とし、この第２群の入力信号によりｇｔ群の肩列の入力
信号の一つを選び出力する選択−路とを備えたＮ相位相
変ｗｊＩ器において、 ！前記選択−路の出方−路
Ｋｍｍ記録振器出方４Ｍ号をタイ建ンダ信号とするり゛
タイミング（ロ）路をＩＮＲｍｌ！したことを善黴とす
る。In the present invention, the oscillation frequency M/・
The frequency of the output signal of this oscillator is divided by N, which is a multiple of 2 greater than or equal to 2, and is calculated as 2g/k (r
ed) An N frequency divider circuit that outputs N columns of signals with different phases, and the output signals of the N columns of the N frequency divider circuit are combined with the input signal of IIIF, and the 2N columns of data [mzHo input signal, In the N-phase phase shifter wjI equipped with a selection path that selects and outputs one of the input signals of the shoulder row of the gt group according to the input signal of the second group, ! Said selection path output path Kmm recorder output No. 4M is used as a tie build/under signal. Timing (b) path INRml! What you have done is considered good.
ｗｃｓ図は本発明の実施例を示す。前述の位相誤差を持
つ変調波出力信号４は、本発明の特徴であるリタイミン
グ回路１０４ （Ｆ／’Ｆ） Ｋ供給され、前記発振器
１０１の出力信号ｌをクロックとしてリタイミングする
ことにより容易に位相誤差が除去され正しい位相を持つ
出力信号５を得る。第４図ＫＮ−２の場合のりタイミン
グ回路１０４０入出方波形を示す。第４図（１１の入力
信号１ａ、２ａの位相誤差ａｉ）Ｘ、（Ｃ）図の出力信
号１ｂ、２ｂ４Ｄ様Ｋ ａ＋ＯＫ補正される。The wcs diagram shows an embodiment of the invention. The modulated wave output signal 4 having the above-described phase error is supplied to a retiming circuit 104 (F/'F) K, which is a feature of the present invention, and is easily retimed by using the output signal l of the oscillator 101 as a clock. The phase error is removed and an output signal 5 having the correct phase is obtained. FIG. 4 shows input and output waveforms of the timing circuit 1040 in the case of KN-2. FIG. 4 (phase error ai of input signals 1a, 2a in 11)X, output signals 1b, 2b, 4D in FIG.
以上述べたように本発明によれば、簡単なりタイミング
回路を付加するととＫより、位相誤差の発生しないディ
ジタル位相変調器を容易に実現でき伝送品質を為めるこ
とができる。As described above, according to the present invention, by simply adding a timing circuit, it is possible to easily realize a digital phase modulator in which no phase error occurs and improve transmission quality.
第１図は、従来例のブロック図。
第２図（ａ）は、ｗＪ１図の一部分の電気回路図。
第２ＷＪ−）は舅−４０場合のクロックおよび位相変調
波のタイムチャート。
第５図は、本発明の実施例のブロック図。
第４図は、同上０Ｎ−２の場合のタイムチャート。
１０１・・・発振器、１０２・・・分局回路、１０３・
・・選択回路、１０４・・・リタイミング回路、１・・
・発振器出力、２・−ｊｌに１１１Ｆ０４１号入力（＃
１〜参Ｎ）、３・・・第２群の信号入力（参１〜番−Ｓ
Ｗχ４・・・入（出）力信号、５・・・出力信号。FIG. 1 is a block diagram of a conventional example. FIG. 2(a) is an electric circuit diagram of a part of the wJ1 diagram. 2nd WJ-) is a time chart of the clock and phase modulation wave in the case of 舅-40. FIG. 5 is a block diagram of an embodiment of the present invention. FIG. 4 is a time chart in the case of 0N-2 same as above. 101... Oscillator, 102... Branch circuit, 103...
...Selection circuit, 104...Retiming circuit, 1...
・Input No. 111F041 to oscillator output, 2・-jl (#
1 to No.N), 3...2nd group signal input (No.1 to No.-S)
Wχ4...Input (output) signal, 5...Output signal.
Claims (1)
〔勤〕なる発振器と、 この発振器の出力周波数をＮ分周しかつ２ｚ、ＩＮ（ｒ
ａｄ）づつ位相の異なるＮ列の信号を出力するに分周回
路と、 そのＮ分周回路のＮ列の出力信号を第１評の入力信号と
しかつ１ｏ４ＢＮ列のデータを第２群の入力信号として
その第２群の入力信号によ１１群のＮ列の入力信号の１
つを選び出力する選択回路とを備えたＮ相位相変ＩＩ器
において、 前記選択回路の出力に帥記発振器の出力信号をタイミン
グ信号とするりタイミング回路を縦続接続したことｔ％
黴とするディジタル位相変調器。(1) Oscillation frequency Nf・N times the carrier frequency f・
The output frequency of this oscillator is divided by N and 2z, IN(r
ad) A frequency divider circuit that outputs N columns of signals with different phases, and the output signals of the N columns of the N frequency divider circuit are used as the first input signal, and the data of the 1o4BN column is used as the second group input signal. According to the input signal of the second group, one of the input signals of N columns of 11 groups
In an N-phase phase changer II equipped with a selection circuit that selects and outputs one signal, the output signal of the master oscillator is used as a timing signal to the output of the selection circuit, or a timing circuit is connected in cascade.t%
Digital phase modulator with mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4213982A JPS58159046A (en) | 1982-03-16 | 1982-03-16 | Digital phase modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4213982A JPS58159046A (en) | 1982-03-16 | 1982-03-16 | Digital phase modulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58159046A true JPS58159046A (en) | 1983-09-21 |
Family
ID=12627599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4213982A Pending JPS58159046A (en) | 1982-03-16 | 1982-03-16 | Digital phase modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159046A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04328933A (en) * | 1991-04-26 | 1992-11-17 | Fukushima Nippon Denki Kk | Four-phase modulation circuit |
| JPH08125704A (en) * | 1994-10-25 | 1996-05-17 | Fukushima Nippon Denki Kk | Multi-mode phase modulator |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5060173A (en) * | 1973-09-26 | 1975-05-23 |
-
1982
- 1982-03-16 JP JP4213982A patent/JPS58159046A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5060173A (en) * | 1973-09-26 | 1975-05-23 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04328933A (en) * | 1991-04-26 | 1992-11-17 | Fukushima Nippon Denki Kk | Four-phase modulation circuit |
| JPH08125704A (en) * | 1994-10-25 | 1996-05-17 | Fukushima Nippon Denki Kk | Multi-mode phase modulator |
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