JPS58159024A - Wide band signal switching circuit - Google Patents

Wide band signal switching circuit

Info

Publication number
JPS58159024A
JPS58159024A JP57040294A JP4029482A JPS58159024A JP S58159024 A JPS58159024 A JP S58159024A JP 57040294 A JP57040294 A JP 57040294A JP 4029482 A JP4029482 A JP 4029482A JP S58159024 A JPS58159024 A JP S58159024A
Authority
JP
Japan
Prior art keywords
transistor
emitter
base
switch element
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57040294A
Other languages
Japanese (ja)
Inventor
Hideki Kataoka
秀樹 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57040294A priority Critical patent/JPS58159024A/en
Publication of JPS58159024A publication Critical patent/JPS58159024A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors

Abstract

PURPOSE:To improve a crosstalk characteristic in case when a signal is cut off and also power consumption in that case, by using a field effect transistor in a wide band emitter-follower type switching circuit of or a switching circuit using a diode. CONSTITUTION:When a controlling transistor 5 is turned on by controlling a base current of the transistor 5 by the potential of a control terminal 6, a current flows to a resistance 9, and the gate-source voltage of a field effect transistor (FET) 15 is set to reverse bias voltage by a voltage drop generated in the resistance 9. Accordingly, the FET15 becomes a cut-off state, and the current flowing in the resistance 9 becomes a bias current of the emitter of a transistor (TR) 3 and the base of a TR4. As a result, emitter-follower circuits of 2 stages are operated, and a signal is outputted to an output terminal 2. When the TR5 is turned off from the control terminal 6, the FET15 attains to a conducting state, the potential of a connecting point 10 attains the same potential as that of an electric power source terminal 7, and the base-emitter potential of the TR3 and 4 is biased in the reverse direction. Also, the connecting point 10 is grounded in AC.

Description

【発明の詳細な説明】 本発明は広帯域信号スイッチ回路の特性改良に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the characteristics of a wideband signal switching circuit.

従来、広帯域信号スイッチ回路としては、ダイオードの
順方向電流を導通・遮断してそれらの場合のダイオード
のインピーダンスの差を利用するスイッチ、トランジス
タのベースヲ順バイアス、逆バイアスにしたときのコレ
クタ・エミッタ間の導通・遮断を利用するスイッチ、エ
ミッタ・フォロワ動作させたトランジスタのバイアス電
圧全制御してスイッチの働きをさせるもの等がある。こ
のエミッタ・フォロワ形のスイッチは、緩衝増幅器の機
能を持っており、さらに広帯域の特性が良いといった特
徴を持っている。第1図はこのエミッタ・フォロワ形ス
イッチ回路の一例で、破線で囲った101.102がそ
れぞれ1個のスイッチを構成している。ここで1は信号
入力端子、2は信号出力端子、6けスイッチの制御端子
、7は正の電圧を加える電源端子、8は負の電圧を加え
る電源端子である。この例では2人力、1出力(以下で
はル入力、m出力のスイッチをnxmと表示する。)で
あるが、ル×1スイッチとする場合には、nコのスイッ
チを用意し、電源端子7,8と出力端子2を一括接続し
て、出力端子2と正の電源端子7の間に抵抗201を入
れればよく、さらにnxmスイッチどする場合には、n
−mコのスイッチ8i)(1イt4n、1ぎ5)4m)
を用意し、tが等しいスイッチどうしの入力端子1を一
括接続し、ノが等しいスイッチどうしの出力端子2を一
括接続して、さらにそれぞれの出力端子に抵抗201を
7LX1の場合と同様に接続すればよい。各スイッチで
エミッタ・フォロワ動作するトランジスタ3゜4は制御
端子6に加えられた電圧で制御用トランジスタ5を導通
させることにより、抵抗9で適当なバイアスを与え、そ
の結果信号入力端子1に入力された信号が信号出力端子
2艷現れる。また制御端子6の電圧を変えてトランジス
タ5をオフにすると抵抗9には電流が流れなくなり、ト
ランジスタ3のエミッタとトランジスタ4のベースの接
続点10の電位は抵抗11により正の電源端子7と同電
位になり、トランジスタ3.4のベース・エミッタ間は
逆バイアスされる。したがってトランジスタ3.4はエ
ミッタフオロワ動作し々くなり、信号は殆ど伝達されな
くなる。この回路では信号遮断時には、電流消費が殆ど
ない特徴があるが、信号導通時の電流消費増加等を防ぐ
意味で、抵抗11に比較的大きな値を用いるためトラン
ジスタ3のゝ−ス”エミッタ間の容量で漏れた信号は殆
ど減衰することなく、再びトランジスタ4のベース・エ
ミッタ間の容量により出力端子2に漏れ出て、充分な漏
話特性を得ることができない。漏話特性を良くするため
、制御用トランジスタ5を無くし、トランジスタ3.4
を逆バイアスするための抵抗11を第2図の様に新たな
制御用トランジスタ13に置き替えたスイッチ回路が特
公昭52−13708号に示されている。この第2図の
回路では、トランジスタ13により信号遮断時にトラン
ジスタ3,4を逆バイアスにすると同時にそnらの接続
点1oを交流的に接地して漏話特性を良くしている。し
かし、信号遮断時でも、トランジスタ13をオンにする
ための抵抗14を通って流れるベース電流と抵抗9を通
るトランジスタ13のコレクタ電流を消費するという欠
点がある。これら2つの回路から、漏話特性を良くし、
信号遮断時の電流消費を少なくする方法として、第2図
の抵抗9を第1図の様な抵抗9とトランジスタ5を直列
に接続したものに置き替えた回路が考えられるが、トラ
ンジスタ5.13を同時に制御するための新たな回路が
必要となり、回路がかなり複雑化してしまう。また信号
遮断時にもトランジスタ130ベース電流を消費させる
欠点がある。
Conventionally, wideband signal switch circuits include switches that conduct or cut off the forward current of a diode and utilize the difference in impedance of the diode in those cases, and switches that connect the collector and emitter when the base of a transistor is forward biased or reverse biased. There are switches that utilize conduction/cutoff of the transistor, and switches that function as a switch by fully controlling the bias voltage of a transistor operated as an emitter follower. This emitter follower type switch has the function of a buffer amplifier and also has good broadband characteristics. FIG. 1 shows an example of this emitter follower type switch circuit, in which 101 and 102 surrounded by broken lines each constitute one switch. Here, 1 is a signal input terminal, 2 is a signal output terminal, a control terminal for the six switch, 7 is a power supply terminal to which a positive voltage is applied, and 8 is a power supply terminal to which a negative voltage is applied. In this example, it is 2-man power and 1 output (hereinafter, a switch with 1 input and m output will be expressed as nxm), but if you want to use 1 x 1 switch, prepare n switches and use the power terminal 7. , 8 and the output terminal 2, and insert a resistor 201 between the output terminal 2 and the positive power supply terminal 7. Furthermore, when using an nxm switch, the n
-m switch 8i) (1it 4n, 1gi 5) 4m)
, connect the input terminals 1 of the switches with the same t, connect the output terminals 2 of the switches with the same t, and connect the resistor 201 to each output terminal in the same way as in the case of 7LX1. Bye. The transistors 3 to 4 that operate as emitter followers in each switch conduct the control transistor 5 with the voltage applied to the control terminal 6, and apply an appropriate bias through the resistor 9, resulting in the signal being input to the signal input terminal 1. The signal appears at the signal output terminal 2. Also, when the voltage at the control terminal 6 is changed to turn off the transistor 5, no current flows through the resistor 9, and the potential at the connection point 10 between the emitter of the transistor 3 and the base of the transistor 4 is brought to the same level as the positive power supply terminal 7 by the resistor 11. potential, and the base-emitter of the transistor 3.4 is reverse biased. Therefore, the transistor 3.4 tends to operate as an emitter follower, and almost no signal is transmitted. This circuit has the characteristic that there is almost no current consumption when the signal is cut off, but in order to prevent an increase in current consumption when the signal is on, a relatively large value is used for the resistor 11, so that the The signal leaked by the capacitance is hardly attenuated and leaks again to the output terminal 2 due to the capacitance between the base and emitter of the transistor 4, making it impossible to obtain sufficient crosstalk characteristics.In order to improve the crosstalk characteristics, the control Eliminate transistor 5 and replace transistor 3.4
Japanese Patent Publication No. 13708/1983 shows a switch circuit in which the resistor 11 for reverse biasing the oscilloscope is replaced with a new control transistor 13 as shown in FIG. In the circuit shown in FIG. 2, the transistors 3 and 4 are reverse-biased by the transistor 13 when the signal is cut off, and at the same time, the connection point 1o between them is grounded in an alternating current manner to improve crosstalk characteristics. However, even when the signal is cut off, there is a drawback that the base current flowing through the resistor 14 for turning on the transistor 13 and the collector current of the transistor 13 passing through the resistor 9 are consumed. These two circuits improve crosstalk characteristics,
As a way to reduce current consumption when the signal is cut off, a circuit in which the resistor 9 shown in FIG. 2 is replaced with a circuit in which the resistor 9 and the transistor 5 are connected in series as shown in FIG. 1 can be considered. A new circuit is required to control both at the same time, making the circuit considerably more complex. Furthermore, there is a drawback that the base current of the transistor 130 is consumed even when the signal is cut off.

本発明の目的は、前述のような広帯域のエミッタ・フォ
ロワ形スイッチ回路又はダイオードを用いたスイッチ回
路において、電界効果トランジスタを用いることにより
信号遮断時の漏話特性が良く、その時の電流消費を殆ど
零にする回路構成を提供することである。
An object of the present invention is to use a field effect transistor in a broadband emitter follower type switch circuit or a switch circuit using a diode as described above, to have good crosstalk characteristics when a signal is cut off, and to reduce current consumption at that time to almost zero. The purpose of the present invention is to provide a circuit configuration that achieves this.

以下第3図を参照にして、本発明の一実施例を説明する
。1は信号入力端子、2は信号出力端子、3.4はエミ
ッタ・フォロワ動作させるトランジスタ、6は制御端子
で、トランジスタ3,4はトランジスタ5によってバイ
アスを制御される。トランジスタ5のコレクタは抵抗9
を介してトランジスタ3のエミッタとトランジスタ4の
ベース及び電界効果トランジス、り(FET ) 15
のソースに接続点10で接続されている。FET 15
のドレインは正の電圧を与えられる電源端子7に接続さ
れ、ゲートは抵抗16を介してトランジスタ5のコレク
タに接続されている。トランジスタ3のコレクタには正
の電源を、トランジスタ5のエミッタとトランジスタ4
のコレクタには負の電源を供給する。
An embodiment of the present invention will be described below with reference to FIG. 1 is a signal input terminal, 2 is a signal output terminal, 3.4 is a transistor for emitter follower operation, 6 is a control terminal, and the bias of transistors 3 and 4 is controlled by transistor 5. The collector of transistor 5 is resistor 9
through the emitter of transistor 3 and the base of transistor 4 and the field effect transistor (FET) 15
is connected to the source at connection point 10. FET 15
Its drain is connected to a power supply terminal 7 to which a positive voltage is applied, and its gate is connected to the collector of the transistor 5 via a resistor 16. A positive power supply is connected to the collector of transistor 3, and the emitter of transistor 5 and transistor 4 are connected to each other.
A negative power supply is supplied to the collector of .

制御端子6の電位で制御用トランジスタ5のベース電流
を制御し、トランジスタ5をオンとすると、抵抗9に電
流が流れ、抵抗9に生じる電圧降下がFET 15のゲ
ート・ソース間逆バイアス電圧となる。FET 15は
遮断状態となり、抵抗9を流れる電流は、トランジスタ
3のエミッタと、トランジスタ4のベースのバイアス電
流となる。したがって2段のエミッタ・フォロワ回路が
動作し、出力端子2に信号が出力される。この場合の入
力される信号電圧の最小値をvlNmin、トランジス
タ3のベース・エミッタ間電圧をV  オン状態にEE
3  ’ ある−トランジスタ5のコレクタ飽和電圧をV。R5s
at 1電源端子8に与えられる負の電圧をvEF、と
すると、抵抗9にかかる電圧の最小値”R9m1nは、
■R9min ”” vINmin−VBEa  ’C
Es sat  ”EEとなるので、FET15をカッ
トオフとするゲート・ソース電圧の絶対値は、とのV 
 よリモ小さく9m1n 選んでおかなければならない。尚抵抗16は、FET1
5ノケート・ソース間容量がトランジスタ3の負荷とな
る抵抗9に並列に接続されて信号導通時のスイッチの周
波数特性が劣化することを防ぐためのものであり、使用
するFET素子や、スイッチの使用目的によっては省略
できる。
When the base current of the control transistor 5 is controlled by the potential of the control terminal 6 and the transistor 5 is turned on, a current flows through the resistor 9, and the voltage drop generated across the resistor 9 becomes the reverse bias voltage between the gate and source of the FET 15. . FET 15 is cut off and the current flowing through resistor 9 becomes a bias current for the emitter of transistor 3 and the base of transistor 4. Therefore, the two-stage emitter follower circuit operates and a signal is output to the output terminal 2. In this case, the minimum value of the input signal voltage is vlNmin, and the voltage between the base and emitter of transistor 3 is V.
3' - The collector saturation voltage of transistor 5 is V. R5s
If the negative voltage applied to the at 1 power supply terminal 8 is vEF, the minimum value of the voltage applied to the resistor 9 "R9m1n" is
■R9min ”” vINmin-VBEa 'C
Essat ”EE, so the absolute value of the gate-source voltage with FET15 cutoff is V
You have to choose a small 9m1n. Note that the resistor 16 is FET1
This is to prevent the frequency characteristics of the switch from deteriorating when the signal is conductive due to the capacitance between the gate and the source being connected in parallel to the resistor 9 that serves as the load of the transistor 3. It can be omitted depending on the purpose.

制御端子6によりトランジスタ5をオフとすれば、抵抗
9には電流が流れないのでFET 15のゲート°ソー
ス間電圧は零となり、FET 15のドレイン・ソース
間は導通状態となる。従って接続点10の電位は、正の
電圧が与えられる電源端子7と同電位になり、トランジ
スタ3及びトランジスタ4のベース・エミッタ間は逆バ
イアスされる。また接続点10は、交流的に接地される
ため、漏話特性は良くなる。FIT 15にはオン抵抗
の小さい素子を用いたほうが良いことは言うまでもない
。さらにトランジスタ3,4.5はこの状態でオフとな
っているため、信号遮断時の電流消費はそれらのトラン
ジスタの漏れ電流によるものだけでごく僅かとなる。し
かも、第3図の回路構成では、エミッタ・フォロワ回路
を制御するためにトランジスタ5とFBT1502個の
半導体スイッチ素子を用いているが、制御端子6から見
た制御方法は第1図のそれと全く同じでよく、スイッチ
の導通・遮断の制御は簡単である。
When the transistor 5 is turned off by the control terminal 6, no current flows through the resistor 9, so the voltage between the gate and the source of the FET 15 becomes zero, and the drain and source of the FET 15 become conductive. Therefore, the potential of the connection point 10 is the same as that of the power supply terminal 7 to which a positive voltage is applied, and the bases and emitters of the transistors 3 and 4 are reverse biased. Further, since the connection point 10 is grounded in an alternating current manner, crosstalk characteristics are improved. It goes without saying that it is better to use an element with a small on-resistance for the FIT 15. Furthermore, since the transistors 3, 4.5 are off in this state, the current consumption when the signal is interrupted is only due to the leakage current of these transistors and is very small. Furthermore, in the circuit configuration shown in Figure 3, a transistor 5 and 1502 FBT semiconductor switching elements are used to control the emitter follower circuit, but the control method seen from the control terminal 6 is exactly the same as that shown in Figure 1. It is easy to control the conduction/cutoff of the switch.

なお第3図の例では、2個のエミッタ・フォロワ動作を
させるトランジスタ3.4を用いる場合について説明し
たが、第4図(a)に示すようにトランジスタ3をダイ
オード17に置き換えた場合、同図(b)に示すように
トランジスタ4だけをダイオード1Bに置き換えた場合
、同図(c)に示すようにトランジスタ3,4をそれぞ
れダイオード17.18に置き換えた場合も同様のスイ
ッチ動作をし、信号遮断時の消費電力は殆ど零で、良好
な漏話特性が得られる。さらにNPN )ランジスタラ
PNP)ランジスタに、PNP トランジスタをNPN
 )ランジスタに、NチャンネルFETをPチャンネル
FETに置き換え、タイオードや電源の極性を逆にした
回路でも同様の効果が得られることは明白である。
In the example shown in FIG. 3, a case has been described in which two transistors 3 and 4 that operate as emitter followers are used, but if the transistor 3 is replaced with a diode 17 as shown in FIG. When only transistor 4 is replaced with diode 1B as shown in Figure (b), and when transistors 3 and 4 are each replaced with diodes 17 and 18 as shown in Figure (c), the same switching operation occurs. Power consumption when the signal is cut off is almost zero, and good crosstalk characteristics can be obtained. Furthermore, add a PNP transistor to the NPN) transistor.
) It is obvious that a similar effect can be obtained with a circuit in which the N-channel FET is replaced with a P-channel FET in the transistor, and the polarity of the diode and power supply is reversed.

また第3図、第4図の単一のスイッチをa、 ra個用
いて、第1図で説明した結線を行うことにより入力数ル
、出力数mのスイッチマトリクスヲ構成できることは明
らかである。
It is also clear that a switch matrix with inputs of 1 and outputs of m can be constructed by using a and ra of the single switches shown in FIGS. 3 and 4 and making the connections described in FIG. 1.

広帯域の情報を交換する交換機に適用する場合を考える
と、マトリクスのスイッチは信号導通状態にあるものよ
り、信号遮断状態にあるもののほうがはるかに多い。し
たがって本発明は、漏話特性を劣化させることなく、信
号遮断時の消費電力を殆ど零としたことにより、大幅な
消電力が期待でき、IC化等の高密度実装をする場合に
も有利となる。
When applied to an exchange that exchanges broadband information, there are far more matrix switches in a signal-blocking state than in a signal-conducting state. Therefore, the present invention can be expected to significantly reduce power consumption by reducing the power consumption during signal interruption to almost zero without deteriorating the crosstalk characteristics, and is also advantageous when implementing high-density packaging such as IC. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来のエミッタ・7オロワ形スイツ
チの回路例、第3図は本発明を説明するためのエミッタ
・フォロワ形スイッチ回路の一実施例、第4図は本発明
のダイオードをm−たスイッチ回路への応用例である。 1 ・・・・・・・・・信号入力端子、 2・・・・・
・・・・信号出力端子、3.5 ・・・・・・・・・N
PN )ランジスタ、 4,13 ・・・・・・・・・
PNP )ランジスタ、 6・・・・・・・・・制御端
子、7・・・・・・・・・正電源端子、 8・・・・・
・・・・負電源端子、9、11.12.14.16.2
01・・・・・・・・・抵抗器、10・・・・・・・・
・ トランジスタ3のエミッタとトランジスタ40ペー
スの接続点、15・・・・・・・・・接合型Nチャンネ
ル電界効果トランジスタ、 17.18・・・・・・・
・・タイオード、 101.102・・・・・・・・・
スイッチ回路。 特許出願人 日本電信電話公社 第2図   第3図 011 −一一一一一一−−一一一一一−
1 and 2 are circuit examples of a conventional emitter/7 follower type switch, Figure 3 is an example of an emitter follower type switch circuit for explaining the present invention, and Figure 4 is a circuit example of a diode of the present invention. This is an example of application to a switch circuit using m-. 1...Signal input terminal, 2...
...Signal output terminal, 3.5 ......N
PN) transistor, 4,13...
PNP) transistor, 6... Control terminal, 7... Positive power supply terminal, 8...
...Negative power supply terminal, 9, 11.12.14.16.2
01・・・・・・Resistor, 10・・・・・・・・・
・ Connection point between the emitter of transistor 3 and transistor 40 pace, 15... Junction type N-channel field effect transistor, 17.18...
・・Tiode, 101.102・・・・・・・・・
switch circuit. Patent applicant Nippon Telegraph and Telephone Public Corporation Figure 2 Figure 3 011 -111111--11111-

Claims (2)

【特許請求の範囲】[Claims] (1)  信号をベースから入力し、エミッタから出力
する第1のトランジスタまたは該トランジスタのベース
・エミッタ接合と同じ向きのダイオード(以下、第1の
トランジスタおよびダイオードヲ総称して「第1のスイ
ッチ素子」という。またトランジスタのベース、エミッ
タとこれらに対応するダイオードのそれぞれの端子を総
称して「ベース等」「エミッタ等」という)と、第1ス
イツチ素子からの出力信号をベースに入力し、エミッタ
に信号を出力する第1のトランジスタの相補形の第2の
トランジスタまたは該トランジスタの接合と同じ11の
タイオード(以下、第2のトランジスタおよびダイオー
ドを総称して「第2のスイッチ素子」という)と、第1
のスイッチ素子のエミッタ等と第2のスイッチ素子のベ
ース等に接続され、第1、第2のスイッチ素子のオン/
オフを行なう制御回路を備えたスイッチ回路において、
前記制御回路が、前記第1のスイッチ素子のエミッタ等
と前記第2のスイッチ素子のベース等の順バイアス電流
を同時に導通または遮断するだめの抵抗と第3のトラン
ジスタの直列回路と、前記抵抗に印加される電圧で制御
され、前記第3のトランジスタの速断時に、前記第1の
スイッチ素子のエミッタ等と第2のスイッチ素子のベー
ス等oi続点を交流的に接地し、かつ第1および第2の
スイッチ素子のベース等・エミッタ等の間に逆バイアス
電圧を与えるための電界効果トランジスタとから構成さ
れたことを特徴とする広帯域信号スイッチ回路。
(1) A first transistor that inputs a signal from its base and outputs it from its emitter, or a diode oriented in the same direction as the base-emitter junction of the transistor (hereinafter, the first transistor and the diode are collectively referred to as "first switch element"). In addition, the base and emitter of the transistor and the corresponding terminals of the diode are collectively referred to as ``base, etc.'' and ``emitter, etc.''), and the output signal from the first switch element is input to the base, and the output signal from the first switch element is input to the base, A second transistor complementary to the first transistor that outputs a signal to the transistor, or 11 diodes that are the same as the junction of the transistor (hereinafter, the second transistor and the diode are collectively referred to as "second switch element"). , 1st
It is connected to the emitter, etc. of the switch element and the base, etc. of the second switch element, and turns on/off the first and second switch elements.
In a switch circuit equipped with a control circuit that turns off,
The control circuit includes a series circuit of a resistor and a third transistor for simultaneously conducting or blocking forward bias currents in the emitter of the first switch element and the base of the second switch element, and the resistor. It is controlled by the applied voltage, and when the third transistor is turned off quickly, the connection points such as the emitter of the first switching element and the base of the second switching element are grounded in an alternating current manner, and 1. A wideband signal switch circuit comprising a field effect transistor for applying a reverse bias voltage between the base, emitter, etc. of the second switch element.
(2)  下記の構成の広帯域信号スイッチ回路をU・
m個用いて、入力数ル、出力数mのスイッチ−/トリク
スを構成したことを特徴とする広帯域信号スイッチマト
リクス回路。 第1のスイッチ素子と、その第1スイツチ素rの出力を
入力とする第2のスイッチ素子と、第1のスイッチ素子
のエミッタ等7と第2のスイッチ素−イのベース等に接
続され、第1、第2のスイッチ素子のオン/オフを行な
う制御回路を備えた広帯域信号スイッチ回路であって、 該制御回路が、 前記第1のスイッチ素子のエミッタ等と前記第2のスイ
ッチ素子のベース等の順バイアス電流を同時に導通また
は遮断するための抵抗と第3のトランジスタの直列回路
と、前記抵抗に印加される電圧で制御され、前記第3の
トランジスタの速断時に、前記第1のスイッチ素子のエ
ミッタ等と第2のスイッチ素子のベース等゛の接続点を
交流的に接地し、かつ第1および第2のスイッチ素子の
ベース等・エミッタ等の間に逆バイアス電圧を与えるた
めの電界効果トランジスタとから構成された広帯域信号
スイッチ回路。
(2) A wideband signal switch circuit with the following configuration is
1. A wideband signal switch matrix circuit characterized in that m switches are used to constitute a switch/trix having several inputs and m outputs. A first switch element, a second switch element whose input is the output of the first switch element r, connected to the emitter etc. 7 of the first switch element and the base etc. of the second switch element i, A broadband signal switch circuit comprising a control circuit for turning on/off a first and second switch element, the control circuit comprising: an emitter of the first switch element, etc. and a base of the second switch element; A series circuit of a resistor and a third transistor for simultaneously conducting or cutting off forward bias currents such as An electric field effect for grounding the connection point between the emitter, etc. of the switch element and the base, etc. of the second switch element in an alternating current manner, and applying a reverse bias voltage between the base, etc. and emitter, etc. of the first and second switch elements. A wideband signal switch circuit composed of transistors.
JP57040294A 1982-03-16 1982-03-16 Wide band signal switching circuit Pending JPS58159024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57040294A JPS58159024A (en) 1982-03-16 1982-03-16 Wide band signal switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57040294A JPS58159024A (en) 1982-03-16 1982-03-16 Wide band signal switching circuit

Publications (1)

Publication Number Publication Date
JPS58159024A true JPS58159024A (en) 1983-09-21

Family

ID=12576582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57040294A Pending JPS58159024A (en) 1982-03-16 1982-03-16 Wide band signal switching circuit

Country Status (1)

Country Link
JP (1) JPS58159024A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0739093B1 (en) * 1995-04-18 1998-08-26 Nortel Networks Corporation High-speed switch and high-speed switching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0739093B1 (en) * 1995-04-18 1998-08-26 Nortel Networks Corporation High-speed switch and high-speed switching method
US5875188A (en) * 1995-04-18 1999-02-23 Northern Telecom Limited High speed switch

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