JPS58158978A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPS58158978A
JPS58158978A JP57041318A JP4131882A JPS58158978A JP S58158978 A JPS58158978 A JP S58158978A JP 57041318 A JP57041318 A JP 57041318A JP 4131882 A JP4131882 A JP 4131882A JP S58158978 A JPS58158978 A JP S58158978A
Authority
JP
Japan
Prior art keywords
layer
substrate
type
region
inp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57041318A
Other languages
Japanese (ja)
Other versions
JPH0241185B2 (en
Inventor
Hiroshi Kanbe
神戸 宏
Susumu Hata
進 秦
Haruo Nagai
治男 永井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57041318A priority Critical patent/JPS58158978A/en
Publication of JPS58158978A publication Critical patent/JPS58158978A/en
Publication of JPH0241185B2 publication Critical patent/JPH0241185B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/107Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
    • H01L31/1075Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To eliminate a special guard ring structure in a photodetector having one conductive type InGaAs layer to become a photoabsorbing layer and one conductive type InP layer to become avalanche amplification layer by sequentially forming one conductive type layer on a high resistance InP substrate having a region including reverse conductive type impurity. CONSTITUTION:A P type region 12 including P type impurity is diffuse in a semi-insulating InP substrate 10, and N type InP layer 11 and an N type InGaAs layer 12 are sequentially grown o the overall surface including the region 13. P type impurity in the substrate 10 is selectively diffused in the layer 11 by the high temperature during the growth or the heat treatment after the growth at this time, and a P-N junction 14 is produced in the layer 11. Thereafter, the back surface of the substrate 10 is polished until the region 13 is exposed, and a reflection preventive film such as SiO2 or Si3N4 is covered on the substrate. In this manner, the difference between the avalanche breakdown voltage V1 in the substrate 10 and the avalanche breakdown voltage V2 in the layer 11 becomes very large as V1>>V2, and the breakdown can be prevented at the end of the junction even if no guard ring is provided.

Description

【発明の詳細な説明】 発明の技術分野 本発明はなだれ増倍作用を有する半導体受光素子に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor light receiving element having an avalanche multiplication effect.

従来技術と問題点 光ファイバが低損失となる波長帯(1〜1.6μm)で
動作する受光素子材料として、InPに格子整合する三
元化合物半導体1rLo、55 Gaa、4y A’ 
(以下1nGaAzと略す)が知られている。JnGa
AIを用いて低暗電流、高量子効率等の高性能な受光素
子を実現する為に、I%QmAzをInPと組合せ、な
だれ増倍作用を1%2層内で行なわせ、光吸収をInG
aAz層内で行なわせるようにした構造が提案されてい
る。
Prior Art and Problems As a light-receiving element material that operates in the wavelength band (1 to 1.6 μm) where optical fibers exhibit low loss, a ternary compound semiconductor 1rLo, 55 Gaa, 4y A' lattice-matched to InP is used.
(hereinafter abbreviated as 1nGaAz) is known. JnGa
In order to realize a high-performance light-receiving element with low dark current and high quantum efficiency using AI, I%QmAz is combined with InP, avalanche multiplication is performed within the 1%2 layer, and light absorption is reduced by InG.
A structure has been proposed in which this is done within the aAz layer.

第1図(A)〜(C)はこの種の受光素子のそれぞれ異
なる従来例を示す断面図である。
FIGS. 1A to 1C are cross-sectional views showing different conventional examples of this type of light receiving element.

同図(A)はP+形IMP基板1上に、順次n形1xP
層2、筒形1*GaAz層3を成長させ、この後、P+
形IsP基板1、旙形1xGaAp層3上にそれぞれ適
当な電極(図示せず)を形成し、更に接合端部での降伏
を防ぐ為にメサ形にエツチングすることにより構成した
、なだれ増倍作用を有するアパランンフオトダイオード
である。この素子構造はよく知られているエピタキシャ
ル成長法、即ち気相成長法(VPE )や液相成長法(
LPE)で実現することができる。しかし、同図(A)
に示すメサ形構造の受光素子は接合が露出している為、
信頼性に欠ける欠点があった・ 同図CB>は上述した欠点を改善したプレーナ形と呼ば
れる受光素子であり、C形1vhP基板4上に順次筒形
I蕗GtxAa @ 5、ル形IルP層6を成長させ、
この後選択拡散法によりP十形1nP領域7v形成させ
、更にこの後端部での降伏を防ぐ為のガードリング8を
形成することにより構成したものである。通常この構造
は、気相成長法により作られる。その理由は、液相成長
法ではル形I絡G@As層5上に筒形InP層6v成長
させる場合、InP成長液が絡形I%GaAz層を溶し
てしまう現象があるからである。
In the same figure (A), n-type 1xP
Grow layer 2, cylindrical 1*GaAz layer 3, after which P+
Appropriate electrodes (not shown) are formed on the IsP substrate 1 and the 1x GaAp layer 3, respectively, and further etched into a mesa shape to prevent breakdown at the junction end. It is an Aparan photodiode with This device structure can be fabricated using well-known epitaxial growth methods, such as vapor phase epitaxy (VPE) and liquid phase epitaxy (VPE).
LPE). However, the same figure (A)
The mesa-shaped photodetector shown in the figure has an exposed junction, so
CB> in the same figure is a light receiving element called a planar type that has improved the above-mentioned drawback, and on the C-type 1vhP substrate 4, the cylindrical I-shaped GtxAa @ 5, the Le-shaped I-P grow layer 6;
Thereafter, a P-type 1nP region 7v is formed by selective diffusion, and a guard ring 8 is further formed to prevent breakdown at the rear end. This structure is usually produced by vapor phase growth. The reason for this is that in the liquid phase growth method, when growing 6v of cylindrical InP layers on the square I% GaAs layer 5, there is a phenomenon in which the InP growth solution dissolves the square I% GaAz layer. .

液相成長法で同図(B)に示すようなプレーナ形の受光
素子を製造する場合は、同図(C)に示すように、亀形
1nGaAz層5上ニInGaAzP四元WIJ9 k
設Lt、 s形I%P層6の成長時に製形l5GaAa
層が溶は出すのを防止するようにしている。尚、同図(
C)に於いて他の同図(B)と同一符号は同一部分を表
わしている。また、InGaAsP四元層を2層以上設
けるようにしても良い。
When manufacturing a planar light receiving element as shown in the same figure (B) by the liquid phase growth method, as shown in the same figure (C), an InGaAzP quaternary WIJ9 k is formed on the tortoise-shaped 1nGaAz layer 5.
Lt, formed during the growth of s-type I%P layer 6
This is to prevent the layer from dissolving. In addition, the same figure (
In C), the same reference numerals as those in the other figure (B) represent the same parts. Furthermore, two or more InGaAsP quaternary layers may be provided.

ところで、同図CB) 、 (C)に示す受光素子に於
いては、ガードリング8を設けること1二より、接合端
部での降伏を防ぐようにしているが、ガードリング8の
製作が難しい欠点があった。即ち、接合のある3形1’
nP層6の下に糺形InGaAz層6や1*GaAzP
四元層9がある為、空乏層広がりを制飢してガードリン
グ効果を効果的に発揮させるには、ガードリング8の深
さをP十形1nP領域7の深さとほぼ等しくすると言う
ような高度の技術が必要となる欠点があった。また、同
図CC)に示す受光素子に於いては、IwbGaAzP
層9を溶かすことなく、ル形I%P層6を成長させる為
には、非常に高度な技術が必要となる欠点があった。
By the way, in the light-receiving elements shown in CB) and (C) of the same figure, a guard ring 8 is provided to prevent breakdown at the joint end, but manufacturing the guard ring 8 is difficult. There were drawbacks. That is, 3 shapes 1' with joints
Under the nP layer 6, there is a porcelain InGaAz layer 6 or 1*GaAzP.
Since there is a quaternary layer 9, in order to suppress the spread of the depletion layer and effectively exhibit the guard ring effect, the depth of the guard ring 8 should be made almost equal to the depth of the P 10-type 1nP region 7. The drawback was that it required advanced technology. In addition, in the light receiving element shown in CC) of the same figure, IwbGaAzP
In order to grow the square I%P layer 6 without melting the layer 9, a very sophisticated technique was required.

以上述べたように、従来のなだれ増倍作用を有する受光
素子に於いては、結晶成長上の欠点と共に、製造上精密
な制御が必要となるガードリング構造を設けなければな
らない欠点があった。
As described above, the conventional light-receiving element having an avalanche multiplication effect has the disadvantage of not only crystal growth but also the necessity of providing a guard ring structure that requires precise manufacturing control.

発明の目的 本発明は前述の如き欠点を改善したものであり。purpose of invention The present invention improves the above-mentioned drawbacks.

その目的は、特別なガードリング構造が不要で。Its purpose is to eliminate the need for a special guard ring structure.

且つ高性能のなだれ増倍作用を有する半導体受光1子を
提供することにある。以下実施例について詳細に説明す
る。
Another object of the present invention is to provide a semiconductor photodetector having a high-performance avalanche multiplication effect. Examples will be described in detail below.

発明の実施例 182図は本発明の一実施例の断面図であり、1゜は半
絶縁性のInP基板(以下半絶縁性1nP基板と称す)
、11はなだれ増倍層となるル形1nP層、12は光吸
収層となる算形回路GαAs層、13はP形不純物を多
量に含んだP影領域である。また、′!g3図(,4)
 、 (B)は第2図に示した受光素子の製造方法の一
例を説明する為の断面図であり、$2図と同一符号は同
一部分を表わしている。
Embodiment 182 of the invention is a cross-sectional view of an embodiment of the invention, where 1° is a semi-insulating InP substrate (hereinafter referred to as semi-insulating 1nP substrate).
, 11 is a le-shaped 1nP layer serving as an avalanche multiplication layer, 12 is an arithmetic circuit GαAs layer serving as a light absorption layer, and 13 is a P shadow region containing a large amount of P-type impurities. Also,'! g3 diagram (,4)
, (B) is a sectional view for explaining an example of a method of manufacturing the light receiving element shown in FIG. 2, and the same reference numerals as in FIG. 2 represent the same parts.

第2図に示した受光素子を製造する場合は、先ず第5図
(A)に示すように、半絶縁性InP基板10に選択的
にP形不純物を多量に含むP影領域15を形成する。尚
、P影領域の形成方法としては、不純物拡散法、イオン
注入法等が適用できる0次に5気相成長法、液相成長法
等の方法により、半絶縁性1xP基板1D上ニル形1n
P層11.指形InGaAz層12を順次成長させる。
When manufacturing the light receiving element shown in FIG. 2, first, as shown in FIG. 5(A), a P shadow region 15 containing a large amount of P type impurities is selectively formed on a semi-insulating InP substrate 10. . The P shadow region is formed on a semi-insulating 1xP substrate 1D by a method such as a 0-order 5 vapor phase growth method or a liquid phase growth method to which an impurity diffusion method, an ion implantation method, etc. can be applied.
P layer 11. Finger-shaped InGaAz layers 12 are grown one after another.

語形hbP層11、に形1nGaAz#A12の成長中
の高温或は成長後の熱処理により、半絶縁性IrLP基
板10中のp形不純物は選択的にn形ITLP層11に
拡散し、同図(B)に示すように、π形1nP J傾1
1中にp−x接合14が形成される。次にP影領域13
が露出するまで半絶縁性1nP基板10を薄くし、第2
図に示す構造を得る。
Due to the high temperature during the growth of the hbP layer 11 and the nGaAz#A12 or the heat treatment after growth, the p-type impurities in the semi-insulating IrLP substrate 10 are selectively diffused into the n-type ITLP layer 11, as shown in the figure ( As shown in B), π-type 1nP J slope 1
A p-x junction 14 is formed in 1. Next, P shadow area 13
The semi-insulating 1nP substrate 10 is thinned until the second
Obtain the structure shown in the figure.

本実施例によれば、結晶成長は気相成長法でも液相成長
法でも良く、液相成長法による場合に於いても、従来例
のように特別な四元層を設ける必要はない。また、半絶
縁性1nP基板10内でのなだれ降伏電圧V1と亀形I
%P層11内でなだれ降伏電圧Viとの差は非常に大き
い為(VI>V鵞)、特別なガードリング構造を設けな
くとも接合端部での降伏を防ぐことができる。従って、
半絶縁性ハP基板10上に、P影領域13の一部分を覆
い、一部分を露出させる電極(例えばリング状の電極)
を形成し、P影領域13が露出した部分に、sho、 
According to this embodiment, crystal growth may be performed by either a vapor phase growth method or a liquid phase growth method, and even when using the liquid phase growth method, there is no need to provide a special quaternary layer as in the conventional example. In addition, the avalanche breakdown voltage V1 and the tortoise shape I in the semi-insulating 1nP substrate 10
Since the difference between the avalanche breakdown voltage Vi within the %P layer 11 is very large (VI>V), breakdown at the junction end can be prevented without providing a special guard ring structure. Therefore,
An electrode (for example, a ring-shaped electrode) that covers a part of the P shadow region 13 and exposes a part is placed on the semi-insulating P substrate 10.
, and in the exposed part of the P shadow area 13, sho,
.

Si、N、等から成る反射防止膜を形成し、更に亀形領
域15の一部分を露出させる電極構造としたのは、該露
出部から光を入射させる為である。また、亀形1nGa
As ii 12上に四元層、ItsP層、多結aVリ
コン層、塁−■族化合物半導体層等を比較的厚く成長さ
せ、これにより、クエへの強度を高めることは従来技術
により容易に可能である。また、比抵抗がn形InP層
11の比抵抗より高い高抵抗I%P基板を、半絶縁性1
nF基板10の代わりに使用することも可能である。
The reason why an anti-reflection film made of Si, N, etc. is formed and an electrode structure is provided in which a portion of the tortoise-shaped region 15 is exposed is to allow light to enter from the exposed portion. In addition, tortoise-shaped 1nGa
It is easily possible using conventional techniques to grow relatively thick quaternary layers, ItsP layers, polycondensed AV recon layers, base-■ group compound semiconductor layers, etc. on As II 12, thereby increasing the strength against Queue. It is. In addition, a high-resistance I%P substrate whose specific resistance is higher than that of the n-type InP layer 11 is used as a semi-insulating substrate.
It is also possible to use it instead of the nF substrate 10.

第4図は本発明の他の実施例の断面図であり、15は半
絶縁性1nP基板、16はなだれ増倍層となる3形rn
p層、17は光吸収層となる語形I%GaAp層、18
はP形不純物を含むJmGaAzP四元層、19はP影
領域、20は凹部である。また、第5図(A)、(B)
は第4図に示した受光素子の製造方法の一例を説明する
為の断面図であり、第4図と同一符号は同一部分を表わ
している。
FIG. 4 is a cross-sectional view of another embodiment of the present invention, in which 15 is a semi-insulating 1nP substrate, 16 is a 3-type rn which becomes an avalanche multiplication layer.
p layer, 17 is an I% GaAp layer which becomes a light absorption layer, 18
is a JmGaAzP quaternary layer containing P-type impurities, 19 is a P shadow region, and 20 is a concave portion. Also, Fig. 5 (A), (B)
4 is a sectional view for explaining an example of a method of manufacturing the light receiving element shown in FIG. 4, and the same reference numerals as in FIG. 4 represent the same parts.

第4図に示した受光素子を製造するには、先ず第5図(
A)に示すように半絶縁性1nF基板15に。
To manufacture the light receiving element shown in Fig. 4, first the photodetector shown in Fig. 5 (
A semi-insulating 1nF substrate 15 as shown in A).

エツチングにより凹部21を形成する0次に、同図CE
)に示すように、半絶縁性1nP基板15の凹部21に
、P形不純物を含むI旙GaAzP四元層18を成長さ
せ、更にル形11%P層16及び語形InGaAa層1
7を順次成長させる。整形I%P層16及びル形1nG
aAsr層17の成長時の高温或いは成長後の熱処理に
より、InGaAzP四元層18中に含まれていたP形
不純物が1%形1rbP層16中に前述したと同様に拡
散し。
The recess 21 is formed by etching.
), an IGaAzP quaternary layer 18 containing P-type impurities is grown in the recess 21 of the semi-insulating 1nP substrate 15, and further a 11% P layer 16 and an InGaAa layer 1 are formed.
7 to grow sequentially. Shaped I%P layer 16 and Le shaped 1nG
Due to the high temperature during growth of the aAsr layer 17 or the heat treatment after growth, the P-type impurity contained in the InGaAzP quaternary layer 18 is diffused into the 1% type 1rbP layer 16 in the same manner as described above.

P影領域19が形成される0次に半絶縁性1rbP基板
15の裏面をエツチングして、第4図に示すような凹部
20を形成する。この場合、適当なエツチング液(例え
ばクロムメタノール、重クロム酸等)を使用することに
より、InPとInGaAppとのエツチングを選択的
に行なうことができるので、エツチングをInGaAJ
FP四元層18の表面で自動的に停止させることができ
る。尚、電極及び反射防止膜は図示を省略したが、電極
はル形1nGaAp層17上に設けられると共に、 I
nGαAIP四元層1Bの周辺にI%GαAsP四元)
−の一部分を覆い、一部分を露出させるように設けられ
るものである。また、反射防止膜はIrkGttAzp
四元鳩18の露出した部分に設けられるものである。
The back surface of the zero-order semi-insulating 1rbP substrate 15 on which the P shadow region 19 is formed is etched to form a recess 20 as shown in FIG. In this case, by using an appropriate etching solution (for example, chromium methanol, dichromic acid, etc.), InP and InGaApp can be selectively etched.
It can be automatically stopped at the surface of the FP quaternary layer 18. Note that although the electrodes and antireflection coatings are not shown in the drawings, the electrodes are provided on the square-shaped 1nGaAp layer 17, and
I%GαAsP quaternary around the nGαAIP quaternary layer 1B)
-It is provided so that one part is covered and the other part is exposed. In addition, the anti-reflection film is IrkGttAzp.
It is provided in the exposed part of the quaternary pigeon 18.

!186図は本発明のその他の実施例の断面図であり、
22は半絶縁性1nP基板、23はなだれ増倍層   
゛となる亀形I絡PH1,24は光吸収1−となるル形
1nGαA3層、25はP形不純物を含んだInGaA
zP 14.26はP形I%P層、27は凹部である。
! FIG. 186 is a sectional view of another embodiment of the present invention,
22 is a semi-insulating 1nP substrate, 23 is an avalanche multiplication layer
The tortoise-shaped I-circuit PH1, 24 is a 1-nGαA3 layer with light absorption of 1-, and 25 is an InGaA layer containing P-type impurities.
zP 14.26 is a P-type I%P layer, and 27 is a recess.

また、第7図(A)〜(D>は第6図に示した受光素子
の製造方法の一例を説明する為の断面図であり、第6図
と同一符号は同一部分を表わしている。
7(A) to (D>) are sectional views for explaining an example of a method of manufacturing the light receiving element shown in FIG. 6, and the same reference numerals as in FIG. 6 represent the same parts.

第6図の受光素子を製造するには、先ず第7図(A)に
示すように、半絶縁性I%P基板22にエツチングによ
り凹部28を形成する。次に、同図(B)に示すように
、半絶縁性1sP基板22上にp形不純物を含んだI*
GaAzP四元層25、P形1nP層26を順次成長さ
せる。I%GaAzP四元層25、p形I襲P層26の
成長時の高温或は成長後の熱処理により、IルGaAz
P四元層25に含まれていたp形不純物は半絶縁性In
P基板22中へ拡散される。次に、選択的エツチングを
行ない、同図(C)に示すように、成長層に凸部を形成
する。次に、同図CD)に示すように、算形InP層2
3、ル形1nGaAt層24を順次半絶縁性1nP基板
22上に成長させる。この後、半絶縁性ll5P基板2
2の裏面を選択エツチング液を用いてエツチングし、第
6図に示すように四部27を形成する。
To manufacture the light receiving element shown in FIG. 6, first, as shown in FIG. 7(A), a recess 28 is formed in the semi-insulating I%P substrate 22 by etching. Next, as shown in FIG.
A GaAzP quaternary layer 25 and a P-type 1nP layer 26 are sequentially grown. I% GaAzP quaternary layer 25 and p-type I-GaAzP layer 26 are grown at high temperatures during growth or by post-growth heat treatment.
The p-type impurity contained in the P quaternary layer 25 is semi-insulating In
It is diffused into the P substrate 22. Next, selective etching is performed to form convex portions in the grown layer, as shown in FIG. Next, as shown in FIG. CD), the shaped InP layer 2
3. A square-shaped 1nGaAt layer 24 is sequentially grown on the semi-insulating 1nP substrate 22. After this, semi-insulating ll5P substrate 2
The back side of 2 is etched using a selective etching solution to form four parts 27 as shown in FIG.

この場合も、適当なエツチング液(例えばクロムメタノ
ール)を使用することにより、エツチングをI絡GtA
zP四元層25の表面で自動的に停止させることができ
る。尚、電極はル形IルGaAz層24上に設けると共
に、InGaAzP四元層25の周辺に。
In this case as well, by using a suitable etching solution (e.g. chromium methanol), etching can be prevented from I-containing GtA.
It can be automatically stopped at the surface of the zP quaternary layer 25. Incidentally, the electrode is provided on the square-shaped GaAz layer 24 and around the InGaAzP quaternary layer 25.

InGgルP四元層25の一部分を覆うように設けるも
のである。また、反射防止膜はInGaAzP四元層2
5の露出部分に設けるものである。
It is provided so as to cover a part of the InGgP quaternary layer 25. In addition, the antireflection film is an InGaAzP quaternary layer 2.
It is provided in the exposed part of No.5.

@4図、第6図に示した受光素子は、半絶縁性1nF基
板15.22にP形1tsGaAzP四元層18.25
を埋込んだ構造となっているので、素子製作工程に於い
て、半絶縁性IsP基板15,22に凹部20 、27
を形成する場合、選択的エツチング液を使用でき、従ッ
テ、エツチングをP ff!/InGaAzP四元@ 
1B 、 25の表面で自動的に停止させることができ
る利点がある。また、半絶縁性1nP基板15.22が
ガードリングとしての役割をはだす為、特別なガードリ
ング構造を設ける必要がなくなる利点がある。
The photodetector shown in Figures 4 and 6 consists of a P-type 1tsGaAzP quaternary layer 18.25 on a semi-insulating 1nF substrate 15.22
Since the structure is such that the recesses 20 and 27 are embedded in the semi-insulating IsP substrates 15 and 22 during the element manufacturing process,
A selective etching solution can be used to form a Pff! /InGaAzP quaternary @
It has the advantage of being able to automatically stop at the surface of 1B and 25. Further, since the semi-insulating 1nP substrates 15 and 22 play a role as a guard ring, there is an advantage that there is no need to provide a special guard ring structure.

尚、実施例に於いては、p形の不純物を含む領域を有す
る半絶縁性1nP基板上に、ル形のなだれ増倍層、光吸
収層を設けるようにしたが、n形の不純物を含む領域を
有する半絶縁性IMF基板上にP形のなだれ増倍層、光
吸収層を設けるようにしても良いことは勿論である。
In the example, a round-shaped avalanche multiplication layer and a light absorption layer were provided on a semi-insulating 1nP substrate having a region containing p-type impurities; Of course, a P-type avalanche multiplication layer and a light absorption layer may be provided on a semi-insulating IMF substrate having a region.

発明の効果 以上説明したように1本発明は、−導電形不純物を含む
領域を有する高抵抗IMF基板上になだれ増倍層となる
反対導電形のIrLP層、光吸収層となる反対導電形の
InGalLx層を順次形成したものであり、高抵抗I
nP基板がガードリングの役割をはだす為、特別なガー
ドリング構造を設ける必要がなく、従って、良好な特性
のなだれ増倍作用を有する半導体受光素子を容易に製造
できる利点がある。また、液相成長法で従来問題となっ
ていたJnGaAzP四元層9の必要性や、I*GaA
zP四元層9が溶けることによる蕗形1nP層6の質の
低下等がなくなる為、なだれ増倍層となる良質の絡形I
MP層を容易に製造することができ、このことによって
も高性能の受光素子を容易に製造することが可能となる
利点がある。更に、基板上に選択的に形成するP影領域
をInGaAzPとしておくことにより、基板裏面に凹
部を設ける際、エツチングを自動的に停止させることが
できる利点がある。
Effects of the Invention As explained above, the present invention provides an IrLP layer of opposite conductivity type to serve as an avalanche multiplication layer and an IrLP layer of opposite conductivity type to serve as a light absorption layer on a high-resistance IMF substrate having a region containing impurities of conductivity type. InGalLx layers are sequentially formed, and high resistance I
Since the nP substrate plays the role of a guard ring, there is no need to provide a special guard ring structure, and therefore, there is an advantage that a semiconductor light-receiving element having good characteristics and an avalanche multiplication effect can be easily manufactured. In addition, the necessity of the JnGaAzP quaternary layer 9, which has been a problem in the liquid phase growth method, and the I*GaA
Since there is no deterioration in the quality of the butterfly-shaped 1nP layer 6 due to melting of the zP quaternary layer 9, a high-quality entangled layer I that becomes an avalanche multiplication layer is eliminated.
The MP layer can be easily manufactured, which also has the advantage of making it possible to easily manufacture a high-performance light receiving element. Further, by using InGaAzP as the P shadow region selectively formed on the substrate, there is an advantage that etching can be automatically stopped when forming a recess on the back surface of the substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)〜(C’)はそれぞれ異なる従来例の断面
図、第2図は本発明の一実施例の断面図、第3図(A)
 、 (B)は第2図に示した素子の製造方法を説明す
る為の断面図、第4図は本発明の他の実施例の断面図、
第5図(A) 、 CB>は第4図に示した素子の製造
方法を説明する為の断面図、第6図は本発明のその他の
実施例の断面図、第7図(A)〜(D)は第6図に示し
た素子の製造方法を説明する為の図である。 1はP形I%P基板、2,6,11,16,25はル形
IMP層、5.5,12,17,24は絡形1nGaA
z層、4はC形IMP基板、7はど形1nF領域、8は
ガードリング、9,18.25はInGaAzP四元層
、10 、15 。 22は半絶縁性IルP基板、15 、19はp影領域、
14はP−譜接合、20 、21 、27 、28は凹
部、26はP形  9IルP層である。 特許出願人 日本電信電話公社 代理人弁理士 玉蟲久五部(外3名) 第1 図 (A) jF!2 図 3 第3 図 (B)
Figures 1 (A) to (C') are sectional views of different conventional examples, Figure 2 is a sectional view of an embodiment of the present invention, and Figure 3 (A).
, (B) is a sectional view for explaining the manufacturing method of the element shown in FIG. 2, FIG. 4 is a sectional view of another embodiment of the present invention,
5(A) and CB> are cross-sectional views for explaining the manufacturing method of the element shown in FIG. 4, FIG. 6 is a cross-sectional view of other embodiments of the present invention, and FIGS. 7(A)- (D) is a diagram for explaining a method of manufacturing the element shown in FIG. 6. 1 is a P-type I%P substrate, 2, 6, 11, 16, and 25 are square IMP layers, and 5.5, 12, 17, and 24 are tangled 1nGaA
z layer, 4 is a C-type IMP substrate, 7 is a square 1nF region, 8 is a guard ring, 9, 18.25 is an InGaAzP quaternary layer, 10, 15. 22 is a semi-insulating IP substrate, 15 and 19 are p shadow regions,
14 is a P-staff joint, 20, 21, 27, and 28 are recesses, and 26 is a P-shaped 9IP layer. Patent Applicant: Nippon Telegraph and Telephone Public Corporation Patent Attorney Gobe Tamamushi (3 others) Figure 1 (A) jF! 2 Figure 3 Figure 3 (B)

Claims (1)

【特許請求の範囲】[Claims] 光吸収層となる一導電形のInGaAz層と、なだれ増
倍層となる一導電形のInP層とを有する半導体受光素
子に於いて、反対導電形の不純物を含む領域を有する高
抵抗1nP基板上に前記−導電形のInP層及びl5G
aAz層を順次形成させたことを特徴とする半導体受光
素子。
In a semiconductor photodetector having an InGaAz layer of one conductivity type serving as a light absorption layer and an InP layer of one conductivity type serving as an avalanche multiplication layer, a high resistance 1nP substrate having a region containing impurities of the opposite conductivity type is used. The - conductivity type InP layer and l5G
A semiconductor light-receiving device characterized by sequentially forming aAz layers.
JP57041318A 1982-03-16 1982-03-16 Semiconductor photodetector Granted JPS58158978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57041318A JPS58158978A (en) 1982-03-16 1982-03-16 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57041318A JPS58158978A (en) 1982-03-16 1982-03-16 Semiconductor photodetector

Publications (2)

Publication Number Publication Date
JPS58158978A true JPS58158978A (en) 1983-09-21
JPH0241185B2 JPH0241185B2 (en) 1990-09-14

Family

ID=12605158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57041318A Granted JPS58158978A (en) 1982-03-16 1982-03-16 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPS58158978A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009300206A (en) * 2008-06-12 2009-12-24 Murata Mfg Co Ltd Ultraviolet sensor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124278A (en) * 1979-03-20 1980-09-25 Nippon Telegr & Teleph Corp <Ntt> Avalanche photodiode

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124278A (en) * 1979-03-20 1980-09-25 Nippon Telegr & Teleph Corp <Ntt> Avalanche photodiode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009300206A (en) * 2008-06-12 2009-12-24 Murata Mfg Co Ltd Ultraviolet sensor

Also Published As

Publication number Publication date
JPH0241185B2 (en) 1990-09-14

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