JPS5815809B2 - General information - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a command prefetch function and performing advance control.

Conventionally, in the branch instruction processing in an information processing device that performs advance control, if it is determined at the design stage that the probability of a branch success is a dog, the branch success side is unconditionally taken first, or conversely, the probability of a branch failure is When it is determined that the branch is a dog, speeding up is achieved by pre-empting the unsuccessful branch, or by pre-empting both the successful and unsuccessful branches.

However, due to the nature of the program that the probability of branch success/failure is uncertain, the first two cases often result in pre-emption in the opposite direction than expected, and the last case does not. Although the program has strong characteristics, it has the disadvantage that the amount of hardware required to store the preemptive information increases significantly.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide an information processing device that can prevent erroneous prefetching of instructions following a branch instruction forming a loop as much as possible without causing an increase in the amount of hardware.

Another object of the present invention is to provide an information processing apparatus that determines the characteristics of a program as it is executed in a timely manner and proceeds with a prefetch operation in a direction that is more effective for subsequent instructions (branch success side/branch failure side). The aim is to provide the necessary amount of hardware and to suppress the increase in the amount of hardware as much as possible.

According to the present invention, in an information processing device having a function of prefetching instructions and performing advance control, a loop is formed on the branch success side, and a route is formed on the branch failure side to exit the loop. a flip-flop that predicts the success or failure of a branch instruction that is being executed; There is obtained an information processing device characterized in that it is provided with a branch instruction control circuit for instructing prefetching.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an information processing apparatus according to the present invention.

As shown in FIG. 1, in an information processing device that performs advanced prefetch control, an instruction prefetch unit 1
, an instruction decoding section 2 , and an operand prefetching section 3 .

Generally, these are collectively called a preceding instruction processing section.

The preceding instruction processing section supplies information necessary for executing the instruction to the instruction execution processing section 4, which operates independently of the preceding instruction processing section.

Instruction prefetch unit 1, instruction decoder 2, operand prefetch unit 3
, and the instruction execution processing unit 4 are capable of parallel processing, and this parallel processing operation is called pipelining.

First, general prefetch control of branch instructions by an information processing device using pipelining will be described.

A program to be executed is stored in the storage device 5, and the instruction word group 7 is stored in the storage device 5 according to the instruction address 6.
is read from.

The read instruction word group is temporarily set in the instruction prefetch section 1, and a predetermined instruction is set in the instruction register in the instruction decoding section 2.

The instruction decoding section 2 decodes this, and the operand prefetching section 3 collects information necessary for executing the instruction.

Here, in the figure, 9 is an operand word address bus, and 8 is an operand word read path.

The operand prefetch unit 3 supplies the necessary information to the instruction execution processing unit 4 when the collection of necessary information is completed.

If the instruction decoded by the instruction decoding unit 2 is a branch instruction, the direction (determined and defined at the design stage of the information processing device) with a higher probability of proceeding is either a successful branch or an unsuccessful branch instruction.

).

That is, the probability that the branch instruction proceeds to the unsuccessful side. If is a dog, the instruction following the branch instruction 0 in the storage device 5 (
The operation continues in the direction of preempting the branch instruction (unsuccessful side instruction), and if the probability of proceeding to the successful side is equal, the prefetching of the instruction (unsuccessful side instruction) following the branch instruction in the storage device 5 is stopped. The instruction prefetch section.

1, the prefetching of the instruction (successful instruction) is restarted from another address (branch successful side address) in the storage device 5.

In an information processing device using such prefetch control, the instruction processing order and the destination are determined when the instruction execution processing unit 4 executes a branch instruction.

The instructions prepared by the line instruction processing unit often differ depending on the characteristics of the program.

In such a case, it is necessary to initially activate the preceding instruction processing section in response to an instruction from the instruction execution processing section 4 to prefetch the new instruction.

The present invention makes it possible to prevent erroneous prefetching of subsequent instructions due to the characteristics of the program as much as possible by adding only a small amount of hardware, and to advance the prefetching operation in a more effective direction.

That is, as shown in FIG. 1, the present invention uses a flip-flop (hereinafter referred to as a prediction FF) that predicts the success/failure of a branch instruction.

) 11, and a branch instruction control circuit for causing the flip-flop 11 to predict in accordance with signals 101 and 102 obtained by executing the branch instruction, and for instructing 103 to prefetch an instruction in the direction according to the prediction of the flip-flop 11. 10 is provided in a preceding instruction processing section, and an instruction subsequent to a branch instruction is effectively prefetched.

Figure 2 shows the prediction FF 11 and branch instruction control circuit 10 in Figure 1.
This embodiment will be described in detail below with reference to FIG. 1 and FIG. 2.

This embodiment has a configuration suitable for processing branch instructions that form a loop by counting the number of loops.

First, the initial value of the prediction FF 11 that predicts the success/failure of a branch instruction forming a loop by counting the number of loops is input to the prediction FF 11 through an OR gate circuit 202.
The initial setting signal 108 from the preceding instruction processing unit inputted to F11 is set as "success" (FF value - 1), and the value is stored in prediction FF11.

After that, when the above branch instruction is set in the instruction decoder 2,
Prefetching of subsequent instructions is performed in the direction according to the instruction 103 of the prediction FF 11.

(This prediction signal 103 is a branch instruction display signal 106 that is issued spontaneously when a branch instruction is set in the instruction decoder 2, and a predicted FF1
This is the output signal of the AND gate circuit 205 which uses the output signal of 1 and the output signal of 2.

) That is, when the branch instruction is set in the instruction decoding unit 2 for the first time after the preceding instruction processing unit is canceled, the predicted FF
11 is "success", so that the prefetching of the unsuccessful instruction following the branch instruction in the storage device 5 is invalidated and the branch destination instruction word in the storage device 5 is prefetched.
The instruction decoder 2 sends a branch success side prefetch command signal 104 to the instruction prefetch unit 1 to instruct it.

When the branch instruction is executed by the instruction execution processing unit 4, the instruction execution processing unit 4 outputs the execution result signal 101 (-1 signal if the branch is successful, -○ signal if the branch is unsuccessful) and the next prediction. A signal 102 (signal 102 (signal 0 when the instruction execution processing unit 4 counts 7 and predicts that the next branch will fail) is reported to the branch instruction control circuit 10.

A prefetch operation after the branch instruction (preemption is performed on the successful side of the branch).

) is correct or not by checking in the exclusive OR circuit 204 whether the execution result signal 101 reported at that time and the value of the prediction FF 11 match.

If the prefetch direction and the execution result of the branch instruction are different, a signal having a logic 1 (prefetch restart signal) from the exclusive OR circuit 204 is input to the instruction prefetch unit 1 via the AND gate circuit 206. ) 105 instructs the instruction prefetching unit 1 to invalidate the instructions following the branch instruction prefetched by the preceding instruction processing unit and to perform prefetching in the correct direction again.

When the prefetch direction and the execution result of the branch instruction match, the value of the prediction FF 11 is reset based on the next prediction signal 102 that is reported simultaneously with the execution result signal 101.

That is, if the next prediction signal 102 is again on the ``success'' side (next prediction signal - 1 signal), the value of the prediction FF 11 is left as ``success'' (FF value - 1), and the next time, the branch is operated on the unsuccessful side. If it can be predicted that the next prediction will occur (next prediction signal = 0 signal), the value of prediction FF11 is set to “unsuccessful” (FF value - 〇).
and set.

This operation is inhibited (1nhibi) as shown in the diagram.
t) 'y'-t circuit 203.

Here, 107 is a branch instruction execution timing signal from the instruction execution processing section 4.

If the value of prediction FFI 1 is set to ``success'', the above operation is repeated until it is reset to ``failure'', and if the value of prediction FF11 is set to ``unsuccess'' (by the next branch instruction) , when it is predicted that the loop in the program will be exited), when the next branch instruction is set in the instruction decoding unit 2, the instruction prefetching unit 1 reads the branch instruction following the branch instruction in the storage device 5. The operation continues in the direction of preempting the instruction (unsuccessful instruction).

The value of the predicted FF 11 indicates the "unsuccessful" side (FF value - 0), and the execution result signal 101 is reported from the instruction execution processing unit 4.
If the branch is unsuccessful, that is, if the loop in the program is correctly exited, the inhibit gate circuit 207 changes the value of the predicted FF11 to a successful branch.
The prediction FF 11 stores this value for the loop operation of the subsequent branch instruction.

In addition, in FIG. 2, 201 is an ink face with other control units.

FIG. 3 shows an example of the above-mentioned branch instruction that forms a loop by counting the number of loops.

In FIG. 3, Sl is x=n, S2 is a processing step,
S3 is x=x-1, 84 is x=0? , Bl are branch instructions.

A loop is formed on the branch success side (ie, NO side) of the branch instruction BI, and a route for exiting the loop is formed on the branch failure side (ie, YES side) of the branch instruction BI.

Next, the setting transition of the prediction FF 11 will be explained with reference to FIGS. 2 and 3.

The initial value of the prediction FF11 is the initial setting signal 10 as described above.
8, it is set as "success" (FF value - 1).

For example, the processing steps of S2 according to the instructions of the program are 1
If it is executed 0 times, it becomes x-10 due to Sl,
After performing the process in S2, x=10-1=9 is executed in S3, and since X=O is not determined in S4, the process proceeds to the NO side (that is, the branch success side), and 1 of the S2 → S3 → S4 process This means that the loop has been executed for the second time.

After that, X is sequentially subtracted in the same way, S2→S3→
The S4 process is executed 10 times, and after the 10 times, X=0 due to S4, so the process proceeds to the YES side (that is, the branch failure side).

The present invention runs from 84 to N in the process of running 10 times.

The instruction word to the side (that is, the branch success side) is preempted without waste,
In addition, in order to achieve the effect of prefetching the instruction word on the YES side (that is, the branch failure side) to be processed after the 10th execution of 84 without error, the result of executing 83 for the 9th time is X = 1 (next time, the loop must be skipped) It can be fully predicted that the operation will proceed to the branch failure side.

), the instruction execution processing unit 4 reports the next prediction signal 102 to the branch instruction control circuit 10 as a 0 signal.

In all cases other than X=1, the next prediction signal 102 is 1.
It becomes a signal.

Based on the conditions that the next prediction signal 102 is the O signal and the branch instruction execution timing signal 107 from the instruction execution processing unit 4, the prediction FF 11 is set to "unsuccessful" (FF value - 0), and the 10th time is set. Prefetching of the YES-side (ie, branch failure-side) instruction to be processed after execution of 84 is correctly predicted.

Note that after the 10th execution of 84, the prediction FF11 is set to ``success'' (F
The F value is set to 1).

In the above embodiment, a 2.3-bit flip-flop (
This can be realized by adding one branch instruction per type) and a small number of peripheral circuits.

As is clear from the above description, the present invention includes a flip-flop that predicts the success or failure of a branch instruction forming a loop in a conventional preceding instruction processing unit, and a flip-flop that predicts the success or failure of a branch instruction that forms a loop. By adding a branch instruction control circuit for instructing the branch instruction to be executed in accordance with the information to be executed and to prefetch the instruction in the direction according to the prediction of the flip-flop, it is possible to control the execution of the program without increasing the amount of hardware. This has the advantage that it is possible to timely determine the characteristics that do not exist, and to effectively proceed with the prefetch operation after a branch instruction.

That is, the present invention has the effect of preventing erroneous prefetching of instructions following a branch instruction forming a loop as much as possible without causing an increase in the amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of an information processing device according to the present invention, and FIG. 2 is a predictive flip-flop 11 in FIG. 1 that is effective for use in branch instructions forming a loop.
and a third diagram specifically showing the branch instruction control circuit 10.
The figure is a flowchart showing an example of branch instructions that form a loop. 1... Instruction prefetch section, 2... Instruction decoding section, 3... Operand prefetch section, 4...
・Instruction execution processing unit, 5...Storage device, 6-...
...Instruction word address, I...Instruction word read path, 8...Operand word read path, 9.
...Operand address path, 10...
- Branch instruction control circuit, 11... Prediction flip-flop, 101... Branch instruction success signal, 102
...Next prediction signal, 103 ... Prediction signal, 104 ... Branch successful side preemption instruction signal, 1
05... Preemptive restart signal, 106...
...Branch instruction display signal from the instruction decoder, 107...
... Branch instruction execution timing signal from the instruction execution processing section, 108 ... Initial setting signal from the preceding instruction processing section, 201 ... Other sound control section interface, 202 ... ...OR gate circuit, 203, 207
...Inhibit gate circuit, 204...
・Exclusive logical OR circuit, 205, 206...
and gate circuit.

Claims (1)

[Claims] 1. In an information processing device that has an instruction prefetch function and performs advance control, a branch instruction in which a loop is formed on the branch success side and a route to exit the loop is formed on the branch failure side. a flip-flop for predicting the success or failure of a branch; for making the prediction of the flip-flop according to information obtained by executing the branch instruction; and for instructing the prefetching of an instruction in the direction of following the prediction of the flip-flop; An information processing device comprising: a branch instruction control circuit.