JPS58157149A - Manufacture of semiconductor integrated circuit and master slice chip - Google Patents

Abstract

PURPOSE:To contrive improvement in the uniformity of the delay time between signals, in simplification of wiring and in efficiency of wiring work by a method wherein a suitable number of fundamental wirings are formed in the titled integrated circuit beforehand. CONSTITUTION:A contact X1 and/or X4 and Y1 and/or Y4 which are connected to the gate of a gate array, for example, formed in an element region 1a are provided, the contact X1 and/or X4 is connected to a clock phi1, and the other contact Y1 and/or Y4 is connected to a clock phi2. In this case, a pair of fundamental wiring 3a for clock (clock phi1) and 3b (clock phi2) extending in the longitudinal direction (array direction) are provided in a wiring region 1b. These fundamental wirings 3a and 3b for clock, which are extended making an almost straight line, have the length same as that of the wiring region, and are provided in the well-kown arrangement relations which will be used as the prestage for a mutual wiring design.

Description

[Detailed Description of the Invention] The device @ relates to integrated circuit technology, and is a master slice type integrated circuit that facilitates interconnection between elements.
This is used for the manufacturing method and the master slice chip used in the manufacturing method.

There is a known master slicing method in which all parts of an integrated circuit up to the last O metal evaporated wiring are made in exactly the same way, and only the last metal evaporated wiring is changed to produce an integrated circuit having a different function. Like this! In a star slice integrated circuit, an element area in which semiconductor elements are arrayed on one chip and an O wiring area for wiring between these elements are predetermined on one chip. are interconnected with different wiring patterns depending on the product type to form an LSI &

Therefore, the master slice satisfies the optimum set of chips, and it is possible to design the circuit according to the customer's order9.It is highly flexible and has four colors. This is an indication. That is, Mr. Sly step 1 has an element area of 1 m.
, has a edging area 1b% and a field area 1e. Element area 1a
A large number of arbitrary semiconductor elements such as iFi transistors are arranged in a 7-lay pattern.

In the section where the arrangement Ii1 for connection is applied, a plurality of horizontally extending underpasses (player arrangement layer) 2 are provided in a single row array #C. These underpasses 2 are
Usually, it is formed using polycrystalline silicon, or a diffusion layer of #iP+ diffusion or N+ diffusion.

On the other hand, the contact-to-contact wiring is constructed by depositing a metal such as KAt on the insulating layer existing on the upper surface of the chip and forming a pattern. In Figure 1, points A, B, and C are shown.
This is a water tank connected using a metal layer 2' and a broken layer 2.

In the conventional master slicing method such as CD, contacts are formed in a random configuration in the wiring area 1b of the chip in mutual arrangement II for connecting desired contacts. D shown in Fig. 2 is a two-phase clock φ, (center @
) and φ, (points) are mutually wired by the conventional method, and the clock φ is within the wiring region lb.

and φ! The wiring paths for each have an arbitrary ρ complex shape. In this conventional method, if the wiring is not carefully designed, there is a possibility that the wiring lengths and wiring routes of the clocks φ, φ, and D may be significantly different from each other, resulting in circuit malfunction. Something happened. Furthermore, as shown in Figure 2, in the conventional technology, the reset edge, which is provided over the entire chip, has more branches and bends than necessary, making the total wiring length too long. Wiring errors often occurred.

As described above, in the conventional technology in which all the inter-element arrangements I are randomly interconnected at the same level, it is necessary to pay special attention to the wiring design for nodes etc. where it is necessary to compensate for the phase shift between signals. Ta. Furthermore, even for wiring for signals that need to be supplied to almost the entire chip D, such as clock signals and reset signals, wiring must be performed for each custom wiring, which hinders the reduction of wiring work time.・Additionally, 1 automatic routing [When performing automatic routing, there is a risk that the wiring lengths will be completely different even if the two nodes are connected with strict delay requirements. The range was narrow.

The present invention has been made in view of the above points, and particularly includes wires used throughout the circuit, such as crosstalk wires and reset wires. Similar to the m-source line, the basic wiring is preliminarily arranged in a regular configuration with θ, and this basic wiring no-turn has the required contact distance ti 4o, which facilitates the layout design and manufacturing, and makes it possible to equalize the amount of delay in node connection, and a method for manufacturing the circuit device, and the method thereof! The purpose is to provide a master slice chip that can be used directly in an IC.

According to one aspect of the present invention, an element region having a plurality of semiconductor elements arranged in at least one array, and an element region extending in a direction substantially perpendicular to the array, A wiring area having a plurality of wiring layers and a wiring area having a plurality of wiring layers are alternately arranged.
Kudos to the master slice chip that broke 1! IO mutual arrangement I
A method for manufacturing a semiconductor integrated circuit by forming m,
the element region and/or arrangement substantially parallel to the array; An appropriate number of basic layouts with approximately the same length as the area and arranged at predetermined intervals! A mutual wiring pattern is formed by the ``turn'' and a connection pattern that continues between the IO contacts on the master slice chip, and a mask for mutual wiring is formed based on the mutual wiring and the IO contacts. %t) provides a method for manufacturing a semiconductor device having each step of forming all interconnections on the master sliced chip using a mask.

According to another feature of the present invention, there is provided an element region having a plurality of semiconductor elements arranged in at least one row of arrays, and several trench wiring layers extending approximately 100 degrees to the array. A suitable number of master slice chips are arranged in parallel with each other, and the element regions and/or the arrays are arranged substantially parallel to the array. A master slice chip 141 provided as a basic wiring pattern t-dense layer having approximately the same length as the area and arranged at predetermined intervals to form part or all of the mutual wiring pattern to be formed on the master slice chip. is also O.

Attached below! ! Detailed explanation of specific embodiments of the present invention with reference to the 5th picture #! I will explain. Figure 1183 shows the present invention 0
1 is a schematic diagram illustrating the principle of a master slice integrated circuit device manufactured according to the method of the present invention; FIG.
It shows. As shown in FIG. 3, the contacts X1 to Y+ and Y+ to Y4 provided in the element region 11, for example, the gate KWea8 of the gate array are f&, and the contacts X1 to X, the Fi microk,
On the other hand, contacts Y to Y4 are in contact with clock φ, kJc
-g is broken. In this case, according to the present invention, the wiring area l
The basic arrangement for clocks of 61 pairs of extending blocks 13 m (for clock-1) and 3b (for crotter 8) is fjFf in the storage area lbO longitudinal direction (array direction)
It is being The basic clock wiring lines 3a and 3b, which are extended in a detailed manner, have approximately the same length as the feldspar in the 11w area, and are prepared in advance with a predetermined arrangement relationship as a step before mutual wiring design. Ru.

The basic arrangement J13m, 3b prepared in this way [for
Respective contacts X1 to Yl in the element region l&
Connection arrangement f ms to - and Ka! from Y4 to desired basic wiring 3m, 3bK! Or n4t layout, basic arrangement! Connection wiring between I3 and contact X, Y and 0, and
113 A mutual interconnection pattern is formed with arbitrary inter-contact OiI interconnections in the lying element region (not shown in the figure). A mask is formed based on the mutual wiring pattern formed by this process, and the mutual wiring pattern shown in FIG. 3 is formed using the master TGL. It is possible to form.

2-phase clock φ1 and φ as the 31st AKF1 basic wiring.
Although only the basic wiring for the clock for , is shown, it is possible to provide an appropriate number of other basic wirings, such as basic wiring for the K11l source voltage and refresh signal, depending on the requirements. Also, as shown later, such a basic arrangement 1Ik
It is not necessarily necessary to provide Kv& within the wiring region, and if possible, considering parasitic effects etc., it is also possible to provide Kv& within the element region la. In addition, 3I! 11, there are a plurality of wires D arranged horizontally within the wiring area lb.
An under female is provided, which is a must! ! Needless to say, it can be used for connection between elements, etc., depending on the requirements. IH3m
The wiring running horizontally and the wiring running vertically are connected to the wiring running horizontally and the wiring running vertically. Should be both! IK) Drill holes in the insulating layer at the intersections to form contacts and connect both layers.

As described above, in the present invention, within the interconnection pattern formed on the master slice step, the clock lines and refresh lines that are commonly used for the entire chip D are connected to the basic wiring. Since the configuration is such that a connection/distribution system is provided in advance to connect IIO contacts based on these p basic wirings, it is possible to design the wiring in an orderly manner. For example, based on the present invention shown in FIG. The lines connecting the contacts and the required clock lines are all approximately the same length.As a result, the amount of signal p delay caused by the wiring is approximately equal, and the possibility of malfunctions is significantly reduced. In the present invention, since the interconnections are arranged in an orderly manner, the efficiency of wiring work can be improved.
Iv1q potential is significantly reduced.

In addition, Figure #I4 is a %D diagram schematically showing the nine master slice molds of the manufacturing factory based on the prior art, and Figure 5 is a diagram schematically showing the 9th master slice mold collection and the IllFm path 0 distribution shape according to the present invention. Several books
This is a schematic diagram of a master slice integrated circuit manufactured using nine basic interconnects [3].

From the comparison of these two figures, it can be seen that the present invention reduces folding parts and has a simple Al-bond mutual arrangement! lt is possible to create an image and therefore mutual arrangement! It can be seen that it is possible to simplify the wiring work of forming an integrated tube and improve the yield.

FIG. 116 is a schematic plan view of an integrated circuit manufactured according to the method of the present invention.

As shown in the figure, this case is 0! Star slice chip D wiring area 1bKhi 3-column array (temporary wiring layer 2 is cut out, center C) buried wiring layer array D 3 p basic wiring layer 3m + 3b * 3t is shape 1i! It's out of place. These basic wiring layers 3m+3b and 3etf are used for power supply, clock signal supply, refresh signal supply, etc. Also, 11M! ! The required D connections are made through the 4 wires and the contacts 5.

Figure j17 shows the 0 interconnection parameter [formation 640] as in the 6th m, but #! In the case shown in Figure 7, the basic arrangement @ 3'a, 3'b, 3'c C) is different. That is, in the case shown in FIG. 7, the basic wiring Is a'a, 3'b * 3/cd jil wiring layer 2 and the same IIK are formed in the master slice chip in advance.

Therefore, Fig. 117 P field meeting basic wiring 3'at 3'b
.

3'c is formed as the same @Kl silicone layer or diffusion layer as the m general wiring layer 2, but as shown in p11a in D (different from the basic wiring 3at 3be 3g formed of metal). @ 3'a I 3'b #3'
If the configuration is made in advance in the efr master slice chip, mutual alignment, @CS manufacturing factory'f:ll
K can be simplified.

The JIB diagram shows the case where the present invention is applied to the master slice step of a CMOS gate array 4.

In this case, the N-type diffusion layer 6a and the PW diffusion layer 6b have
An Iv silicon gate 7 is provided as a common gate for both. Moreover, the underpass 8 related to the KFi diffusion layer or polysilicon related to 0MO8 is formed by the shape fR.
Ru. Basic arrangement 13&*3b, 3a, 3dd element area 1a
An insulating layer is deposited within the insulating layer. In this case, not only the semiconductor element O but also the underpass 8 are carved in the element region 1a! I'm vomiting. 12) In this specification, an element region and a wiring region refer to an element region KjiI- which has at least a semiconductor element, and a wiring region Kk which has at least a wiring field layer. So,
Additionally, it may be %ID that has a separate f)fjE meeting.

In addition, j1g#Ac' structure 1i! [In the case of fFIJ, it is possible to use it as a basic wiring @ 3 b t VDD line and as a basic wiring * 3 @ t V @ @ wire.

As explained in detail above, according to the present invention, by preparing an appropriate number of basic wiring lines in advance, it is possible to equalize signal spacing, simplify wiring lines, and improve the efficiency of wiring work.
The master slice type integrated circuit r)**V can be further improved. Note that the present invention is based on the metal wiring layer aK.
It is D that can be applied regardless of the situation, and it is impossible to create a basic system that can be applied. Gaba, 8 pits) OCP
Circuit #1 with many opportunities to interface with the U (central processing unit) It can be done in an orderly manner. It goes without saying that the superposition is not limited to the specific specific implementation described above, and that various ρ modifications are possible within the technical scope of the present invention. For example, the position, number, material (metal, silicon, diffusion, etc.) of the basic wiring II to be fabricated can be selected according to appropriate conditions.

[Brief explanation of the drawing]

Fig. 181 is a schematic diagram showing the overall configuration of the conventional master slice step D, Fig. 12 is an explanatory diagram showing mutual interconnection based on the prior art, and Fig. 3 is an explanatory diagram showing mutual interconnection based on the principle of the present invention. FIG. 4 is a schematic diagram of the master slice step shown in the conventional technique 111 with mutual wiring, and FIG.
t-shaped lI [Schematic diagram of the master slice chip shown,
FIG. 6 is a partial plan view showing an example of an integrated circuit manufactured according to the present invention, FIG. FIG. 3 is a partial plan view of another example of an integrated U-way manufactured based on the same method; (Description of code V) 1: Master slice step 1 凰: Element area 1b: Wiring area 2: Embedded wiring layer 3: Basic wiring 11 4
: Connection line 5: Kontatato Patent Applicant Rico Co., Ltd. - Figure 1 Figure 2 Figure 3 Figure 5 Figure 10 Figure 6 Figure 7 Figure 8 Figure 0

Claims (1)

[Scope of Claims] 1. An element region having I[a semiconductor elements arranged in at least one row of arrays and a buried wiring layer t-cover provided extending in a direction substantially perpendicular to the array. A master slice chip in which an appropriate number of arrangement areas are arranged alternately. In a method of manufacturing a semiconductor integrated circuit by forming cs interconnections, the element region and/or the interconnects are substantially parallel to the array. An appropriate number of basic wiring patterns having approximately the same length as one area and arranged at predetermined intervals and connection patterns connected to the contacts on the master slice chip are used to form interconnected IIA turns. Then, form a mutual wiring mask based on the mutual wiring @A turn, and form 7 [[) mutual wiring aiiv on the master slice chip using the thus formed mutual wiring mask. A method for manufacturing a semiconductor integrated circuit, characterized in that it has St. 2. An element region having a plurality of semiconductor elements arranged in an O array in at least t1 rows and an arrangement region having a plurality of semiconductor elements in the trenched wiring layer 1 extending in a direction substantially perpendicular to the array. In an appropriate number of master slice chips arranged alternately, the slices are substantially parallel to the play, have approximately the same length as the element area and/or wiring area, and are arranged at predetermined intervals. A basic wiring pattern meeting, which is a part of the mutual arrangement-no-turns to be formed on the master slice chip! A master slice chip with a 1% image provided as a 1e layer.