JPS58154262A - Complex semiconductor device - Google Patents

Complex semiconductor device

Info

Publication number
JPS58154262A
JPS58154262A JP57037622A JP3762282A JPS58154262A JP S58154262 A JPS58154262 A JP S58154262A JP 57037622 A JP57037622 A JP 57037622A JP 3762282 A JP3762282 A JP 3762282A JP S58154262 A JPS58154262 A JP S58154262A
Authority
JP
Japan
Prior art keywords
substrate
light receiving
receiving element
light
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57037622A
Other languages
Japanese (ja)
Inventor
Shuzo Kagawa
修三 香川
Takao Kaneda
隆夫 金田
Takashi Mikawa
孝 三川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57037622A priority Critical patent/JPS58154262A/en
Publication of JPS58154262A publication Critical patent/JPS58154262A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/1443Devices controlled by radiation with at least one potential jump or surface barrier

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To improve characteristics such as frequency characteristic and light receiving sensitivity and contrive the miniaturization and high reliability of a light receiving device, by forming light receiving elements and transistors on a single Ge semiconductor substrate. CONSTITUTION:The light receiving element is constituted of a P-N junction constituted of the Ge substrate 1 having one conductivity type and the first reverse conductivity type region 2 which is provided selectively on one main surface of the substrate 1. An insulation gate type semiconductor element is constituted of the second and third reverse conductivity type regions 3A and 3B provided on the main surface of the substrate 1 by being isolated each other, and a gate electrode 7 provided on the surface of the substrate 1 between the regions 3A and 3B via an insulation film 4''. Thereby, it becomes fit for the wavelength which is regarded as optimum in transmission by optical fibers, and brings further improvement of characteristics and further improvement of the miniaturization and reliability of a device, as compared with a conventional device.

Description

【発明の詳細な説明】 (−発@O伐術分野 本発明は、波長1.OJIm乃至1.55μs4直に対
応する受光素子とトランジスタとを同一基板上に設は九
複合半導体装置に関する0 4b)  技術O″f11に 光ファイバ通1方式の実用化によりて知られるように、
光フアイバ自身の進歩とともに4!r種の元デバイス技
術が開発されてiる0すなわち、光を導波路内にとじ込
めて扱う固体化され走光デバイス、例えば半導体レープ
などの発光装置、フォトダイオードなどの受光装置、光
スィッチ、光コネクタ等が開発され、これ、らの光デバ
イスによって構成され九システムは性能はもとより、1
1!幀性及び経済性が大幅に改善されている0 この光デバイス技術は、単一のmar有する個別のデバ
イスtv&供するjl[に止まらず、さらに^性能化、
小形化、高信頼化を進めるために、機能をJ%にする複
数の素子を複合、集積すること管志向してiる。その−
の方向として、元入力16号を一旦電気信号に変換して
、増幅、波形壷形、−1演算もしくは変復調等を行い、
梃に光出力18号t−制御する場合などに心優とされる
元電変換回路中電子回at同一基板上に形成することが
試みられている〇 これらの元デバイスの対象とする元+14の波長は、化
学気相成長法等による低損失化によシ、光ファイバでの
伝送損失の極小が波長1.55^謳へ移行し、を九波%
13声諷ではjt7アイバの材料分散が零と−なる時黴
會有する九めに、波長1.0岸講乃至1.5s#@4f
olI囲が本命とみられている0こO#長I QJs+
乃至1.5 Ssm 機11K>ケb半4体受元素子に
は、シリコン(81ンよpバンドギャップの狭い半導体
材料が必要とな)、その候補としてはゲルマニウム(G
 a )中InGaAs、InGaAsPなどの三元も
しくは四元厘−■族化合物半導体があげられる◎ 前記半導体材料による受光素子は既に多くの試みが報告
され、G・受光素子は既に実用化されているが、単体の
受光素子と外部増ll1g1路とを用いて出力11号を
取出した場合には配置1部分のキャパシタンス、インダ
クタンスの#譬等によって特性がItIIl@されるな
どの不都合があり、先に述べた如、:1゜ く、受光素子とトランジスタ素子等とt−複合・集積す
ることがjitLい0 (0発明の目的 本発明は、単一のゲルマニウム半導体基板上Vこ、受光
素子とトランジスタを形成することによって、配線部分
の中ヤパシタンス、インダクタンスナトを減少して、周
波数特性受光感匿などの特性を向上し、かつ受光装置の
小型化及びI%i6僅禎化t4める複合半導体装rll
JII4:φ膜造l−會提供すること上目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a composite semiconductor device in which a light-receiving element and a transistor corresponding to a wavelength of 1.0JIm to 1.55 μs are provided on the same substrate. ) As is known with the practical application of the optical fiber transmission method in technology O''f11,
4 along with the progress of optical fiber itself! R types of original device technologies have been developed, i.e., solid-state phototravel devices that confine light within a waveguide and handle it, such as light-emitting devices such as semiconductor tapes, light-receiving devices such as photodiodes, optical switches, and optical devices. Connectors, etc. were developed, and nine systems made up of these and other optical devices not only had high performance, but also
1! This optical device technology has significantly improved affordability and economic efficiency.This optical device technology is not limited to providing individual devices with a single mar.
In order to promote miniaturization and high reliability, we are aiming to combine and integrate multiple elements with J% functionality. That-
In the direction of
Attempts have been made to form the electronic circuit in the power conversion circuit on the same substrate, which is considered to be convenient when controlling the optical output No. 18 using a lever. Due to the reduction in wavelength loss through chemical vapor deposition, etc., the minimum transmission loss in optical fibers has shifted to a wavelength of 1.55, and the wavelength has decreased by 9%.
In the 13th tone, when the material dispersion of jt7 Aiba becomes zero, the wavelength is 1.0 s to 1.5 s#@4f.
OlI Kai is considered to be the favorite 0koO#long I QJs+
1.5 Ssm Machine 11K>keb For the semi-quadramid receiving element, silicon (requires a semiconductor material with a narrower p bandgap than 81 nm), germanium (G
a) Among them are ternary or quaternary compound semiconductors such as InGaAs and InGaAsP. Many attempts have already been made to create light-receiving elements using the above-mentioned semiconductor materials, and G-light-receiving elements have already been put into practical use. If output No. 11 is obtained using a single light-receiving element and an external amplifier, there are inconveniences such as the characteristics being changed due to the capacitance and inductance of the arrangement 1, as mentioned earlier. For example, it is possible to combine and integrate a light receiving element, a transistor element, etc. by 1 degree. By forming a composite semiconductor device, it is possible to reduce the intermediate capacitance and inductance of the wiring portion, improve characteristics such as frequency characteristics, light reception sensitivity, etc., and also reduce the size of the light receiving device and reduce I%i6.
JII4: The purpose is to provide a φ membrane fabrication l-meeting.

(西 発明の構成 本発明の目的とする複合半導体装置は、−導電11を有
するゲルマニウム基板、IW記ゲルマニウム基板と轟鋏
基板の一方の主面に選択的に配設された第1の反対導電
型領域とからなるPN接合から構成される受光素子、及
び前記ゲルマニウム基板の罰紀主向に互いに蟻隔して配
設された第2及び第3の反対導電型ill域と当該第2
及び第3の反対尋mIjji領域間の基板表面に絶縁膜
を介して配設されたグー)1他とをMlする絶縁ゲート
型千尋体凧1:、− 子とを含むことt−%像とするものである。
(Structure of the Invention A composite semiconductor device as an object of the present invention comprises: - a germanium substrate having a conductor 11; a light-receiving element constituted by a PN junction consisting of a type region, and second and third illumination regions of opposite conductivity types disposed at an antagonal distance from each other in the vertical direction of the germanium substrate;
and a third insulated gate type chihiro body kite disposed on the substrate surface between the regions with an insulating film interposed therebetween. It is something to do.

(・)発明の実施例 以下、本発明を実施例によp1図面を一照して具体的に
説明する〇 受光素子と同一基板上に形成するトランジスタとしては
、製作工程数が少い電界効果トランジスタ(以下FIT
と略称する)が適してお勤、特に半導体基板がゲルマニ
ウムである場合に拡絶縁ゲート杉(以下MI8と略称す
る)FETが最も適当である0午ヤリアの移動度はダル
マ二りムにおいても他の半導体#科と同様に電子が正孔
よプ大きく、電子のil#[μsx&、600ai/V
@5eas正孔)移動[sp −1,800d/V @
8@ c 41i!f”t”あり、#1Ml8FETは
nチャネル形とすることが有利である@そのために本実
施例においては基板の導電型はpliiとする@ 第1図乃至第3図は本発明の実施例の製造工場【示す断
面図である◎第1図に示す如く、キャリアー縦がlXl
0  am  禍度のp臘ゲルマニクム基板1に受jt
素子のn 領域2及びMISFETのソース及びドレイ
ンとするn領域3ム、 3Bを形成する。本実施例にお
いては、これらOnn職域2び3ム、 3Bは、フォト
レジストt−マスクとして、イオン注入法によって砒素
(As)を加速電圧100kCVail!においてドー
ズm5xlO”ω4程度に注入し、温度約550℃、1
時間楊度のアニールを厖すことにより同時く形成した。
(・) Examples of the Invention The present invention will be explained in detail below using examples with reference to the drawings on p. Transistor (hereinafter referred to as FIT)
In particular, when the semiconductor substrate is germanium, the expanded insulated gate cedar (hereinafter abbreviated as MI8) FET is most suitable. Similar to the semiconductor # family, electrons are larger than holes, and electron il# [μsx &, 600ai/V
@5eas hole) transfer [sp -1,800d/V @
8@c41i! f"t", it is advantageous to make the #1Ml8FET an n-channel type.@Therefore, in this embodiment, the conductivity type of the substrate is set to plii.@Figures 1 to 3 show the structure of the embodiment of the present invention. Manufacturing factory [This is a cross-sectional view showing ◎ As shown in Figure 1, the carrier length is lXl
0 am P germanium substrate 1 of the degree of misfortune
An n region 2 of the element and n regions 3 and 3B to be used as the source and drain of the MISFET are formed. In this embodiment, these Onn areas 2, 3 and 3B are used as photoresist T-masks to inject arsenic (As) by ion implantation at an acceleration voltage of 100 kCVail! was implanted at a dose of m5xlO"ω4 at a temperature of about 550°C and 1
They were simultaneously formed by annealing for a long time.

次いで第2図に示すμ口く杷−膜4,4′及び41t形
成する。ただし、絶縁ll&4’は受光素子の人力信号
光に対して反射防止、膜として機能し、絶縁膜41はM
ISFETのゲート絶縁膜として砿能する〇絶1111
1i%4’が反射防止膜としての機能を果すためには、
光学的薄膜による光の干渉に関して既に矧られている厳
適櫃があり、本実施例においてもこの値を標準憾とした
。その例として波長1.3μ票の入射光に対して、絶縁
膜4′が窒化シリコン(Si、N4)よりなるときに厚
さ180m@、二ば化シリコン(SiOx)よりなると
きに厚さ2301+s等があげられる。
Next, the μ-loquat films 4, 4' and 41t shown in FIG. 2 are formed. However, the insulation film 41 functions as an anti-reflection film for the manual signal light of the light receiving element, and the insulation film 41
〇1111 can be used as gate insulating film of ISFET
In order for 1i%4' to function as an antireflection film,
There are already strict limits regarding light interference due to optical thin films, and this value was also set as a standard value in this embodiment. For example, when the insulating film 4' is made of silicon nitride (Si, N4), the thickness is 180 m@, and when it is made of silicon dioxide (SiOx), the thickness is 2301+s for incident light with a wavelength of 1.3 μm. etc. can be mentioned.

ま友絶嫌膜4Nはその組成によって半導体の表向準位が
変化するなどの理由によりて、MISFh:Tの特性に
大きい影響を及ぼすゲート絶縁膜として機能するために
、その組成、厚さ等はMISFETに求める特性により
、かつ基[O導電11に応じて選択される◎ 一般には、絶縁膜4,4′及び41の材料としては、8
1sN4.810m及び酸化アルixウム(楠騙等が適
癲であp1必費に応じて、二種以上のIIAを重畳して
もよi口 これらの絶縁属を形成するには、低温で実施可能な化学
気相成員法(以下CVD法と略称する)、4IKプラズ
マCVD法が適癲であって、既に報告されて−る各種の
方法が適用可能である0本夷庸例においては、絶I&J
IK4,4−41はプ91CICVD法によ)、シラン
(81&)及びアン毫ニアCN&)tMvh%亀直約3
20℃にお−て、allN4属を厚さ1110鳳11に
形成し、弗化アン%具つムCNHhF)二弗化水素()
I F)コ!O:1のエッチャントによって、絶縁属4
1部分t4さ約60mmに、塘九電楓11゜ 形成〇九めO開口部を設けるエーチングtJIIL九〇
次iでjll&$1iii11に示す如く、蒸着法によ
りてアル1二りム(ムL)層を形成し、パター二ンダを
施すことによって、受光素子のn儒電lis並びKMI
8FWTのソース・ドレイン電極6ム、 (3B及びゲ
ート電極7t−形成し九〇受元素子のpiJi喝極とし
ては、この複合半導体素子基板の底面を金(Au)めっ
111ijにダイボンディングするl1111立法によ
る場合は、自づからAuG・合金層が形成されるため販 に特に加工する必要はないが、基事戚面にAuG・蒸着
を行ってもよい。咳、不実施例ではAuG@蒸着により
p@鴫離礁8f形成し麺。
The composition, thickness, etc. of the Mayuzetsu-gai 4N function as a gate insulating film that greatly affects the characteristics of MISFh:T due to reasons such as changes in the surface level of the semiconductor depending on its composition. is selected depending on the characteristics required for the MISFET and according to the group [O conductivity 11] Generally, the material for the insulating films 4, 4' and 41 is 8
1sN4.810m and aluminum oxide (Kusudama et al. may superimpose two or more types of IIA depending on the requirements).To form these insulating materials, conduct at low temperature. In extreme cases, the chemical vapor deposition method (hereinafter referred to as CVD method) and 4IK plasma CVD method are suitable, and the various methods already reported are applicable. I&J
IK4, 4-41 was prepared using CICVD method), silane (81 &) and Annexia CN &) tMvh% Kame Nao approx. 3
At 20°C, allN4 was formed to a thickness of 1110°C and hydrogen fluoride (CNHhF) hydrogen difluoride () was formed.
IF) Ko! O:1 etchant makes the insulating metal 4
Etching tJIIL 90th i to provide an opening at 11° in diameter of about 60 mm in 1 part t4, Al 12 rim (mu L) by vapor deposition method as shown in 11 By forming a layer and applying a pattern, the KMI
8FWT source/drain electrodes 6m, (3B and gate electrode 7t) are formed, and the bottom surface of this composite semiconductor element substrate is die-bonded to gold (Au) plating 1111 as the piJi electrode of the receiving element. If it is based on legislation, an AuG/alloy layer will be formed on its own, so there is no need for special processing for sales, but AuG/evaporation may be performed on the basic surface. As a result, p@Shiru Reef 8F was formed and noodles.

次に本実l1fA例の構造を有する複合装置の動作を説
明する0側4図は受光素子とMISFETを組み合わせ
て光検出器を形成する場合の結罎図である0図面におい
て、R1はバイアス抵抗、島は貞荷抵抗を示している0 nll電fi5とpil1区極8閣には逆バイアスの電
圧が印加されてお9、受光素子に元が入射されていない
法−では、バイアス抵抗R1と受光素子の見かけ上の抵
抗の分圧比に相″ムする電圧がゲート峨憔7に印加され
ている。しかし光が41!!縁濃4′を逃して受光率子
へ入射されると受光素子のPN接合部で光起醒力が発生
し、受光素子にキャリアが流れる為、受光素子での見か
け上の抵抗が1がる口即ち、ゲート電#7.7にかかる
電圧が低下してMISFETでの増幅度が低下する。こ
れより、負荷抵抗&の両端にかかる出力電圧が小さくな
り1光が受光素子へ入射されたことを検出出来る0以上
の如くにして形成されたMISNETによって受光素子
の出力電流の増幅器tlIl成した結果、従来19周波
a籍性及び受元感飄が向上し、かつ小型化された受光装
置を構成することかで龜た。
Next, the operation of the composite device having the structure of this practical example is explained. Figure 4 on the 0 side is a conclusion diagram when a photodetector is formed by combining a light receiving element and a MISFET. In Figure 0, R1 is a bias resistor. , the island shows a charge resistance. 0 A reverse bias voltage is applied to the nll electric fi5 and the pil1 ward pole 8. In the method in which the source is not incident on the light receiving element, the bias resistor R1 and A voltage that matches the voltage division ratio of the apparent resistance of the light receiving element is applied to the gate gate 7. However, if the light misses the 41! edge concentration 4' and enters the light receiving element, the light receiving element A photowake-up force is generated at the PN junction of the PN junction, and carriers flow into the photodetector, which increases the apparent resistance of the photodetector by 1. In other words, the voltage applied to the gate voltage #7.7 decreases, causing the MISFET to As a result, the output voltage applied to both ends of the load resistor & becomes smaller, and the MISNET formed as above 0 can detect that one light is incident on the light receiving element. As a result of constructing the output current amplifier tlIl, the conventional 19-frequency a characteristic and reception sensitivity have been improved, and it has become possible to construct a smaller light receiving device.

本*mnの受光素子に、ガードリングを例えばn+領領
域り深いn領域を形成するなどの方法によって設けてア
バランシ翼ホトダイオード(APD)とすることも軽易
であって更に受光感1會向上することができる口 また、以上説明した実t’sの導′1臘t1i転してn
、mの基板を用いて、pチャネル形のM I 81に2
Tを形成することも可能でお)、この#I成はイオン化
率の大きい正孔によりアバランシェ増倍tおこさせるタ
イプの低−置屋G・−APDK遍している0(f)  
発明の効果 本発明は以上説明した如く、波長1.0μ婁 乃至1.
5sμl楊度に対応した受光素子とトランジスタとの複
合半導体装置を1単一のゲルマニウム牛導体基板上に線
受光素子とMI 13 Fj、Tを形成することによつ
て提供するものであって、元ファイノ(伝送において蛾
適とされる波擾に適合し、かつ、従来技術による個別の
懺能會有する元デノ(イスと電子回路による受光装置に
比較して、時性の向上、装置の小臘化、gi!]iiK
の同上をもたらし、光7アイバ通僅の進展に大きくを与
するものでめる0
It is also easy to form an avalanche wing photodiode (APD) by providing a guard ring on the light receiving element of this *mn by a method such as forming a deep n region in the n+ region, and the light receiving sensitivity is further improved. In addition, the above-mentioned actual t's leads to
, m substrate, p-channel type M I 81 2
It is also possible to form a T), and this #I formation is a type of low-Okiya G-APDK that causes avalanche multiplication by holes with a high ionization rate.
Effects of the Invention As explained above, the present invention has a wavelength of 1.0 μm to 1.0 μm.
A composite semiconductor device including a light receiving element and a transistor corresponding to 5 s μl density is provided by forming a line light receiving element and MI 13 Fj, T on a single germanium conductor substrate, and the original Phyno (compatible with wave disturbances that are suitable for transmission), and has an individual function using conventional technology (improved timing and smaller equipment compared to light receiving devices using chairs and electronic circuits) Rinka, gi!] iiK
It brings about the same as above and greatly contributes to the progress of light 7 Aiba communication.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第1図は本発明の実り例を示す断面図である
0 図において、1はp型ゲルマニウム基板、2は受光素子
のn+a域、3ム、3BはFETのn1領域、4.4’
及び41は絶縁膜、5は受光系子のn1Xil電極、6
ム、6BはFETのソース・ドレインIL億、7はyg
’rのゲート(憾、8はp−電=1示す0尭1図 應 2 図 第 3 圀 第 4 口
1 and 1 are cross-sectional views showing practical examples of the present invention. In the figures, 1 is a p-type germanium substrate, 2 is an n+a region of a light-receiving element, 3 is a n1 region of an FET, 3B is a n1 region of an FET, and 4. 4'
and 41 is an insulating film, 5 is an n1Xil electrode of the light receiving element, and 6 is an insulating film.
6B is the source/drain IL of the FET, 7 is yg
Gate of 'r (Sorry, 8 indicates p-electron = 1)

Claims (1)

【特許請求の範囲】[Claims] 一導電aitt有するゲルマニウム基板、前記ゲルマニ
ウム基板と轟該基板の一方の主面に選択的に配役された
IIILlの反対尋電履領域とからなるPN接倉から構
成される受光素子、及び前記ゲルマニウム基板の前記主
面に亙1/mK1111隔しそ配役され九票2及び纂3
0反対導電渥領域と幽該第2及び第3の反対導m虚領域
間の基板表面に絶縁属を介して配設されたゲート電極と
會弧する絶縁ゲート蓋半導体素子とを含むことを特徴と
する複合半導体装置0
a germanium substrate having one conductor; a PN bonding element comprising a germanium substrate and an opposite electrode region of IIIL selectively arranged on one main surface of the substrate; and a light receiving element comprising a germanium substrate. On the main surface of ``Kiwa 1/mK1111'', 9 votes 2 and 3 were cast.
The invention is characterized in that it includes an insulated gate lid semiconductor element that interacts with a gate electrode disposed on the substrate surface between the imaginary and second and third oppositely conductive imaginary regions with an insulating metal interposed therebetween. Composite semiconductor device 0
JP57037622A 1982-03-10 1982-03-10 Complex semiconductor device Pending JPS58154262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57037622A JPS58154262A (en) 1982-03-10 1982-03-10 Complex semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57037622A JPS58154262A (en) 1982-03-10 1982-03-10 Complex semiconductor device

Publications (1)

Publication Number Publication Date
JPS58154262A true JPS58154262A (en) 1983-09-13

Family

ID=12502725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57037622A Pending JPS58154262A (en) 1982-03-10 1982-03-10 Complex semiconductor device

Country Status (1)

Country Link
JP (1) JPS58154262A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500466A (en) * 1983-11-21 1986-03-13 アメリカン テレフオン アンド テレグラフ カムパニ− photodetector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500466A (en) * 1983-11-21 1986-03-13 アメリカン テレフオン アンド テレグラフ カムパニ− photodetector

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