JPS58154259A - Preparation of semiconductor rom - Google Patents

Abstract

PURPOSE:To change an E-type MOS into a D-type by forming a gate oxide film and gate metal pattern on a semiconductor substrate surface, making thin said pattern in the region where the eyes of ROMs are to be formed and by changing a threshold voltage through implantation of ions. CONSTITUTION:A thermal oxide film 12 is formed on a semiconductor substrate 11 and moreover a silicon nitride film 13 is formed. The boron is implanted to the area from where the film 13 has been removed and a channel stopper 15 is formed. A field oxide region 16 is then formed and the films 12, 13 are removed. A gate insulating film 17 consisting of SiO2 is thereafter formed and a polycrystalline silicon is grown thereon at the entire part thereof by doping P or As in a high concentration. Ions are implanted with a metal pattern 18 used as the mask and the source, drain diffused layers 19 are formed. The metal pattern 18 in the region where the eyes of POM are to be formed is made thinner, ion is implanted therethrough and thereby the E-type MOS is changed to the D-type.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention provides a mask ROM for setting data during the manufacturing process.
The present invention relates to a method of manufacturing a semiconductor ROM such as ROM.

Conventionally, in order to configure a mask ROM in MI8 semiconductor DLC, data eaves generally depend on whether or not to connect a diffusion region formed on a semiconductor substrate and a layer formed by evaporation. I'm trying to do a lot of things. In other words, depending on whether or not a contact pad is formed to connect the metal and the diffusion region, the ROM can have four turns of data.
However, with the current demand for high integration density, contact holes are used to form RO
In the case of forming an M-shaped pattern, the area occupied by each memory element section becomes large, resulting in a large 4-inch area for high integration.

As a means to improve this point, N-channel g
/D MOS (m) The following is considered. In other words, after forming the J11 gate on the surface of the semiconductor substrate, Inject impurity ions with the same polarity as the source and drain, and form an e-) metal pattern thereon, and
Source and drain diffusion regions are formed on the substrate, and a contact hole is formed, a wiring metal layer is deposited, and a nolene layer is formed to form a mask ROM.

However, if the ROM is manufactured using this method, if the ROM number is changed frequently, the 'RO
Since the M-eye formation process is performed at the initial stage of the semiconductor ROM manufacturing process, a major problem arises. In other words, RO due to changes in stored data
It becomes difficult to promptly follow up on M's request for change, and problems with delivery times also arise.

This invention is based on the above-mentioned points, and makes it possible to sufficiently respond to requests for false integration, and even when there is a change in memory setting data. It is an object of the present invention to provide a method for manufacturing a semiconductor ROM such as a mask ROM that enables sufficient tracking.

That is, in the two-speed method according to the present invention, after forming an r-) oxide film on the surface of the semiconductor substrate and forming an ff-) metal arm turn, the 2-speed method forms the ROM eye. t-memory-) Make a thin metal layer, pass through this thin metal layer, implant impurities such as phosphorus or ion by ion implantation, and change the threshold voltage of the MI8 semiconductor device. The purpose is to change from enhancement salt to Deiderets V-Yon type salt.

A manufacturing method according to an embodiment of the present invention will be described below with reference to the drawings. This example shows the case using N-MOI. First, as shown in Figure 1, the P-type is 6 to 10 Ω".
(100) A thermal oxide film 12 of 200 to 1000 layers is formed on the surface 1 of the fourth semiconductor substrate DD ball made of single crystal silicon having a tilted crystal plane. Then, silicon nitride 1IXis is formed on this thermal oxidation g12, and this chamber 1
The hissilicon film 13 is partially removed except for an active region (a) and (4) to become a transistor or the like (MOI9) (111). What about the parts of the silicon nitride film 13 other than the removed viscous castle? A channel stock/415 is formed to prevent inversion due to the parasitic MO8 effect.

Here, the marked V recon film 13 may be removed by plasma etching with Freon gas using photorenost as a mask, leaving the activated region 14.

The silicon nitride film IJ acts as an oxidation-resistant mask against thermal sensitization of the semiconductor substrate 11, and by thermally oxidizing selectively using this silicon nitride film 11 as a mask, As shown in the figure, a field oxide film region 16 is formed.Then, the dimpled V-lipid film 11 and the thermal oxide film 12 are removed.In this case, the thickness of the oxide film in the field oxide film region IC is 0. It is sufficient that the thickness is about .7 to 1.2μ.

After removing the silicon nitride film IJ and the thermal oxidizer 12 in this manner, the portion other than the oxidation region 16, that is, the active region M14, is thermally oxidized to 50G-100.
An r-) insulation J[JF is formed by a silicon dioxide film of 0 μm. This carbon insulating film 11E4 is made of polycrystalline silicon coated with phosphorus or arsenic, and grown to a thickness of 0.3 to 0.4 .mu.m over the entire surface by, for example, a low pressure CVD method. Then, MO8) Selectively cover the r-t part of the transistor and the parts that will become the wiring layer with a resist, and remove the polycrystalline silicon in the part where the resist does not exist by plasma etching using Freon gas. f-') Metal pattern 1 made of crystalline silicon
form 8. Then, 1-this r as shown in Figure ′@3
-) Phosphorus or arsenic is ion-implanted using the metal pattern 18 as a mask to form MO8) source and drain diffusion layers 19 of the transistor.

Incidentally, the source and drain diffusions 1-19 were formed by ion implantation with the r-) insulating PIX 11tl remaining in the semiconductor layer, but this was done by exposing the surface of the portion where the source and drain expansion layer 19 was to be formed. Alternatively, a silicon dioxide film may be formed on the surface of the r-)* group Noreen 11 made of polycrystalline silicon.

Next, as shown in Fig. 84, the area other than the value range to be the 6280M eye is covered with a resist 20, and the polycrystalline silicon of the dart metal 9 turns 1a in the area to be the r-toe is covered with a Freon-based polycrystalline silicon. Plasmae, by Tschinda 0.1
~0,2 voice -fi [* to make it thinner. After that, using the resist 20 as it is as a mask, the source, P
Impurities with the same polarity as rain diffusion @19, such as phosphorus.

r-) Metal parable turn 11 made of thinned arsenic, Iron, etc.
A channel doped region is formed by implanting ions through the RO to change the enhanced deaf MO8) transistor to the r-prev1 type MO8) transistor.
Silicon dioxide 22 is formed on the entire surface by thermal oxidation so as to correspond to the M-shaped eyes 21, and a silicon nitride film 2S is further formed on the hill.
is formed on the entire surface with a thickness of 300 to 100X, and then, at t of this silicon nitride film 23, an interlayer insulating layer 24 made of a PSG film containing about 4 to 16% by weight of phosphorus is formed by 0.5% by weight.
Formed on the entire surface with a thickness of ~1.5 μm. This J-edge layer 24 is partially etched using a resist as a mask to form an opening 11.
is subjected to heat treatment at about 900° C. to 1100° C. using reflow technology to make the acute corners into a smooth shape.

At this time, the silicon nitride @21 formed on the entire surface acts as a stone Δ when etching the interlayer insulating layer 24,
In addition, for reflow heat treatment, for example, when performed in steam, it acts as an oxidation-resistant mask for the semiconductor substrate 11, the r-) button 1, and the turn 18.

Next, a contact hole 26 for electrically connecting the opening 25 is formed using a resist as a mask. Then, the aluminum layer containing 1 (..., ~2%) silicon is further deformed to form a pattern (desired as a resist mask), and heat treated at 400°C to 500°C to form a silicon-containing layer. Aluminum is deposited to form a wiring metal 1111F connected to the contact hole 16 including the contact hole 71.

After that, plasma CVDj was developed for /ftsu Vpe-Vay.
2. Thus, a silicon nitride film 2# is formed.

FIG. 115 is an explanatory diagram of a part of the mask ROM constructed as described above, viewed from the light.

Incidentally, the position of the ROM thus formed is specified by the data stored therein, and the embodiment shows one example thereof.

That is, in the above-mentioned manufacturing method, the polycrystalline silicon of the r-total turn 11 is selected and formed thinly in correspondence with the area that is to become the eye of the ROM.
Impurity ions such as ions are implanted to form a ROM as shown in FIG. In this case, r-to metal quantity turn 1
Since the # polycrystalline silicon is arbitrarily thinned and ion-implanted, ions can be implanted in a sufficiently low acceleration state, and in particular, OM eyes can be easily formed using an ion implanter that does not have insect acceleration energy. It depends on what you do. In this case, etching of polycrystalline silicon and ion implantation for forming ROM eyes can be performed using the same resist as a mask, which is effective in simplifying the manufacturing process.

As described above, according to the present invention, impurities can be implanted into the channel portion at a lower acceleration voltage through the 74 turns of polycrystalline silicon (metal) formed selectively. By changing the threshold voltage of the region, the enhancement type is changed to the dilation V-type to form the ROM eye. Therefore, by using L2 in this manner, it is not necessary to take up a special area for daily use of the ROM, and it can be made non-linearly advantageous for highly integrated C2. Also, f-
) Since the ion implantation condition from the 7th turn of the metal metaphor is a low acceleration voltage, the ion implantation process can be performed using an ordinary ion implanter. Therefore, the distribution of impurity ions can be well rebounded without depending on the variation in the thickness of the polycrystalline silicon, and the implantation conditions can be easily determined.

In addition, since the process of forming 110M meshes is performed after forming the r-) metal arm, it is possible to use the process for forming highly integrated mask ROMs, which is highly usable. , and has the excellent effect of being able to provide products in a short delivery time.

In the embodiment, in the N-ROM, the source.

Although the ROM was formed by implanting an impurity having the same polarity as the drain, it can be implemented in the same manner in the case of P-MO8, C-MO8, etc., or in the case of other semiconductor devices. Sara C
2. Is it okay to implant impurities with a different polarity from the source and drain, and in some cases change the threshold voltage? A non-polar impurity such as 1 may be implanted.

Here, the r-) gold j14 dove in the area that should be the eye of the ROM is arbitrarily set to 4 higher than the c-t metal dove in the other areas,
Since the purpose here is to apply a voltage of 1ki-1ll to this r-) portion, there is no need to consider the effect on the characteristics even if the metal layer is made thinner.

[Brief explanation of the drawing]

Figures 81 to g4 are nof-turn diagrams as seen from the perspective of one embodiment of the present invention. ″ 11...Substrate, 14...Activation region, 16...Field oxide film, 11...Dart oxide film, 1g...
r) Gold 24... Interlayer insulating layer, 27... Wiring metal layer. Applicant's agent, patent attorney Takeshi Suzue'・1 Figure 1! Figure I4fi5L4 Figure 7

Claims (1)

[Claims] Means for forming an r-) insulator in an active region of a semiconductor substrate surface, and means for forming an r-) metal pattern serving as an r-) arrangement on the r-) insulating film. , this r-gold m/4 turn between the sources. The above and the means to form a drain ambiguous layer? -Gold of the lane part corresponding to the selected ROM number of the mother turn of -T&-NO!
1441 thinner than other parts, and means for injecting charged particles into the E-era semiconductor substrate portion through the metal layer made thinner by this means to form a Channelel doped region. A method for manufacturing semiconductor ROM.