JPS58153489A - Address converting system of channel memory in time division exchange system - Google Patents

Abstract

PURPOSE:To secure the normal connection in case a fault arises to a part of the data area of a channel memory, by using a spare area to change the address of a faulty area given from a control memory to the address of the spare area. CONSTITUTION:A channel memory SPM-P receives the writing and reading addresses from a counter CNT and a control memory CM via selectors SEL1 and SEL2 respectively when no fault arises. Then the memory SPM-P performs an exchange connection between incoming and outgoing highways FHWM and BHWM after the sequential writing and random reading of the writing and reading addresses. If a fault arises within the memory SPM-P, the address of the SPM-P and the address of a spare area SRM-S to be switched are set to buffers BURO and BUR1 respectively by a control part CPU. When the address delivered from the selector SEL2 is csoincident with the fault address within the buffer BURO, a comparator COMP switches the selector SEL1. Then the address of the area SRM-S within the BUR1 is given to the memory SPM-P in place of the fault address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address conversion method for a communication path memory in a time-division conversion system, and more specifically, to a communication path memory and a control memory for the communication path memory to perform circuit switching. In the time division exchange method, from the upper rudder control memory, tfJff
The present invention relates to an address conversion method for converting the address into an address of a non-faulty part and sending it to the communication path memory when the data area of the communication path memory corresponding to the address information stored in the communication path has a failure.

BACKGROUND ART No. 1 is a diagram showing an example of a conventional communication path device in a time division switching system, which is configured with one stage of communication path memory.

In the figure, MPX is a multiplexing device, SPM is a communication path memory, DMPX is a demultiplexing device, and SEL is a selector, which constitutes a communication path device, and PF is a terminal such as a telephone, FHW1 to Fml. 's indicates 7ward highway, and BHW1 to BHIi'm indicate backward high.

The call data from terminal pp to terminal is PCM encoded and multiplexed into each of the forward-highway FHFt-FHW books according to the time slot (TS>~TSn) assigned to each terminal, and these etc. Forward book
The communications or speech data on the highways FHW, -F□III are further multiplexed by a multiplexer@xpx into one intermediate forward highway FHFI'H and input into the speech path memory SPH.

The above PCM encoded data time-division multiplexed by this multiplexer MPX is stored in the control memory C
The writing address information read from the MW is written to the communication path memo 175PH, and the reading address information read from the reading control memory CMR is written from the communication path memory SPM to the intermediate backward no.way HEWN. Demultiplexer 1D
Backward no iway BHWI~BHW with MPX
'm, and further separated into time slots and distributed to each terminal, where circuit switching is performed. In addition, a control memo for praise! /Address information output from CMw and control memo 9 for barking The address information output from CMR is switched and controlled by the read/write switching signals R/W and S in the selector SEL, and in the read/write cycle. Control memo for adding soda +7 CMW
The address information for setting in that is outputted by the CMR is selected, and the address information for reading that is output by the control memo for reading +7 CMR is selected in the setting cycle.

In this case, for inspection and extrusion 1. Control memory C
Either Af or CMH is sequentially
It is usually configured with a counter, and if a sequential counter is used as the write control memory CMw, sequential write/random read control is possible, and if a sequential counter is used as the read control memory CMR, random read control is possible. -Write/sequential read control will be performed.

In either case, the PC on the channel memory SPM
The address where the M-encoded nine call data is stored is one-to-one with one set of highway number and time slot number.
It is compatible with.

Since the conventional time-division channel device was configured as described above, it had the following problems. It is assumed that a failure occurs in the memory area of the communication path memory SPH, and data cannot be guaranteed for the data area at a certain address in the communication path memory SPH.

When this situation occurs, the line (-channel) configured using the address of the faulty memory area is cut off. However, in this case, the call route memo +7
If there is a normal area on the SPH where call data can be saved, this area can be used to maintain the line.

Writing and reading control memo can be saved to any address in the channel memory, so the above problem can be avoided. However, in general, the communication path device IL has advantages such as simple configuration and easy control, so as mentioned above, the control memory CMW
, CMR is used as a sequential counter.

m2 Figure U is a diagram showing the configuration of an example of a conventional time-division communication path device that is subject to sequential write/fundum read control. In the figure, the symbols are the same as in Figure 1. CNT is a control memory (chtvt) that sequentially sends omitted addresses.
CM is a read control memory that sends out read address information for random read.

Similarly to FIG. 1, the call data from the terminal PF is multiplexed into one intermediate 7-word highway FHIM and input into the call memo IJ SPH, and the call data from the terminal PF is input into the call memo IJ SPH.
The call data extracted from PM is intermediate backward
Output to highway BHWM. At this time, call data of the number m of highways and the number of time slots are multiplexed on both highways. That is, it is multiplexed by mx%.

Each forward highway FHil-F□mI accommodates time slots rsl-rs% in one frame, and the call data it carries becomes mx'n time-division multiplexed PCM numbers by the multiplexer [I MPX]. , the intermediate 7-word highway pyxtd reaches the speech path memory SPH, and uses the address information given as the output of the counter CNT (increased by 1 for each sub-time slot as described later) as an address, and writes it into the speech path memory SPH.
They are written to the PH in address order, that is, sequentially. In the read control memory CM, address information for reading the channel memory is written from the central control unit CPU corresponding to each sub-time slot, and this address is read out for each sub-time slot. The call data in the call path memo IJ SPH is read out at random based on the address information. This address corresponds to the exchange line 1 & what line.

Call path memo! The call data read from the JSPM passes through the intermediate bank word highway BIIWM, and the multiplex signal is further distributed to time slots assigned at each end, and transmitted to the terminal.

FIG. 3 shows the flow of time-division multiplex call data up to Ward Highway BW, (2). In the figure, T indicates one frame. Forward Highway FHW, ■ has n time slots in one frame, and one call data is allocated to each time slot.

7 Orward Highway FEF,~FHWws
are multiplexed as indicated by X by a multiplexer MPX. In other words, if we take the call data of forward highway FHW1■ as an example, it will be placed on the sub-time slot indicated as HWI of time slot b i1HWM■, and similarly it will be carried on the sub-time slot indicated as HWI of the forward highway FHW1■.
The data on time slot TSi of 1', .about.FHWtn is placed on sub-time slots such as HW, .about.MWj A-H1l'ts. One time slot (rsxt/
...Responds to If.

Similarly, Forward Highway FJ? '71~Fml
The data on each of the other time slots TS~TS% of 'm are similarly multiplexed. In this way, the call data of xw is multiplexed onto the intermediate forward highway pyx as shown by ■.

FIG. 4 is a diagram showing the relationship between addresses of the speech path memory SPH and data written to those addresses.

As shown in the diagram, call path memo! J SPM Unxm
address "1", and the company is located at address "1".
sub-time slot ff of time slot TS1.

Then, as shown in FIG. 4, the sub-time slots Ml, HW3,
...Writes the data carried by Gin.

As shown in FIG. 4, the address of the call data written in the call path memory SPM has a one-to-one correspondence with one combination of a highway number (1) and a time slot number (1 to 2). . Since the data arrangement of the communication path memory SPH is determined in this way, the read data can be read out according to the start-up address information of the communication path memory SPH sent from the reading control memo IJCM to a different highway number and time slot number. Restore it to the position.

The intermediate backward highway BHWH in Figure 2 includes:
As shown in FIG. 3, the contents of the communication route memo 175PM are read out at random, and for example, the data in the sub-time slot HWI of the time slot TS1 is placed in the time slot TS1 of the packed word highway EHW1.

Like this intermediate punk word highway BHIl'H
The data in the sub-time slots HW1-HWwh of each time slot TS1-75m are outputted in the corresponding time slots TS1-TSm of the packed word highways EHW, ~BH'W@, respectively.

Sub-time slot conversion is performed at the address specified by the read control memory CM, and line switching is performed.

Here, as described above, if the memory area in which the communication path memo V_SPY is stored becomes unusable, the terminal that uses that area to perform overconfidence becomes unable to communicate.

In other words, communication is impossible if the same address as used during normal operation is used.

As shown in Fig. 2, instead of controlling the sequential 2-item/-) random read using the counter CWT for writing address generation and the control memory CM for reading address generation, Even if random write/sequential read control is performed using the control memo IJCM for writing address generation and the counter CNT for reading address generation, the communication path cannot be accessed from the reading side of the communication path memory SPH. When looking at the memory area for storing call data in the memory SPH, there is a one-to-one correspondence between addresses and call data storage. Therefore,
Even if random write/sequential read control is performed, the above-mentioned problem still remains, that is, some terminals may become unable to communicate due to a failure in the memory area of the speech path memory SPH.

As shown in FIG. 1, the control memory CM11. for writing and reading the communication path memory spx. A CMB is provided, and each control memo 90MW is sent from the central control unit CPU.
, the line connection can be maintained by writing address information to the CMH avoiding the memory area that caused the failure. However, if this is done, the amount of hardware and the amount of software for controlling the two control memories will also increase, which is extremely uneconomical and undesirable.

As described above, with the conventional technology, it is impossible to maintain line connectivity in the event of a failure in a part of the memory area of the channel memory of the time-sharing channel device, and it is not possible to maintain line connectivity. However, the above-mentioned method increases the amount of hardware and software, and cannot be economically implemented in the event of a failure of some memory area of the channel memory of the indivisible channel device. , the purpose is to economically prevent line connections from becoming impossible by simple means.

Examples of the invention FIG. 5 is a connection diagram of one embodiment of the present invention.

The embodiment shown in FIG. 5 is used when there is a failure in the memory area for one address.

In the figure, FHWM and BHFl'M are the intermediate forward highway and intermediate bankward highway, respectively, and SPM is the channel memory, and the channel memory body 5PM- corresponds to the channel memo IJ SPH in FIG.
P and spare area 5 PM-5, 5EL1, S
EL* is a selector, COMP is a comparison circuit, CRT is a counter that generates a write address, CM is a control memory that generates a read address, BURO and BUR
l are the first and second buffer registers, respectively.

If the channel memory SPM is normal, no data will be stored in the buffer registers BURO and BUR1.

In the adjustment cycle, the heave cutting and adjustment switching signals R/W and S control the selector SEL to select the output of the counter CNT, and in the adjustment cycle, the read/write switching signal R/F 4 S controls the selector SEL, selects the output of the control memory CM, and sends each output as address information to the speech path memory SPM. At this time, the output of the selector SEL (the above address information) is also diverted to the comparison circuit coxp, but if the communication path memo IJ SPM is normal, the central control unit CPU sends the data to the second buffer register BURj. It is not set, its contents are empty, and the ENB pin for driving the comparator circuit COMP is ti@0', so the comparator circuit COMP does not perform a comparison operation, and its output Out
is @0'', so the selector 5EL1 selects and passes the output of the selector SEL!, and blocks the contents of the second buffer register BUR1 from passing. Note that normally it is assumed that the speech path memory SPMId is normal. , its body S
Circuit switching is performed using the address in PM-P.

Now, call route memo IJ SPM call route memory body 5P
An unusable memory area occurs within the H-P area,
When the central control unit CPU recognizes the address of this faulty memory area, it first stores the faulty channel memory main body 5pht in the first buffer register BURO.
- write the address information of the memory area in p, secondly the central control unit @ CPU writes in the second buffer register BUR1 the address to which the data to be accommodated in the faulty area is to be evacuated; The comparison circuit COMP driving bit ENB set in the second buffer register BUR1 is set to 11#. The evacuation address is stored in the spare area SPM of the channel memory SPH.
Set within -5.

Once the above settings are completed, write and read address information is transferred from the counter CNT and control memory CM to the selector S in each write and read cycle.
When the address information is input to the selector EEL@ through EL, the address information is also input to the comparator circuit coitp and compared with the address information of the faulty area stored in the buffer register BURO. If there is no match, selector SEL
Since the area corresponding to the address information output from , is normal, and the coincidence output Out of the comparison circuit COMP is 101, the selector 5ELI selects the normal address information output from the selector SEL and stores it in the communication path memory. S
PH to block the save address in buffer register BUR1.

If the address output from the selector SEL and the address of the faulty area in the buffer register BURO match, the comparison circuit COMP outputs a match output (11" as hbt). The selector 5ELI is controlled by @11 of this match output Out. is selected, the contents of buffer register BUR1, ie, the save address, are selected and stored in the communication path memory S.
PH to block the address of the faulty area from being output from the selector SEL*.

Therefore, call data that was written to an address in the faulty memory area and was supposed to be read from that address is stored in the buffer register EUR.
1 is newly set to a normal address in the reserve area 5PM-5, which is different from the above address, and the call data is written.

Readout is based on the call path memo IJ for that address.
This is successfully carried out in the SPH reserve area 5PM-5, and the line can be maintained.

Here, the counter CWT and the control memory CM may have exactly the same configuration as those according to the prior art shown in FIG. If set to 01, the comparison circuit COMP is not driven and operates in exactly the same way as shown in FIG.

When a fault occurs in the memory area of the communication path memory SPH, by setting predetermined data in the buffer memories BURO and BURl, the communication path memory SPH
Reserve area SPM-! ; can be used to maintain the line; in this case, there is no need to change the contents of the control memory CM, and there is no need to change the setting 1vL of the counter CNT.

FIG. 6 is a connection configuration diagram of a different embodiment of the present invention. In the embodiment shown in FIG.
The address data stored in RO and EUR'I is for one address in the communication path memory SPM, and only one address in the communication path memory SPH can be changed, and if a failure occurs in only one address, the line It is possible to maintain However, the present invention not only makes it possible to change only one address, but also allows address translation to be performed in units of multiple blocks of addresses in the speech path memory SPH. FIG. 6 shows an embodiment in which address translation is performed in units of blocks containing a plurality of such addresses.

In FIG. 6, the symbols indicate the same things as in FIG.

In FIG. 6, the address for writing in the communication path memory SPH and digging out is output from the selector SEL in the same way as in FIG. t bits on the side and m bits on the upper side are selector SEL.
, and input to the comparison circuit COMF.

In this case, for example, the address group @000i000'~@00
0i111", the upper 3
Set bit @000'' in the first buffer register BURO as faulty block information.
The register BUR1 contains the upper 3 bits of the address in the spare area SPM-5 of the channel memory SPH, for example @1.
Set 11' and set the comparator circuit drive pit) ENB pit to @1".

Now, when the contents are not set in the buffer register EURO (comparison circuit drive pin) ENB is "0#", the comparison circuit COMP is inactive, and the upper bit of the address information output from the selector EEL! does not match the setting contents of the first buffer register BURO, the match output Out of the comparison circuit COMP is 10#.
The selector SEL selects and passes the output from the selector SEL, that is, the upper 11411fn bits of the address.

At the output section, the upper side information bits and the lower side t bits, which are not changed at all, are combined and sent to the channel memory 5pit as address information. As can be easily understood from the above explanation, in this case, the address information output from the selector SEL reaches the speech path memory SPH without being changed in any way.

When the upper bit of the address information output from the selector SEL matches the content set in the first buffer register BURQ as information indicating a faulty area, the match output Out of the comparison circuit coip becomes "1". "The selector 5ELI selects and outputs the information (saved address information) set as the address information to be changed in the buffer register BUR1, and the selector SEL,
Ensuring the passage of information from. At the output section of the selector 5ELI, the upper bit of the address information output from the selector 5ELI is changed to the setting contents of the buffer register EUR1, and reaches the speech path memory SPH as saved address information.

For example, as shown above, the address group "ooo :ooo
If a fault occurs in the area '~'00011', '00o#' is written to the first buffer register EURO and '111#' is written to the second buffer register BUR1.
Therefore, the address information "ooooooo ~ 000111" that outputs the selector SEL is @111000
~111111' and input into the speech path memory SPH. Here, enter the above address in the spare area SPM-5.
By providing the communication path memory SPH in the
Blocks within the area (°ooooooo in the above example)
''~@000111'), and the data storage can be converted to a block (in the above example, ``111000~111111#'') in the spare area 5PH-5 of the speech path memory SPH. Therefore, even if a failure occurs in a block consisting of a plurality of addresses, the line can be maintained.

The present invention is not limited to the above embodiments, and various modifications can be made within the technical scope thereof.

Effects of the Invention Since the present invention is configured as described above, the present invention provides a time-division communication path for circuit switching, which is provided with a communication path memory and a communication path control memory that provides write and read addresses to the communication path memory. In the equipment, when a fault occurs in the memory area of the channel memory, a spare area is provided in the channel memory, and a buffer register is provided to store the address for the faulty area of the channel memory in the above-mentioned area of the channel memory. By converting the area into a spare area and storing the data (call data) that should be accommodated in the faulty area in the spare area of the communication route memory, the line can be maintained with simple addition of hardware and simple control processing. This has the effect of making it possible to do so. In addition, at this time, there is no need to make any changes to the contents of the control memory that stores the address information of the communication path memory, and the address of the fault area and the address that newly stores the data are changed to the first and second addresses, respectively. 2111! Control is simple because it only needs to be set in the buffer register of il, and the load on the central control wAJ device is extremely small.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of an example of a conventional communication path device in a time-division switching system configured with one stage of communication path memory, and Fig. 2 shows a communication path under sequential write/random read control. One of the conventional channel devices with memory
A diagram showing an example configuration, FIG. 3 is a diagram showing the flow of call data on each highway of the above-mentioned communication path device, and FIG.
FIG. 5 is a diagram showing the relationship between the address arrangement of the communication path memory in FIG. 2 and the communication data to be stored in the address;
The figure is a connection configuration diagram of an embodiment of the present invention when changing one address, and FIG. 6 is the connection configuration diagram of an embodiment of the present invention when changing addresses for a block consisting of a plurality of addresses. It is a diagram.

Claims (1)

[Claims] a channel memory that stores time-division multiplexed data;
a control memory for transmitting address information for writing and line adjustment to the communication path memory to perform line switching; and a first buffer register for storing information indicating an address or a group of addresses of a faulty area of the communication path memory. , a second buffer register for storing information indicative of addresses or L address groups in a spare area of the channel memory; and address information sent from the control memory to the channel memory and stored in the first buffer register. compared to the information obtained,
a comparison circuit that sends a match output when a match occurs; and a comparison circuit that converts address information or information indicating a group of addresses sent from the control memory based on the match output of the comparison circuit into the content set in the second buffer register. An address conversion method for a communication path memory in a time-division switching system, characterized in that the address conversion method for a communication path memory in a time division switching system is provided, comprising a selector for transmitting the history to the communication path memory.