JPS58151299A - Collating card - Google Patents

Collating card

Info

Publication number
JPS58151299A
JPS58151299A JP57033950A JP3395082A JPS58151299A JP S58151299 A JPS58151299 A JP S58151299A JP 57033950 A JP57033950 A JP 57033950A JP 3395082 A JP3395082 A JP 3395082A JP S58151299 A JPS58151299 A JP S58151299A
Authority
JP
Japan
Prior art keywords
card
verification
case
verification card
common conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57033950A
Other languages
Japanese (ja)
Inventor
相合 征一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP57033950A priority Critical patent/JPS58151299A/en
Priority to FR8300531A priority patent/FR2522851B1/en
Publication of JPS58151299A publication Critical patent/JPS58151299A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12035Zener diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は外部から入力される暗号コードによって個人ま
たは団体を識別し且つ入力信号を記憶しまたは入力信号
をカード内部の半導体装置で処理して記憶し、または入
力信号に応じた出力信号を発信する等の役割を果す照合
カードの改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention identifies an individual or a group by a cryptographic code input from the outside, and stores the input signal, or processes and stores the input signal in a semiconductor device inside the card, or converts the input signal into the input signal. The present invention relates to an improvement of a verification card that plays a role such as transmitting a corresponding output signal.

この種の照合カードにはマイクロプロセッサや不揮発性
メモリ等が含まれ、その半導体チップとしては多くの場
合、VOS型構造のチップが用いられるが、該チップは
静電気により容易に破壊され、従って照合カードを衣類
に対し摩擦する等の動作によって内部の半導体装置が破
壊される欠点があった。
This type of verification card includes a microprocessor, non-volatile memory, etc., and the semiconductor chip used is often a chip with a VOS structure, but this chip is easily destroyed by static electricity, so the verification card There was a drawback that the internal semiconductor device could be destroyed by operations such as rubbing it against clothing.

本発明の目的は静電気破壊を防止し得る構造の照合カー
ドを提供することである。
An object of the present invention is to provide a verification card having a structure that can prevent damage caused by static electricity.

上記目的を達成するため本発明による照合カードの特徴
は、半導体チップの所定の電極端子からの引出線をカー
ドの非動作時には共通接続1.た状態に保つことである
In order to achieve the above object, the verification card according to the present invention has the following features: 1. Common connection of lead wires from predetermined electrode terminals of the semiconductor chip when the card is not in operation; It is important to keep it in a good condition.

次に図面を参照のもとに本発明の詳細な説明する。第1
図ないし第3図は本発明が関連する照合カードの一例を
示し、照合カード(11はプラスチック等からなる基板
001と、その適宜位置に形成された窓(lυに収めら
れたケース(13ト、ケース内の−または複数の半導体
チップ(8)等からなり、両面はカバーフィルム0国、
α4で被われている。ケース03内VCは通常、マイク
ロプロセッサおよびメモリとして用いられる二つの半導
体チップが含まれ、該チップの所定の電極端子α鴎から
の各引出線α6)は絶縁材料(16b)によりケースα
りに取付けられ、その接点部分(15a)で信号入出カ
ニニットの端子(17)の接触を受けて交信する。図示
の例では端子0ηの接触を受ける引出線(161は8つ
であるが、その数は場合により異なることがあるのは言
うまでもない。また、それらの引出線はチップ(S)の
両側に延びていてもよいが、第4図に見られるようにチ
ップ(S)の片側に延びていてもよい。
Next, the present invention will be described in detail with reference to the drawings. 1st
The figures to FIG. 3 show an example of a verification card to which the present invention relates, in which a verification card (11 is a substrate 001 made of plastic or the like, and a case (13, Consists of - or multiple semiconductor chips (8) etc. in the case, with cover film on both sides,
Covered by α4. The VC in the case 03 usually includes two semiconductor chips used as a microprocessor and a memory, and each lead wire α6) from a predetermined electrode terminal α of the chip is connected to the case α by an insulating material (16b).
The contact part (15a) receives contact with the terminal (17) of the signal input/output crab knit and communicates. In the illustrated example, there are eight lead lines (161) that come into contact with the terminal 0η, but it goes without saying that the number may vary depending on the case. Also, these lead lines extend on both sides of the chip (S). It may extend to one side of the chip (S) as seen in FIG.

この照合カード(11の特徴は非動作時にdそれらの引
出線aet−共通接続した状態に保つことであり、その
ため引出線ne q第5図に見られるように中継継部材
α印は以下に述べるように、照合カードが嶌子(17)
の接触を受けて動作する際は導通しないが、動作しない
時には導通する工うになりている。共通の導体としては
ケース0がメタルケースであれば、ケース(121であ
ってもよい。中継部材a印は導体の板ばねQ8であって
もよく、その一端はケース等の導体に固定され、自由な
他端には磁石Qlが設けられて引出線αeに接触してお
り、動作時Kd端子aηと共に接近する棒状の磁石■の
斥力で想像線で示すように離れ、単独回路にされる。板
ばね罎が磁性体材料で作られていれば、第6図に見られ
るように磁石αIt−設ける必要がなく、その場合は磁
石(21)で吸引されて離される。なお、板ばねの代り
にコイルばねを用いてもよい。
The feature of this collation card (11) is to maintain the common connection between the lead wires aet and d during non-operation, and therefore, as seen in Figure 5, the relay joint member α mark is as described below. So, the matching card is Shimako (17)
It is designed so that it does not conduct when it operates due to contact with the terminal, but conducts when it does not operate. If the case 0 is a metal case, the common conductor may be the case (121).The relay member marked a may be a conductor leaf spring Q8, one end of which is fixed to a conductor such as a case, A magnet Ql is provided at the other free end and is in contact with the lead wire αe.During operation, the magnet Ql is separated as shown by the imaginary line by the repulsive force of the rod-shaped magnet 2, which approaches the Kd terminal aη and becomes an independent circuit. If the leaf spring is made of a magnetic material, there is no need to provide the magnet αIt- as shown in FIG. A coil spring may also be used.

また共通の導体は薄板状の金属片C22)であってもよ
−く、金属片(22) k′i槙7図に示すように適当
な支持体C23)の上に設置されるのが好ましい。この
ような支持体としては樹脂製のケースであるのが好まし
い。第8図に示すように、金属片(22) ′に支持体
上に設置1−で単一の組立体として構成すれば、それを
第4図に示すようなケースa2の所定の区域(12’)
Kはめ込むことによって簡単に組付けること成すること
ができ、それにより創造が容易になる。
Further, the common conductor may be a thin metal piece C22), and it is preferable that the metal piece (22) is installed on a suitable support C23) as shown in Figure 7. . Preferably, such a support is a case made of resin. If constructed as a single assembly by mounting the metal piece (22)' on a support 1- as shown in FIG. ')
Easy assembly can be accomplished by K-fitting, which facilitates creation.

中継部材(国としては上記のようにばねに限るものでは
なく、例えば第9図に示すように、引出線tt61と共
通の導体【22)との間に接続された抵抗(18a)で
めりてもよい。この場合[Fi低抵抗して動作時に問題
のない程度の抵抗値のものが用いられる。
Relay members (not limited to springs as mentioned above, for example, as shown in Fig. 9, relay members (18a) connected between leader wire tt61 and common conductor [22)] It's okay. In this case, [Fi] is used that has a low resistance and has a resistance value that causes no problems during operation.

さらに第10図に示すように、半導体スイッチ(18b
)で中継部材aB1−構成してもよく、この場合、信号
入出力端子0ηからの電圧が印加されると抵抗が大きく
なり、電圧の負荷がないときは抵抗が小さくなって共通
接続された状態になる。また場合により、中継部材Gi
n抵抗とツェナーダイオードのような非直線性の半導体
素子で構成して設定電圧を越えると急激に電流が流れる
ようにし、且つ信号人出カニニットの端子電圧より前記
設定電圧全高くなるようにすればよい。上記半導体スイ
・ノチまたは半導体素子は複合素子と[、て構成しても
よい。
Further, as shown in FIG. 10, a semiconductor switch (18b
) may be configured as a relay member aB1-; in this case, the resistance increases when voltage from the signal input/output terminal 0η is applied, and when there is no voltage load, the resistance decreases, resulting in a commonly connected state. become. In some cases, relay member Gi
If it is constructed with an n-resistance and a non-linear semiconductor element such as a Zener diode, so that the current flows rapidly when the set voltage is exceeded, and the set voltage is made to be higher than the terminal voltage of the signal generator. good. The semiconductor device or semiconductor element described above may be configured with a composite element.

なお、第3図におけるGNDの引出線は接地用のもので
あるためケースa3または金属片(22)に常に接続さ
れており、従ってその位置には中継部材0口1ける必要
はない。
Note that the GND lead wire in FIG. 3 is for grounding and is always connected to the case a3 or the metal piece (22), so there is no need to connect a relay member at that position.

上記のように、本発明によれば、信号入出力端子との接
触を受ける所定の引出線は動作時Vc/fi中継部材に
おいて導通がしゃ断されるので、それぞれ単独回路にな
り、信号入出カニエツトと所定の交信を行なうことがで
きるが、動作しない際は上記各引出線は中継部材を介し
て共通接続されているので静電気破壊を適切に防ぐこと
ができる。
As described above, according to the present invention, the conduction of the predetermined lead wires that come into contact with the signal input/output terminals is interrupted at the Vc/fi relay member during operation, so that each becomes an independent circuit and connects to the signal input/output terminal. Although predetermined communication can be carried out, when the device is not in operation, the respective lead wires are commonly connected via a relay member, so that damage caused by static electricity can be appropriately prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は照合カードの平面図、第2図はその一面図、第
3図は本発明の一例による照合カードの要″部の平面図
、第4図は他の実施例の要部の平面図、第5図は第3図
の線A −A断面図、第6図d別の要部の部分的な断面
図、第7図はさらに他の実施例の要部を示す部分的な断
面図、第8図は第7図に示された部材の斜視図、第9図
および第10図はそれぞれ別の実施例を示す第6図に類
似の断面図である。
FIG. 1 is a plan view of the verification card, FIG. 2 is a front view thereof, FIG. 3 is a plan view of the main part of the verification card according to one example of the present invention, and FIG. 4 is a plan view of the main part of another embodiment. Figure 5 is a sectional view taken along the line A-A in Figure 3, Figure 6d is a partial sectional view of another main part, and Figure 7 is a partial sectional view showing the main part of another embodiment. 8 is a perspective view of the member shown in FIG. 7, and FIGS. 9 and 10 are sectional views similar to FIG. 6 showing different embodiments.

Claims (1)

【特許請求の範囲】 (l)、半導体チップの所定の電極端子からの各引出線
り信号入出力端子の接触を受けて交信中るようになって
いる照合カードにおいて、前記引出線は前記カードの動
作時には導通しないで動作しない際は導通する中継部材
を介【7て共通の導体に接続されていることを特徴とす
る照合カード。 (2、特許請求の範囲第1項に記載の照合カードにおい
て、前記共通の導体は前記半導体チップを納めたメタル
ケースである照合カード。 (3)1%許請求の範囲第1項に記載の照合カードにお
いて、前記共通の導体は薄板状の金属片からなる照合カ
ード。 (4)、特許請求の範囲第3項に記載の照合カードにお
いて、前記金属片は支持体上に設置されている照合カー
ド。
[Scope of Claims] (l) In a collation card that communicates by receiving contact of each leader line signal input/output terminal from a predetermined electrode terminal of a semiconductor chip, the leader line is connected to the card. A verification card characterized in that it is connected to a common conductor through a relay member that is not conductive when it is in operation and conductive when it is not in operation. (2. The verification card according to claim 1, wherein the common conductor is a metal case containing the semiconductor chip. (3) 1% allowance according to claim 1. In the verification card, the common conductor is a thin metal piece. (4) In the verification card according to claim 3, the metal piece is installed on a support. card.
JP57033950A 1982-03-05 1982-03-05 Collating card Pending JPS58151299A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57033950A JPS58151299A (en) 1982-03-05 1982-03-05 Collating card
FR8300531A FR2522851B1 (en) 1982-03-05 1983-01-14 INFORMATION CARD PROTECTED AGAINST ELECTROSTATIC BREAKDOWN

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57033950A JPS58151299A (en) 1982-03-05 1982-03-05 Collating card

Publications (1)

Publication Number Publication Date
JPS58151299A true JPS58151299A (en) 1983-09-08

Family

ID=12400776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57033950A Pending JPS58151299A (en) 1982-03-05 1982-03-05 Collating card

Country Status (2)

Country Link
JP (1) JPS58151299A (en)
FR (1) FR2522851B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63125396A (en) * 1986-11-14 1988-05-28 日本電気株式会社 Ic card

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604274B1 (en) * 1986-09-22 1991-01-11 Flonic Sa MULTI-FUNCTION ELECTRONIC MEMORY CARD AND DEVICES FOR PROCESSING SAID CARDS
FR2627880B1 (en) * 1988-02-26 1992-01-17 Sgs Thomson Microelectronics CHIP CARDS WITH DIFFERENT SENSE OF INSERTION

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2480008A1 (en) * 1980-04-04 1981-10-09 Flonic Sa IMPROVEMENTS TO MEMORY CARDS
DE3130324A1 (en) * 1981-07-31 1983-02-17 GAO Gesellschaft für Automation und Organisation mbH, 8000 München CARRIER ELEMENT FOR AN IC COMPONENT
US4409471A (en) * 1981-12-17 1983-10-11 Seiichiro Aigo Information card
US4447716A (en) * 1982-03-01 1984-05-08 Seiichiro Aigo Information card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63125396A (en) * 1986-11-14 1988-05-28 日本電気株式会社 Ic card

Also Published As

Publication number Publication date
FR2522851A1 (en) 1983-09-09
FR2522851B1 (en) 1988-10-28

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