JPS5815061B2 - Intermediary device between mass spectrometer and computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic control device for a mass spectrometer, and more particularly to an automatic control device suitable for performing mass fragmentography analysis.

Conventionally, when mass fragmentography analysis was performed automatically using a computer, all analysis conditions were directly controlled and measured moment by moment, which placed an excessive load on the computer's software and made it difficult to perform other tasks. There was a problem in that the analysis had to be conducted with restrictions.

The present invention was made for the purpose of providing one intermediary device between an analysis device and a computer, on the one hand to realize automation of analysis, and on the other hand, to reduce the burden on the computer and increase the efficiency of computer use. .

The intermediary device in the present invention has a storage function and a control function, and when the computer is given measurement conditions such as the number of measurement channels, mass number, sampling rate, etc., the computer provides information necessary for measurement control, such as mass number. The intermediary device receives the above information from the computer, stores it, and controls the mass spectrometer. , the computer collects measurement data.

Therefore, the computer is freed from the task of operating the mass spectrometer, and is freed up to perform other tasks.

The present invention will be explained below with reference to Examples.

FIG. 1 shows an embodiment of the present invention.

N is a mass dispersion magnet, ■ is an ion source, and D is an ion detector.

In this embodiment, mass number scanning is performed by changing the ion accelerating voltage in order to switch the mass number at high speed, and 2 is a high voltage power supply for ion acceleration.

The output of the detector is amplified by a preamplifier A and then stored in a sample and hold circuit H.

In mass number scanning, the ion accelerating voltage is not changed continuously, but it is sequentially and dramatically switched so that ions of several preset mass numbers are detected, and in synchronization with this switching, the sample and hold circuit H is By operating an input switch, for example, the detection output of an ion with a given mass number is stored in H1, and the detection output of an ion with another mass number is stored in H2.

The stored information of the sample and hold circuit H is stored in the changeover switch row S.
and the A-D converter AD
The information is input to a computer (hereinafter referred to as CPU) via the CPU.

The amplifiers marked with X1 times, X10 times, and X100 times are range switching amplifiers.

The information path from the detection of ions of one mass number to the acquisition of measurement data into the CPU is called a channel, and the illustrated embodiment has eight channels.

Specific devices include those that are common to each channel, and those that correspond to each channel, such as the hold circuits H1, H2, etc. in the sample and hold circuit H, their input switches, or the output side switch row S.

The area surrounded by the chain line in the figure is an intermediary device according to the present invention, and 1 to 5 are memories, respectively, into which data is sent and written from the CPU.

The memory 1 governs the overall control of the mass spectrometer, and stores information for channel numbers, application/removal of ion accelerating voltage, and background subtraction control.

The memory 2 stores the ion acceleration voltage of each channel.

The memory 3 stores the background of each channel.

The memory 4 stores the number of channels stored in the memory 1.

. In other words, there are a total of 8 channels, but if you want to use only 2 channels, memory 1 stores the channel numbers 1 and 2, and since there are 2 channels to measure, memory 4 stores the number 2. I am forced to do it.

The memory 5 stores the sample hold time, that is, the sampling rate.

Although the apparatus shown in the figure has eight channels, assuming analysis of various substances, there are many types of fragment ions to be detected, and the signal representing the ion acceleration voltage for detecting each ion has a large number of bits.

The signal representing the background value also has a considerably large number of bits.

Therefore, all of these data cannot be stored in the memory 1 in advance.

What is stored in memory 1 is only the data related to the ions to be detected in one analytical operation, including information on which channel to use to detect that ion and the ion acceleration voltage for detecting that ion. When the address of the memory 1 is specified and the data at that address is read out, the channel designation code portion of the data is applied to the input channel selection circuit (decoder) 13. Then, in hold circuit H, the input switch of that channel is turned on.

Also, the ion acceleration voltage code part of the read data is applied to the memory 2 as an address designation signal.
The data at that address is read out from the address, and is sent to the accelerating high voltage power supply circuit (2) to actually generate a predetermined high voltage.

Also, the background code portion of the data read from the memory 1 is applied to the memory 3 as an address designation signal, and the background data read from that address in the memory 3 is processed by the DA converter 10. The analog signal is applied to the preamplifier A as a subtraction signal, and the background component is subtracted from the detection output of the ion detector.

Address counter 6 specifies the address of memory 1.
The counter 6 is incremented by several 1 when the sample hold time designated for one channel has elapsed.

Ions having the mass number thus obtained are detected for a predetermined period of time, and the detection signal is integrated in a designated channel of the hold circuit H.

The sample hold time is realized as follows.

14 is a clock counter that counts clock pulses input through AND gate 15 (assumed to be already open), and its counting output is exclusive OR (E
16 (hereinafter referred to as XOR).

A sample hold time code from the memory 5 is also input to the EXOR 16.

The EXOR 16 (only one is shown in the figure) has the same number of bits as the counter 14, and this number of bits is equal to the number of bits in the memory 5, and one EXOR gate has the outputs of the corresponding bits of the counter 14 and memory 5. is applied,
When the count of the counter 14 and the output of the memory 5 match, the output of the EXOR 16 becomes O.

Since the output of EXORI6 becomes 0 only during one cycle of the clock pulse, this 0 output is one pulse, and the address counter is incremented by this pulse.

At the same time, the counter 14 is also cleared by this pulse.

Reference numeral 17 denotes an EXOR gate having the same structure as EXOR 16, to which the count output of address counter 6 and the storage output of memory 4 are applied, and when the two match, the address counter 6 is cleared by a pulse output from EXOR 17.

When only three channels are used in the analysis, channels 1 to 3 are used, so the data stored in the memory 4 is "3", and the address counter 6 counts 3.
When this happens, a signal is output from EXOR 17 to clear address counter 6.

Therefore, the address counter 6 returns to O, specifies address 0 in the memory 1, and restarts measurement for the channel number 1.

The apparatus of the present invention is used when mass fragmentography is performed on the outflow gas of a chromatograph.

In FIG. 2, curve C indicates the output peak of the gas chromatograph detector.

The rising edge tl of this peak is detected by a peak detector, and this detection signal is applied as a set input to the flip-flop 18 in FIG.

Ant gate 15 is opened by the set output of flip-flop 18, and a clock pulse is input to clock counter 14, and the apparatus shown in FIG. 1 starts detecting ions of the specified mass number in the first channel. The output is integrated in the first channel H1 within the sample and hold circuit H.

When the sample hold time elapses, address counter 6
advances, and detection of the designated ions in the second channel starts from the time point t2 in FIG.
The operation of playing the fourth channel and returning to the first channel again for a specified number of channels is repeated many times for one peak.

When the end te of the peak is detected, the detection signal resets the flip-flop 18 and the device of FIG. 1 stops operating until the next peak is detected.

During this time, if the next peak is to be analyzed with a different ion or sample hold time than the previous peak, new data is input from the CPU to memories 1, 4, and 5.

The data sampled and held in the sample and hold circuit H is transferred to the CPU by operating the switch row S with a signal from the CPU.
It is read into U (not shown).

This reading is performed such that the first channel is measuring the second channel while the second channel is measuring the third channel, and when the reading is completed, the sample and hold circuit of that channel is cleared. .

Since it takes some time for the ion accelerating voltage to stabilize to a new voltage after being switched, the circuit 11 detects that the channel has been switched by a change in the output of the memory 1, and uses that detection signal to trigger the delay circuit ( one-shot circuit)
19 is activated so that the ion accelerating voltage is not applied to the ion source (2) until the output of the channel switching wave accelerating high voltage power supply becomes stable.

The device of the present invention has the above-mentioned configuration, and most of the control of the mass spectrometer is performed by the intermediary device enclosed by the chain line in Figure 1, and the computer writes necessary information into the memory of the intermediary device and collects measurement data. Since you only have to do certain tasks, the burden on your computer is reduced and your free time increases, allowing you to complete other tasks with more free time, thereby improving the efficiency of using your computer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a graph showing the relationship between the output peak of a chromatographic detector and the timing of mass fragmentography. H... Sample hold circuit, ■...
Ion source, M... Mass dispersion magnet, D.
...Ion detector.

Claims (1)

[Claims] 1. A multi-channel sample hold circuit that holds the ion detection signal, the channels of this sample hold circuit, the ion acceleration voltage and sample hold time specified in that channel, and measurement operations such as background for subtraction from the ion detection signal. A memory into which information is input from a computer and stored, an address counter that specifies the address of the memory, and a sample hold time read from the memory is measured by pulse counting, and the count of the address counter is calculated based on the elapsed time. An intermediary device between a mass spectrometer and a computer, comprising a counting device and a device generating a voltage according to ion accelerating voltage information read from the memory.