JPS58149041U - CMOS integrated circuit - Google Patents

CMOS integrated circuit

Info

Publication number
JPS58149041U
JPS58149041U JP1651983U JP1651983U JPS58149041U JP S58149041 U JPS58149041 U JP S58149041U JP 1651983 U JP1651983 U JP 1651983U JP 1651983 U JP1651983 U JP 1651983U JP S58149041 U JPS58149041 U JP S58149041U
Authority
JP
Japan
Prior art keywords
integrated circuit
cmos integrated
cmo5
rectifying
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1651983U
Other languages
Japanese (ja)
Inventor
勝幸 池田
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP1651983U priority Critical patent/JPS58149041U/en
Publication of JPS58149041U publication Critical patent/JPS58149041U/en
Pending legal-status Critical Current

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  • Rectifiers (AREA)
  • Transmitters (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の電気装置の構成、を示す図である。第
2図は本考案による一実施例を示す図であり、第3図は
本考案の他の実施例を示す図である。 4・・・・・・電源回路、5・・・・・・波形整形回路
、6.8・・・・・・ダイオード、7・・・・・・コン
デンサ。
FIG. 1 is a diagram showing the configuration of a conventional electrical device. FIG. 2 is a diagram showing one embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. 4... Power supply circuit, 5... Waveform shaping circuit, 6.8... Diode, 7... Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の入力信号端子を有するCMO3集積回路において
該入力信号端子のいずれかの信号をも整流平滑する手段
を有し、該整流平滑手段からの出力を該CMO5集積回
路の電源として用いることを特徴とするCMO5集積回
路。
A CMO3 integrated circuit having a plurality of input signal terminals has means for rectifying and smoothing any signal of the input signal terminals, and the output from the rectifying and smoothing means is used as a power source for the CMO5 integrated circuit. CMO5 integrated circuit.
JP1651983U 1983-02-07 1983-02-07 CMOS integrated circuit Pending JPS58149041U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1651983U JPS58149041U (en) 1983-02-07 1983-02-07 CMOS integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1651983U JPS58149041U (en) 1983-02-07 1983-02-07 CMOS integrated circuit

Publications (1)

Publication Number Publication Date
JPS58149041U true JPS58149041U (en) 1983-10-06

Family

ID=30028881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1651983U Pending JPS58149041U (en) 1983-02-07 1983-02-07 CMOS integrated circuit

Country Status (1)

Country Link
JP (1) JPS58149041U (en)

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