JPS58148969A - Measuring device of alternating-current signal level - Google Patents

Measuring device of alternating-current signal level

Info

Publication number
JPS58148969A
JPS58148969A JP3274382A JP3274382A JPS58148969A JP S58148969 A JPS58148969 A JP S58148969A JP 3274382 A JP3274382 A JP 3274382A JP 3274382 A JP3274382 A JP 3274382A JP S58148969 A JPS58148969 A JP S58148969A
Authority
JP
Japan
Prior art keywords
output
signal
switch
outputs
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3274382A
Other languages
Japanese (ja)
Inventor
Kazuyuki Tsurunaga
鶴永 和行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3274382A priority Critical patent/JPS58148969A/en
Publication of JPS58148969A publication Critical patent/JPS58148969A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/22Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of ac into dc

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To measure levels of AC signals of low frequency and with frequency variation, by sampling and holding the AC signals only when they have specified potential differences between their rectification outputs and phase shift signals and specified rectification outputs. CONSTITUTION:When an AC signal E1 is applied from an AC signal source 11, a rectifying circuit 12 and a phase shifting circuit 15 generates the rectification output Ei1 and phase shift output Ei2 respectively. When the output Ei1 exceeds a prescribed value, a switch 14 is turned on through a checking circuit 13 and when the difference between the outputs Ei1 and Ei2 is within a prescribed range and below a prescribed value, a switch 17 is turned on through a sample timing signal generating circuit 16. Only when both those switches 14 and 17 are turned on, the charging and discharging of a memory capacitor 19 is so controlled that a charging voltage is equal to the sum output of the outputs Ei1 and Ei2 obtained by an adder 18, thus performing sampling and holding corresponding to variation of the signal Ei. Consequently, levels of even AC signals of low frequency and with frequency variation are measured.

Description

【発明の詳細な説明】 本発明は電動機2次回路婢の1M波数変化を伴う交流信
号の電圧あるいは電流の大きさを測定する交流イぎ号レ
ベル測定装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC signal level measuring device for measuring the voltage or current magnitude of an AC signal with a 1M wave number change in a motor secondary circuit.

〔発明の技術的背鍍〕[Technical background of the invention]

一般に交流電圧あるいは交流電流の大きさを測定する場
合には平滑回路等のフィルターによって、これらの被測
定蓋を直流電圧に変換して測定する方法が用いられる。
Generally, when measuring the magnitude of alternating voltage or alternating current, a method is used in which the voltage to be measured is converted into direct current voltage using a filter such as a smoothing circuit.

第1図はこのような測定方法の一例を示すプロツク図で
、図中1は交流信号源、2は入力信号を整流する整流器
、3は整流出力を平滑するチョークコイル、4は平滑用
コンデンサ、5は負荷抵抗である。このようにすれば負
荷抵抗50両端には入力信号1の電圧hiに比例した直
流電圧Eoを得られるので、この電圧EOから交流電圧
giを知ることができる。
Figure 1 is a block diagram showing an example of such a measurement method, in which 1 is an AC signal source, 2 is a rectifier that rectifies the input signal, 3 is a choke coil that smoothes the rectified output, 4 is a smoothing capacitor, 5 is a load resistance. In this way, a DC voltage Eo proportional to the voltage hi of the input signal 1 can be obtained across the load resistor 50, so that the AC voltage gi can be determined from this voltage EO.

[゛背景技術の問題点〕 しかしながらこのようなものでは、入力信号の周波数が
低下するにつれて、出力電圧のリツノル含有率が大きく
なり、正確な電圧検出が不oJ能となる。また平滑用の
チョークコイル3、コンデンサ5等を設けているために
急激な入力電圧の変化に対する応答が遅くなる問題があ
った。
[Problems with Background Art] However, in this type of device, as the frequency of the input signal decreases, the rhiznor content of the output voltage increases, making accurate voltage detection impossible. Furthermore, since the smoothing choke coil 3, capacitor 5, etc. are provided, there is a problem in that the response to sudden changes in input voltage becomes slow.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので従来の方法
でti検出困難であった低周波数、たとえは数Hzの交
流16号あるいは周波数変化を伴う交流信号に対しても
容易にそのレベルを検出することが口1舵な交流信号レ
ベル測定装置を提供することを目的とするものである。
The present invention has been made in view of the above circumstances, and it is possible to easily detect the level of low frequency, for example AC 16 of several Hz, or AC signals with frequency changes, which was difficult to detect using conventional methods. It is an object of the present invention to provide an AC signal level measuring device that is easy to detect.

〔発明の概要〕[Summary of the invention]

本発明は被側定信号の整流出力を基準とし、これを任意
に移相した信号に対する電位差が所定範囲内にあり、か
つ上記整流出力がノ訂定の設定値よりも大なる時だけト
紀整流出力および上記移相した信号をす/ゾルホールド
することを特徴とするものである。
The present invention uses the rectified output of a fixed signal as a reference, and only when the potential difference with respect to a signal arbitrarily phase-shifted from this is within a predetermined range and the rectified output is larger than a set value of correction, the rectified output can be adjusted. It is characterized by holding the rectified output and the phase-shifted signal.

〔発明の実施例〕 以〒一本発明の一実施例を第2図に丁すブロック図を#
照して詳細に説明する。第2図において11は側足すべ
き被検出1g号を出力する交流(i!1号源、12は入
力信号を半波整流する整流回路、ISは整流出力レベル
glJが設定値Emlを越えるとfKlのスィッチ14
ヘオン信号を与える検出僅号チェック回路、1番は整流
出力に任意O位相遅れa(与える移相回路である。そし
て16は3個の比較層m’as 6A、J611.Jg
Cからなり上記II流回路11(D出力Ellと移相−
路15の移相出力EiJとの電位差が肩定の値以下のと
きにのみ第2のスィッチ11ヘオン信号を与えるナン!
ルタイミング信号発生−路である。なお、第1のスイッ
チ14へはダイオードからなる加X器11を介して整流
出力および移相出力が与えられこの第1のスイッチ14
0出力を第2のスイッチ1rを介してメモリコンダン?
19へ与えて光電する。そしてこのメモリコ/7′″ン
?19の充電電圧は^入カインピー〆ンスのバッファ1
0を介して出力端子11から出力される。遣え加算器1
1の出力には放電抵抗22を介挿し、加算器180出力
電圧に比してメモリコンダンt19の充電電圧がlll
1い場合は、その差分を放電抵抗22を介して放電す\
、るようにしている。
[Embodiment of the Invention] Hereinafter, a block diagram of an embodiment of the present invention shown in FIG.
This will be explained in detail. In Fig. 2, 11 is an AC (i!1 source) that outputs the detected 1g signal to be added, 12 is a rectifier circuit that half-wave rectifies the input signal, and IS is fKl when the rectified output level glJ exceeds the set value Eml. switch 14
No. 1 is a phase shift circuit that gives an arbitrary O phase delay a (a) to the rectified output. And No. 16 is a phase shift circuit that gives an arbitrary O phase delay a (a) to the rectified output.
The above II flow circuit 11 (D output Ell and phase shift -
The switch 11 gives a ON signal to the second switch 11 only when the potential difference between the line 15 and the phase-shifted output EiJ is less than a predetermined value.
This is the timing signal generation path. Note that a rectified output and a phase-shifted output are provided to the first switch 14 via an X adder 11 made of a diode.
0 output through the second switch 1r?
Give it to 19 and photoelectrically. And the charging voltage of this memory controller/7''' pin 19 is the buffer 1 of the input impedance.
0 from the output terminal 11. Adder 1
A discharge resistor 22 is inserted in the output of the memory capacitor t19, and the charging voltage of the memory capacitor t19 is lll compared to the output voltage of the adder 180.
1, the difference is discharged via the discharge resistor 22\
, I try to do so.

このような構成であれば、父渡偏号源11から55諏偵
号目(嬉3図偽))が与えられると整流@1;2からは
11流出力E目(第3図(b〕)、移相器IJからは移
相出力E12(第3図(b))が出力される。そして*
線出力Ellが設定gEmJを越える部分でのみオン僅
号(渠3図(C))がaglのスイッチ14へ与えられ
販スイッチ14をオンさせる。また丈ングルタイミング
侶号発生回路16に↓すIl猿出力at1と移相出力E
iJとの電位差が用足の設定値よりも小さいときにのみ
17m号(第3図(d))が第2のスイッチ11へ与え
られ該スイッチ11をオンさせる。そして第11第2の
各スイッチJ4.J7がオンしている閣にメモリコンf
”7t19の充電電圧が加算器18の出力に等しくなる
ように光電あるいは放電抵抗22による放電かなされる
。したがってメモリコンデンサ19の光電電圧Ec(@
3図(・))は交a信号Elの変化に対応し、との光電
電圧Eaはバッファ20を介して出力端子21からアナ
ログ備考F、oとして出力される。
With this configuration, when the 55th reciprocal signal (False 3rd figure) is given from the father's deviation signal source 11, the rectification @1; ), a phase shift output E12 (Fig. 3(b)) is output from the phase shifter IJ.
Only when the line output Ell exceeds the setting gEmJ, an ON signal (Channel 3 (C)) is applied to the agl switch 14 to turn on the sales switch 14. In addition, Il monkey output at1 and phase shift output E are input to the length timing signal generation circuit 16.
No. 17m (FIG. 3(d)) is applied to the second switch 11 to turn on the switch 11 only when the potential difference with iJ is smaller than the set value of the foot. and each of the eleventh and second switches J4. Memory controller f in the cabinet where J7 is on
``7t19 is discharged by the photoelectric or discharge resistor 22 so that the charging voltage of the adder 19 becomes equal to the output of the adder 18. Therefore, the photoelectric voltage Ec of the memory capacitor 19 (@
3 (·) corresponds to the change in the alternating current a signal El, and the photoelectric voltage Ea is outputted from the output terminal 21 via the buffer 20 as analog notes F, o.

〔発明の効果〕〔Effect of the invention〕

したがって交に1i(号の姫流出力とこれを移相し九移
相出力とが所定の電位差以内でかつ上記整流出力が所定
電圧を越えていると1にのみ上記Ii流出力および移相
出力の加算値をすングルホールドするようにしている。
Therefore, if the output of the output of the output of the princess of 1i (No. 1) and the phase-shifted output of 9 are within a predetermined potential difference, and the rectified output exceeds the predetermined voltage, the output of the output of the Ii and the phase-shifted output will only be 1. The added value is held in place.

したがって交流信号が極めて低賦波数の場合あるいは周
波数が変化する場合にも確実に動作し、かつ構成も極め
て藺導である。
Therefore, it operates reliably even when the alternating current signal has a very low number of waves or changes in frequency, and the structure is extremely simple.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の交流信号のレベル漏電方法を示すブロッ
ク図、第2図は本発明の一実施例を示すブロック図、第
3図は上記実施例の動作を説明する波形図でおる。 11・・・交t&信号源、12・・・**器、II・・
・検出慣号チェック回路、14・・・41のスイッチ、
15・・・移相器、16・・・サングルタイ建ンダ傭号
発生同路、17・・・第2のスイッチ、11・・・加算
器、19・・・メモリコンデンサ、20・−・バッファ
、2ノ・・出力端子、22・・・放電抵抗。 出膳人代場人  弁理士 鈴 江 武 彦1115 第2図
FIG. 1 is a block diagram showing a conventional AC signal level leakage method, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram explaining the operation of the above embodiment. 11...AC & signal source, 12...** instrument, II...
・Detection inertia check circuit, switches 14...41,
DESCRIPTION OF SYMBOLS 15... Phase shifter, 16... Sungle tie construction/signal generation same circuit, 17... Second switch, 11... Adder, 19... Memory capacitor, 20... Buffer, 2: Output terminal, 22: Discharge resistor. Serving person Patent attorney Suzue Takehiko 1115 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 交流信号をIi流する整流器と、この姫訛−のli流出
力を所定菫たけ移相する移相器と、上紀整訛出力が用足
レベルよりも大なるときにオン信号を出力する検出偏号
チェック回路と、上記整流出力および移相器の移相出力
を与えられかつ上紀慣出16号チェック回路から与えら
れるオン信号でオンする第1のスイッチと、上記整流出
力と移相出力との電位差が所定値よりも小さいときにオ
ン信号を出力するサンデルタイイング信号発生回路と、
上記第1のスイッチの出力を与えられかつ上自己サンダ
ルタイミング信号発生回路から与えられるオン16gで
オンする第2のスイッチと、この第2のスイッチから与
えられる信号のレベルに応じ九電位に光電され上記交a
m号のしくルに応じたアナログ櫨を陳持するメモリコン
デンサとを具備する交流イメ号レベル測定装置。
A rectifier that flows an alternating current signal Ii, a phase shifter that shifts the phase of the li output of this princess accent by a predetermined step, and a detection device that outputs an on signal when the li output of the princess accent is greater than the usage level. an eccentricity check circuit; a first switch that is supplied with the rectified output and the phase shift output of the phase shifter and is turned on by an on signal supplied from the Joki Ide No. 16 check circuit; and the rectified output and the phase shift output. a sander tying signal generation circuit that outputs an on signal when the potential difference between the
A second switch is supplied with the output of the first switch and is turned on at 16g supplied from the self-sandal timing signal generation circuit, and the second switch is photoconducted to nine potentials according to the level of the signal supplied from the second switch. The above connection a
An AC image level measuring device equipped with a memory capacitor that displays an analog signal corresponding to the mechanism of the m level.
JP3274382A 1982-03-02 1982-03-02 Measuring device of alternating-current signal level Pending JPS58148969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3274382A JPS58148969A (en) 1982-03-02 1982-03-02 Measuring device of alternating-current signal level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3274382A JPS58148969A (en) 1982-03-02 1982-03-02 Measuring device of alternating-current signal level

Publications (1)

Publication Number Publication Date
JPS58148969A true JPS58148969A (en) 1983-09-05

Family

ID=12367313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3274382A Pending JPS58148969A (en) 1982-03-02 1982-03-02 Measuring device of alternating-current signal level

Country Status (1)

Country Link
JP (1) JPS58148969A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007313803A (en) * 2006-05-26 2007-12-06 Matsushita Electric Works Ltd Manufacturing method for multi-layer laminated plate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007313803A (en) * 2006-05-26 2007-12-06 Matsushita Electric Works Ltd Manufacturing method for multi-layer laminated plate

Similar Documents

Publication Publication Date Title
JP6211166B2 (en) Handrail inspection device and handrail inspection system
KR20060089729A (en) Magnetic bridge electric power sensor
CN107037255A (en) A kind of ripple voltage detects circuit
JP2010197223A (en) Wattmeter
US3846688A (en) Machine work sensor
JPS58148969A (en) Measuring device of alternating-current signal level
US8477057B2 (en) Systems, methods, and apparatus for sensing AC voltage
JP2569971B2 (en) Power ripple measuring instrument
JPH0452901B2 (en)
JPS58165058A (en) Insulation type current detector
JP2007121125A (en) Current detector and capacitance measurement device
JPH05297038A (en) Grounding-resistance testing instrument
JP3211020B2 (en) Displacement detector
CN114047419B (en) Silicon controlled rectifier detector and silicon controlled rectifier performance detection method
JP4081327B2 (en) Resonant switching power supply
KR20180022387A (en) Apparatus and method of detecting connection error
JP2008076337A (en) Input impedance measuring instrument and method
JPH08182180A (en) Integration judging circuit and resistance component leakage detecting circuit using it
JPH08160083A (en) Instrument and method for measuring insulation resistance to the earth for low-voltage circuit
JPH05292742A (en) Switching power supply
RU2401432C1 (en) Reactive power measurement device
SU73807A1 (en) AC Frequency Meter by Compensation Method
SU80953A1 (en) AC rectifier
JPS59107212A (en) Level measuring method
SU630597A1 (en) Phase metering arrangement