JPS58148453A - Semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably reduce the incidence of soft errors for the titled semiconductor device by a method wherein, in the case of flip-flop type memory consisting of an assembled FET, a metal layer whereon a prescribed potential was given is arranged on a memory cell through the intermediary of an insulating film. CONSTITUTION:An insulating film 10 and a metal layer 11, made of aluminum, tungsten, gold and the like, are added to the static memory using the load which has heretofore been in use as resistance, and the metal layer 11 is generally grounded. According to this constitution, the capacitance by insulating films 7 and 10 is generated between a memory node N15 and the metal layer 11. As a result, a capacitor CA is added between nodes N1 and N2, and the memory cpacity of the device is increased. As the memory capacity is increased as above, the amount of critical charge is increased too, and at the same time, the number of alpha particles and energy are attenuated by the insulating film 10 and the metal layer 11, thereby enabling to reduce the generation of soft errors.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using a flip-flop type circuit as a memory cell.

FIG. 1 is a circuit diagram showing a memory cell of a conventional flip-flop type circuit and for explaining the present invention. In the same figure, (TI) and (T1) are transfer cables, respectively, and (Qs) are driver transistors. load resistance, (Bl
) and (Bm) are bit lines, (Vc) is a power supply voltage, and (Nu) and (Bm) are nodes, respectively.

Note that the sources of the driver transistors (Ql) and (Ql) are commonly connected and connected to the ground, the drain of the driver transistor (Ql) is connected to the gate of the driver transistor (Q,), and the driver transistor (-
) is connected to the gate of the driver transistor (Qt) and latched together. And in writing and glaring cycle)
(Ts) and (-) are turned on, nodes (N1) and (N1) are turned on, bit lines (Bl) and (B
, ).

Next, the operation of a memory cell of a conventional flip-flop type circuit will be explained with reference to the first factor and FIG.

First, let the potential of the node (N1) be ■, and the potential of the node (N2)
If the potential of is ■, then the 2 of this flip-flop circuit is
As shown in Figure 2, the two stable operating points are y, = vC%v
Point P where ==o and point Q where v1=0 and %=Vc. Therefore, in the (vl-%) plane, the potential vt yV! When is on the A side of dotted line F, it settles at point Q, which is the stable operating point, and B#! Point P, which is the stable operating point when it is at I
The latch is fixed. When the potentials X and 1 are both lower than VT (driver transistor (Ql) and (Q's I, key k1M pressure), driver transistors (Q8) and (Ql) are both turned off).
, flip-flop type circuits are in a very unstable state.

However, in semiconductor memory devices that use conventional flip-flop circuits as memories, α particles emitted from radioactive substances contained in packaging materials generate electron-hole pairs in the silicon substrate, causing So-called soft errors, in which electrons reach nodes in the N-type diffusion layer due to the electric field and lower the potential there, change the data content, are likely to occur. That is, node (N1
) is L level (vl=O), /-)' (Ns) b
At the sH level (%wvc), even if an α particle hits the drain of the driver transistor (Ql), data will not be inverted because it will strengthen the Ql, but an α particle will hit the drain of the driver transistor (Ql). When hit, the potential of the node (N2) decreases to (V□, ~) as shown in Figure 2.
If the area is flat, the latch will not be fixed and it will become unstable), increasing the possibility of soft errors occurring.

Therefore, '%l, = Q.

The potential difference from the stable point to the unstable point at point Q where 1=0 is Vc-VT. Therefore, if the potential drop due to the collected electrons exceeds this value, the probability that a soft error will occur increases. Also, when starting to stare, the potential ship is V
(c), so if the number of electrons converged at a node is the same, the error rate will be high.

Therefore, an object of the present invention is to provide a semiconductor memory in which the incidence of soft errors is extremely reduced.

Storage node due to charge generated by α particles, Nl
A soft error occurs when the change ΔV in the potential of eNl becomes larger than Vc - VT, so the critical charge ff1Qcri (which causes a soft error) is expressed as -.

Qcrit = C(Vcc - VT) where C is the larger the capacity Q(rit) of the storage node, the less likely soft errors will occur.To increase Qcrit, increase the capacity jIC of the storage node, -There is a way to increase VT, but the latter is determined from the beginning of the design and cannot be changed significantly.

Therefore, the most effective method in this case is to increase the capacity Ck of the storage node.

The present invention provides a semiconductor device in which the states of nodes of memory transistors are increased.

This will be explained in detail below using examples.

FIG. 8 shows a part of a cross section of a conventional static memory in which a resistor is used as a load. The capacitance of the storage node Nl is mainly due to the junction capacitance of this node, the stray capacitance associated with the gate capacitors of the transistors and their interconnections. The junction capacitance cannot be increased due to the requirement to reduce the memory cell area.

FIG. 4 shows an embodiment of the present invention. s
In addition to the state shown in the cross-sectional view in the figure, a metal layer 11 of aluminum, tungsten, gold, etc. is added to the insulation #l,
Metal layer 11 is generally grounded to earth.

With this structure, storage node N 1 (5) and metal layer 1
There is an insulating film 7 between 10 and 10. A capacitance due to IO will occur. As a result, as shown in diagram rk6, a capacity tCm is added between nodes Nl and N2, increasing the storage capacity.

Due to this increase in capacitance, the critical charge Qcr
It becomes artificial, and the number and energy of α particles are attenuated by the metal layer 11 in the insulating film 1, and soft errors are corrected.

The present invention can be easily applied to static W formed on compound semiconductors such as GaAs.

[Brief explanation of the drawing]

Fig. 1 is a conventional static RAM memory cell circuit diagram, Fig. 2 is an explanatory diagram of the operating point of static theory, Fig. 8 is a sectional view of conventional static theory, and Fig. 4 is a static RAM of an embodiment of the present invention. FIG. 5 is a memory cell circuit diagram of a static support according to an embodiment of the present invention. l...Semiconductor substrate, 2...Isolation oxide film, 8...Gate electrode, 4...Diffusion node (GN/D
), 5...Storage node, 6...Load resistance, 7.
... Oxide film, 8... Metal wiring (GND), 9... Metal wiring (Vcc), 10-... Insulating film, 11... Metal layer. Agent Makoto Kuzuno - Figure 1 c Figure 2 Figure 3 □ [ Figure 4 Figure 5 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 112016/1989 2
, Title of the invention Semiconductor device 3, Relationship to the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitachi Katayama 4, Agent Address: 2-2-3-6, Marunouchi 2-chome, Chiyoda-ku, Tokyo, Claims column 6 of the specification to be amended, Contents of the amendment (1) Correction of the Claims column of the specification as shown in the attached sheet. do. 7. List of attached documents (1) One or more documents stating the amended scope of claims Claims (1) A combination of first and second insulated gate field effect transistors (hereinafter abbreviated as FET) In the flip-flop memory, the first node of the first FET is connected to the gate of the second FET, and the first node of the twentieth FET is connected to the gate of the second FET.
The node of is connected to the gate of the first FET, the 20th node of the first and second FET is a commonly connected flip-flop as a memory cell, and on this memory cell,
A semiconductor device characterized in that a metal layer applied with a predetermined potential is arranged with an insulating film interposed therebetween. (2) The semiconductor device according to claim 1, wherein the insulated gate field effect transistor is formed of a compound semiconductor. (3) The semiconductor device according to claims 1 and 2, wherein the predetermined potential is set to a high potential or a low potential (ground) among the power supply potentials used.

Claims (3)

[Claims] (1) In a flip-flop memory formed by combining first and second insulated gate field effect transistors (hereinafter abbreviated as FETs),! The first node of the 11110 FET is connected to the gate of the second OFET, and the first node of the second OFET is connected to the gate of the second OFET.
The first node of is connected to the gate of the first FET, the 20th nodes of the 1st and 20th FETs are commonly connected flip-flops as memory cells, and a predetermined potential is applied to this memory cell. 1. A semiconductor device characterized in that a metal layer is arranged with an insulating film interposed therebetween. (2) A patent claim characterized in that it is formed of an insulated gate sleep field effect transistor and a compound semiconductor.
j. The semiconductor device according to item 1. (3) The semiconductor device according to claims 1 and 2, wherein the predetermined potential is a higher potential or a lower potential (ground) of the used power supply potential.