JPS58147887A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce cell area and to obtain ideal symmetry to unreversible characteristics of a static type semiconductor storage circuit which uses a GaAs substrate, by adding at least two diffused layers and constituting an address selective transistor (TR). CONSTITUTION:A bipolar TR is an NPN TR having a collector 3-2, base 2, and emitter 3-3; the base 2 is connected to an address line and the emitter 303 is connected to a data line. The current gain of the bipolar TR which is a performance index is determined by the 3-2 and 3-3, but this consists of Self and Align as evident from its structure, so an extremely large value is obtained. The 3-2 is the drain of an MESFET and also the collector of the bipolar TR. The address selective TR is constituted only by adding the 2 and 2-3, so the constitution area is much less than usual.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a static type semiconductor memory device, and mainly relates to improving the characteristics of a device using a GaAs substrate.

Static RAM uses bistable flip-flop circuits as memory cells, and either stable state is 1",
Information is stored with the opposite value set as "0". Therefore, information is stored as long as power is supplied.

Figure 1 shows the cell configuration of static hazy.

The memory cell consists of transistors T and -T4 forming a flip-flop and address selection transistors Ts and 'rs. The figure shows an example in which a flip-flop is configured with an EA type inverter in which the driver is an enhancement type and the load is an enhancement type. E/D type, 6 made in Depressi type due to the load configuration.
There is also a CMOS static type made of MO8 and an E/R type in which the load is formed by a resistor. Each cell basically consists of six elements.

The basic operation of the memory cell shown in FIG. 1 will be explained. It is assumed that this cell is selected by the address signal. At this time, 'r, , 're are conductive, and T1 + "2 *
T3 H'r.

The state of the flip-flop (F/F) consisting of Assuming that T2 is now ON and 'r is OFF, node A + i 0 potential and node B are at VDD level.

Therefore, H level and L level are read to the data line and the data line, respectively.

On the other hand, to invert the F/F, use the address signal as above to select this cell and set D to H level and D to L level to iF.
When input, T1 becomes conductive and T2 becomes non-conductive, F/F is inverted and the address line is made non-conductive (No)'B4! L
level, node A i,t H level is maintained.

Ts, Ts) The transistor reads the memory cell,
Since it works as an iI-loaded switch, it is desirable that it operate at high speed and occupy a small area in order to enable high integration.

Furthermore, since a large number of memory cells are connected to the data lines D and D, the coupling capacitance becomes large, and T8. The T6 transistor needs to have high driving capability.

In view of the above points, the present invention is constructed using a substrate such as GaAs. In a static type semiconductor memory device, the address selection transistor is formed in the minimum area and becomes a #ζ pub-polar transistor, so that the current driving ability does not decrease even if a large number of memory cells are connected to the data lines D and D. The purpose is to

1. An embodiment of the present invention is shown in FIG. In FIG. 2, the memory cells are ME of Q+, Ql, Qs, Q4.
Composed of SFETs, address selection transistors Qa, Q
s is a bipolar transistor. It is assumed that this cell is selected by the address signal. Q2 is on now
.

When Ql is in the OFF state, node C is at the 0 level and node D is at the VDD level. For this reason, H level and L level are read on the data line and data greenstone, respectively. On the other hand, to invert this F/F, select this cell using the address signal as described above, write H level to D and L level to D, node D becomes L level, node C becomes H level, and Ql becomes ON, Ql is turned OFF, F/F is inverted, and the address line is made non-conductive, thereby maintaining node D at L level and node C at H level. , FIG. 8 is an IC cross-sectional view showing one embodiment of the present invention.
, Qa, Qs, and Qs.

MESFET QIQ2 has 8-1, 8-2 as a source and drain, 5 as a gate, and 4 as a channel region.

In the bipolar transistors Qa and Qs, 8-2 is the emitter, 8-8 is the collector, and 2 is the base.

The base region of the transistor E7 is connected to the address line, and the transistor E7 is connected to the data line D.

FIG. 4 shows a method of forming the IC structure shown in FIG. In FIG. 4, reference numeral 1 denotes a semiconductor substrate, and a substrate having a semi-insulating resistivity is usually used.

After forming the insulating film 10 on the entire surface of the substrate, a resist film 20 is applied using a mask. After patterning the region 2, the region 2 is formed by P-type ion implantation (3). Using the same procedure, patterning is again performed using the insulating film 10 and the resist 21 to form a region 4, and n- ion implantation @, which will become a channel region, is performed to form a region 4. Continuing to the 4th
As shown in figure (C), n+ ion implantation O was performed, and 8-
Regions 1, 8-2, and 8-8 are formed. The entire area is covered with an insulator and heat treated to form a MESFET and a bipolar transistor.

In Fig. 4(a), make ohmic contact and insulating film 8.
0 and complete the Schittky gate 50 and internal wiring.

The bipolar 1 transistor according to the present invention is 8-2.2°8
NPN with −8 as erector, base, and emitter, respectively
The current gain, which is the figure of merit of the transistor, is determined between 3-2° and 8-8, but as is clear from the structure, since it is formed of 5elfAttgn, the current gain can be changed to an extremely large value. Also, 8-2 is the drain of the MESFET (it becomes the collector of the polar transistor). Since the address selection transistor can be configured by simply adding 2 and 8-8, the configuration area can be significantly reduced compared to the conventional configuration. becomes possible.

In addition, the transistor consisting of 8-2, 8, and 8-8 is a so-called lateral NPN transistor, and even if 8-2 is the emitter and 8-8 is the collector, its basic operation is different. Needless to say, good tropism is another advantage of this configuration.

As is clear from the above description, the present invention makes it possible to configure an address selection transistor in a static semiconductor memory circuit other than 81, which mainly uses a GaAs substrate, by adding at least two diffusion layers. The area can be reduced. In addition, the conventional problem of increased data line capacitance due to the large-capacity structure can be compensated for by the driving ability of bipolar transistors, and the symmetry of irreversible characteristics can be idealized by using lateral NPN transistors. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram used in a semiconductor static RAM whose substrate is mainly GaAs other than Si. FIG. 2 shows a semiconductor static R showing an embodiment of the present invention.
In the AM configuration diagram, Ql, (h, Qs, Q4
is MESFET. Qh and Qs are bipolar transistors. VDD is a power supply, Vss is a ground, and D and D are data lines. FIG. 8 is a sectional view showing an embodiment of the present invention as an IC, in which 1 is a substrate of the first conductivity type, and 2 is a second conductive shadow region. 8-1.8-2 and 8-8 are second conductive shadow areas. 4 is a channel region of the second conductivity type, and 6 is a gate region. FIG. 4 is an explanatory diagram showing a specific configuration method of the present invention.
2.8-1.8-2.8-8.4.5 is the same as tm, IO is the insulating film, 20.80 is the resist film for pattern error, and 40 is the shot key gate and internal wiring. 50 is an ohmic contact to the diffusion region, ■ indicates P type @ n- type 0 indicates n type ion implantation. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 At L7 line D Claims + 11 No. 1. Second. 8th. a fourth transistor;
The gate of the first transistor is connected to the drain of the second transistor, the gate of the second transistor is connected to the drain of the first transistor, and the first... The sources of the second transistors are commonly grounded, and the sources of the 8th and 4th transistors are respectively grounded. A flip-flop connected to the drain of the second transistor and whose gate and drain are commonly connected to the power supply, and a sixth transistor that transfers the memory state of the flip-flop to the data line by an address selection signal. Preparation, Section 5 above. The base of the sixth transistor is connected to the address line, the collector of the sixth transistor is connected to the drain of the first transistor and the source of the eighth transistor, the collector of the sixth transistor is connected to the drain of the second transistor and the source of the fourth transistor, 5. A semiconductor memory device characterized in that the output of the emitter of the sixth transistor is connected to a data line. 12+J51- The emitter of the transistor is connected to the drain of the first transistor and the source of the eighth transistor, the emitter of the sixth transistor is connected to the drain of the second transistor and the source of the eighth transistor, and the emitter of the sixth transistor is connected to the drain of the second transistor and the source of the eighth transistor. 2. The semiconductor memory device according to claim 1, wherein the collector output of the sixth transistor is connected to a data line. (3) No. 8. The semiconductor memory device according to claim 1, wherein the fourth transistor is constituted by a resistor. (4) First. Second. 8th. The fourth transistor is MESF
ET, 51st 6th transistor bipolar NP
N) The semiconductor memory device according to claim 1, which is a transistor. (5) First. 5. The semiconductor memory device according to claim 1, wherein the drain of the second transistor and the emitter or collector of the bipolar transistor are shared. (6) 1st. Second. 8th. The fourth transistor is MESF
ET, 5th. 2. The semiconductor memory device according to claim 1, wherein the sixth transistor is a bipolar lateral transistor. (7) Using GaAs for the semiconductor substrate, the fifth. 2. The semiconductor memory device according to claim 1, wherein the emitter or collector of the sixth transistor is formed at the same time as the drain and source of the first and second transistors are formed.

Claims (1)

[Claims] (1) First. Second. 8th. a fourth transistor;
The gate of the first transistor is connected to the drain of the second transistor, the gate of the second transistor is connected to the drain of the first transistor, and the first... The sources of the second transistors are commonly grounded, and the sources of the 8th and 4th transistors are respectively grounded. Connected to the drain of the li2 transistor,
The sixth transistor includes a flip-flop whose gate and drain are commonly connected to a power supply, and a sixth transistor that transfers the storage state of the core flip-flop to a data line by an address selection signal. The base of the sixth transistor is connected to the address line, the collector of the sixth transistor is the drain of the first transistor and the source of the eighth transistor, the collector of the sixth transistor is the drain of the second transistor and the source of the fourth transistor. A semiconductor memory device characterized in that the outputs of the emitters of the fifth and sixth transistors are connected to a data line and a data line. The emitter of the (2+5th) transistor is connected to the drain of the first transistor and the source of the eighth transistor, the emitter of the sixth transistor is connected to the drain of the second transistor and the source of the eighth transistor, and the emitter of the sixth transistor is connected to the drain of the second transistor and the source of the eighth transistor. 2. The semiconductor memory device according to claim 1, wherein the collector output of the sixth transistor is connected to a data line. (3) No. 8. The semiconductor memory device according to claim 1, wherein the fourth transistor is constituted by a resistor. (4) First. Second. 8th. The fourth transistor is MESF
ET, No. 6. 6th transistor bipolar NPN
) The semiconductor memory device according to claim 1, which is a transistor. (5) First. 5. The semiconductor memory device according to claim 1, wherein the drain of the second transistor and the emitter or collector of the bipolar transistor are shared. (6) 1st. Second. 8th. The fourth transistor is MESF
ET, 5th. 6) The semiconductor memory device according to claim 1, wherein the transistor is a bipolar lateral transistor. (7) Using GaAs for the semiconductor substrate, the fifth. The emitter or collector of the sixth transistor is formed in the first and second transistors.
When forming the drain and source of a transistor, they are formed at the same time! A semiconductor memory device according to claim 1.