JPS58146156A - Data transmitting system - Google Patents

Abstract

PURPOSE:To transmit data with high reliability, by dividing the operating state of a receiver into the 1st state retrieving synchronizing codes at each bit, the 2nd state using a synchronizing detection window, and the 3rd state of synchronism state, giving severe transfer condition when the 1st transfers to the 2nd, and relaxed condition to the 3rd state. CONSTITUTION:A reception signal is inputted to a shift register 6, compared with a pattern of a pattern generating circuit 7 at a comparison circuit 8, and a coincidence bit, ''0'' and a dissidence bit, ''1'' are inputted to a shift register 9, ''0'' is counted at a counter 10, and as the result, a count number S is given to a processor and the transfer condition among the states depends on the number of counts S. The content of the shift register 9 is read in the processor via the counter 10 every time one-bit of the reception signal is received at the 1st state ST1. In the 2nd and 3rd states ST2, ST3, the content of the counter 10 is read in the processor in the timing to detect the synchronizing code.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system, and more particularly to a data transmission system that performs synchronous transmission using a serial signal to which a synchronization code Y is added.

Conventionally, there has been a data transmission system of this type that transmits information in a format as shown in Figure @1. @1 In the figure, 1 is a start code with a unique pattern t made up of multiple bits, and 2 is data with a fixed pit length, which contains information to be transmitted from the transmitting device to the receiving device. 3 is a stop code having the same format as the start code 1 and a unique pattern t.

Start code 1. Data 2 and stop code 3 constitute one transmission unit, ie, a frame. The transmission signal sent from the transmitting device consists of a series of such frames, and the receiving device detects the start code 1t', decodes the original information Y from data 2, and detects the stop code 6 to decode the received data 2. Information Y is assumed to be valid.

In order to detect the start code 1 and stop code, the receiving device includes a pattern generation circuit that generates those patterns, and the contents of the received transmission signal Y.

A comparison circuit is provided that detects a match between the same number of bits as the pattern and the bits of the pattern of the pattern generation circuit. When detecting a start code in the initial state, a search for start code 1 is performed by checking the output Y of the comparator circuit every time 1 bit Y of the transmission signal is newly received. stop code 6
When detecting χ, if the frame length is known in advance, such as a fixed length of 7 frames, a detection window is opened at a predetermined timing after start code 1 is detected, and a matching signal is output from the comparison circuit. Check whether it is done or not. As a result, when a match signal is output, the information received as data 2? If it is valid, there is a possibility that there was an out-of-synchronization, so the information received as data 2? Invalid, that is, dismissed. Next, the receiving device starts searching for the start code 1 described above from the initial state.

In conventional data transmission systems, when a stop code sound cannot be detected as described above, the system returns to the initial state and searches for a start code, so it takes a long time to establish synchronization. If sign and Y are detected consecutively, data? There was a drawback that made it effective.

This invention was made to eliminate the above-mentioned drawbacks of the conventional system, and the operating state of the receiving device can be divided into three states depending on the degree of matching of synchronization code patterns: synchronization code? The first state to explore.

It is estimated that it is in a synchronized state, and performs a synchronization code detection operation at a predetermined timing.@2 It is determined that it is in a synchronization state, and it performs a synchronization code detection operation Y at a predetermined timing, and the received data Y is valid. The conditions for transition from the first state to the second state are set to be the strictest, and the retention conditions for the third state χ are set to be the most gentle. By setting the transition conditions to the state, it becomes easy to return to and maintain the synchronized state.

Another object of the present invention is to provide a data transmission method that can shorten the time from an initial state to a synchronized state and can provide efficient and reliable data transmission.

An embodiment of the present invention will be described below with reference to the drawings. Second
The figure shows the format of the transmission signal, where 4 is a 24-bit synchronization code with a unique pattern Y of sharp autocorrelation, and 5 is a fixed number of bits contained in the information to be transmitted (for example, 144
The data consists of bits, of which 48 bits are check bits.

FIG. 3 shows a block diagram of a receiving device that receives a transmission signal having the format t shown in FIG. In Figure 3,
6 is a 24-bit shift register that inputs the transmission signal t-pit serial; 7 is a pattern generator that generates the same pattern Y as the synchronization code 4 of the transmission signal; 8 is composed of 24 exclusive logic gates;・Register 6 and ノ (
A comparator circuit that detects a coincidence Y between each bit with the turn generator 7; 9 is a 24-bit tact register that leads the output signal of the comparator circuit 8 to a parallel input, converts it into a serial signal and outputs it; 10 is a shift register; This is a 5-bit counter that counts the I□m bits output from register 9. The count result S of the counter 10 is sent to a processor (CPU) not shown. Reference numeral 11 is an 8-bit register that latches the data (5% of the data of the transmission signal: content) stored in the shift register 6 using a strobe. The strobe generating circuit for latching the register 11v is not shown because it is not the gist of the present invention and any known circuit may be used. Further, the processor may also be of a normal stored program type.

Next, the operation will be explained. The received transmission signal is sampled by the clock 1 bit F at a time and is input to the shift register 6. The contents of the shift register 6 are compared with the data of the pattern generator 7 by the comparison circuit 8, and the matching bit becomes 10'' and the mismatching bit becomes @11 and is input into the shift register 9. The contents of shift register 9 are sent to counter 10 and 'O''
The number of bits is counted. The count result S of the counter 9 is sent to the processor.

FIG. 4 is a state transition diagram illustrating the operating state of the receiving device. The operating state of the receiving device is an initial state 8T1 . It is presumed that synchronization code 4 is detected, that is, it is presumed to be in a synchronized state, and the operation is performed based on the state 1! ! 8
T2. and a state 8T5 in which the synchronization code 4 is detected, that is, the state is assumed to be in a synchronized state.

In state 8T1, the count number S of the counter 10 is 8, >
St > 83 > 84 > as has a relation χ with a maximum of 2
Constant equal to 48. On the other hand, when the condition is JI8T1, K8
When < 8° (transition T, 1), state 8T2 and 18 < 8a (transition T2.) and state f1
This is when S<S at 8T5 (transition T8.). In state 8T1, each time the shift register 6 newly inputs one bit of the transmission signal, the contents of the shift register 9 are read into the processor via the t counter 10t' and the synchronization code 4 is searched. As a result, when Ss≦8, the state shifts to the upper state 8T2 through transition T, .

In state 8T2, Ss<S<S in state ST2
.

(transition T4), when state a8T1, S1≦
8 (transition Tu) and state ST3, S
, ≦S < S4 (transition Tst).

In state 8T2, it is presumed that the receiving device is in a synchronized state, so the synchronization code 41: At the timing to be detected, the contents tm of the shift register 9 are read via the counter 10v. As a result, the count number 8 is 8<8. When it becomes (transition T□), it returns to the lower state 1118T1,
Also, when St≦8, the highest level, that is, the state of synchronous state 1
11sT3, and the data continued from the register 11 becomes valid.

State 8T3 is 84≦8 in state ST3 (transition T1.) and 8.8 in state 8T2. When ≦S (transition To), it is assumed that the information of data 5 read into the processor via the register 11 is valid. At this time, if data 5 has a code error, data 5Y
- Correct processing by included check bits (48 bits).

However, in state ST5, S, ≦S (when Sa, returns to lower state l1118T2 and pc transition T8.)
, and when it becomes 8 (S), it returns to the lowest state 8T1 (transition T1.). In state ST!, the contents of the counter 10 are continued at the same timing as in state ST2, that is, the synchronization detection window is Open it and examine its contents.

The correspondence between transitions T11 to Tsm and count numbers is shown in a table.

For example, in state a8T3, when S≦S<84, it is considered that the synchronization code 4 and part of the data 5 have changed due to temporary noise, so the state returns to state 8T2 and the primary synchronization code 4 is changed. Wait for detection. In the detection of the next synchronization code 4, even if the detection window Y is opened at a predetermined timing, as long as there is no continuous noise, there is a sufficient probability that S<S
Since the conditions of transition T7. By 11J8
At T5, the data read into the processor becomes valid. Such an operation shortens the time required to achieve resynchronization compared to the case of acquiring synchronization from the initial state again.

As described above, according to the present invention, a synchronization code is searched bit by bit according to the degree of matching of the patterns of Y synchronization codes in the operating state of the receiving device.
Divided into 2 states in which the synchronization detection window Y is opened at a predetermined timing and @3 states in which the synchronization detection window Y is opened, and @3 states in which the synchronization detection window Y is opened at a predetermined timing.
Condition for transition to state? The conditions for transition to the upper state are set to be the strictest, and the conditions for transition to the lower state are set to be the most relaxed, so
It is easy to return to and maintain a synchronized state, the time required to reach the initial state can be shortened, and efficient and reliable high-level data transmission can be realized.

[Brief explanation of the drawing]

FIG. 1 is a format diagram of a transmission signal in the conventional data transmission system, FIG. 2 is a format diagram of a transmission signal in the data transmission system of the present invention, and FIG. 3 is a block diagram of a receiving device according to the data transmission system of the present invention. FIG. 4 is a state transition diagram of the receiving device shown in FIG. 3. 6.9... Shift register, 7... Synchronous pattern generator, 8... Comparison circuit, 10... Counter, 11
···register. Agent Shin Kuzuno - (1 other person) Drunk 1
Zugawa 2 Wa No. 3 ゛me No. 4 Amendment to figure procedure (voluntary) Commissioner of the Japan Patent Office 1 Indication of the case Japanese Patent Application No. 80781/1982 2.
5 &Ming's name Data transmission method 3, Person making the amendment Representative Hitoshi Katayama Section 5, Subject of amendment (1) Scope of claims in Ming a9 (2) Detailed explanation of the invention in the specification (3) Drawing 6, contents of amendment (1) Amend the attached claims. (2) The phrase [-data] on page 4, line 10 of the specification is corrected to "erroneous data." (3) In the 12th line of page 6 of the specification, correct the statement "1-Register 11" to read "The data in register 11 is sent to the processor. A clock and register 11 to create shift register 6.9t-0." . (4) On page 7, line 17 of the specification, [(transition Tl1) state S
1 (4 transitions, state ST2)
"When," he corrected. (5) The statement l-83<8<82 J on page 8, line 6 of the specification is corrected to [S3≦8<82 J. (6) In the table on page 10 of the specification, write “
The phrase “S4×S” is corrected to “S2≦S”. (7) The text "Synchronization code 4 and data 5" in the seventh to sixth lines of the bottom of page 10 of the specification is corrected to "Synchronization code 4". (8) In the second line from the bottom of page 10 of the specification, [82<S J] is corrected to "S2≦S". (9) Correct Figure 2 on a separate sheet. 4. Correct Figure 3 on a separate sheet. 7. List of attached documents (1) One document stating the amended scope of claims (2) One document stating the amended Figure 2 (3)
) A document stating the corrected figure 3 1 Claims after overcorrection A synchronization code formed from a plurality of bits and having a unique pattern, and a fixed number of bits forming information to be transmitted. In a data transmission system that continuously transmits a transmission signal consisting of content data, a receiving device is required to detect a match between the above pattern and a plurality of bits corresponding to the above synchronization code from the received series of transmission signals. number of bits S and a predetermined constant 81 to aS (however, Eh > 8
2>83>84) When Ss), S and Sl are consecutive, S3≦8 (820, when S>S3 is next, and when S4≦S and then S<Ss, the above applies) A first state in which a synchronization code is searched every time a bit of the transmission signal is received, and when Ss≦S in the first state, S3≦
When S > S2 consecutively and after S4≦S, 85≦8<
84, a second state is checked at a predetermined timing to check whether the pattern matches a plurality of focuses of the transmission signal corresponding to the synchronization code, and 84 is detected in the second state.
When 2≦S or when S4≦S continues, check at a predetermined timing whether the pattern matches the plurality of bits of the transmission signal corresponding to the synchronization code, and validate the received data. A data transmission method characterized by setting three states. Figure 2 Figure 3

Claims (1)

[Claims] In a data transmission method that continuously transmits a transmission signal consisting of a synchronization code formed from a plurality of bits and having a unique pattern Y, and data formed from a fixed number of bits and containing information to be transmitted, The receiving device receives the number of bits 8 that match the pattern and a plurality of bits of the received series of transmission signals and corresponds to the synchronization code, and a predetermined constant 8. to am (however, 8. > 8.
> s, > 8a > SS), 8 < 8tt consecutively, 8 (8, then S < S, and S4 ≦ 8 then 8 < 8. is the first state in which the synchronization code is searched every time a bit of the transmission signal is received; in the first state, when K8.<8, s
Sl≦8 (When 8, g consecutively and after S,≦8:
8. When ≦S<84, in the second state in which the coincidence between the pattern and the plurality of bits of the transmission signal corresponding to the synchronization code is checked at a predetermined timing, and in the @2 state, 8. ≦8, or when S4≦87 continues, the process checks at a predetermined timing whether the pattern matches the plurality of bits of the transmission signal corresponding to the synchronization code, and determines that the received data Y is valid. A data transmission method characterized by setting three states.