JPS58145231A - Logical gate circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption, by making the level of a transmission gate equal to an input level by a charging circuit consisting of an MOS transistor (TR) of channel type opposite to an FET used for the transmission gate. CONSTITUTION:A charging circuit inverter 5 and an output circuit inverter 6 are provided, the input of which is connected to the output of transmission gates TG10a-10d. When the TG10a is turned on and the other TG is turned off, if an input signal to an input terminal 40a is tansited from a high to a low potential, the output of the TG10a is increased from the low to the high potential, and when the value exceeds a threshold voltage of the inverters 5, 6, the output of the inverter 5 goes to a low potential to turn on a charging TR. Thus, the output of the TG10a is charged up almost to the power supply voltage VDD. Then, a through-current flows to the inverters 5, 6, allowing to prevent the usual power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic gate circuits that provide high integration density in integrated circuits.

Conventionally, in a CMO8 integrated circuit, the n-channel t shown in FIG.
A pair type transmission gate (hereinafter referred to as ``pMO8T'') is a combination of a type MO8FET (hereinafter referred to as nMO8T) and a p-channel type MO8FET (hereinafter referred to as pMO8T).
Compared to the n-channel type TG (abbreviated as TG) shown in FIG. 2, which consists only of nMO8Ts, the circuit area occupied can be reduced because the number of constituent elements is smaller.

(b) Since the input capacitance of the gate can be reduced, the delay due to the wiring resistance can be reduced.

Although it has the advantages of When the output of channel type TG is high level, pMO8T whose gate is connected to the TG output terminal
cannot be made to be in a complete cut-off state. For this reason, the CMO8 circuit, which is characterized by low power consumption, has a fatal drawback in that a steady through current flows through the CMOS gate of the next stage, causing static power consumption. In addition, in Figures 1 and 2, 8 is an inverter, 1
0 is TGllon is nMO8T, 10p is pMO8T
, 40 is an input terminal, 50 is an output terminal, and 60 is a control terminal of the TG.

Furthermore, the p-channel TG made of only pMO8T also had the same drawbacks as the n-channel TG.

The present invention provides a logic gate whose input is connected to the output of the TG, and a logic gate whose input is connected to the output of the TG, and its The F used for the TG where the gate is connected to the gate and the drain is connected to the TG output.
The charging circuit consists of a MO8T with a channel type opposite to that of the ET, so that the high level or low level of the TG output cannot be raised or lowered to the same level as that of the input. do.

Fig. 3 shows an example in which the present invention is applied to a four-manpower, one-output multiplexer, in which 1 to 4 are inverters for the input buffer sofa, 5 is an inverter that forms a charging circuit together with 20 pMO8Ts, and 6 is an output buffer inverter. It is an inverter. Here, Ip, 2p', :Up, 4p+5p, 6p is pMO8T, In, 2n, 3n, 41.5n
, 6n is nMO8T. Still 10a,
10b, 10c, ]IOdit are nMO8Ts that operate as TGs, and 30 is these nMO8Ts.
This is a Tecoder that supplies high level to only one gate of T and low level to the others. 40a, 4
0b, 40c, and 40d are input terminals, and 50 is an output terminal. 60a, 61)b l
This is a terminal for controlling the i decoder 30. 35 is a power supply terminal to which a power supply of voltage DD is connected. 36) means ground. Note that the output of each gate is
The low level refers to a potential higher or lower than the circuit threshold voltage of the gate of the next stage, respectively. The basic operating principle of a multiplexer employing a TG is to turn on only one TG, turn off the others, and guide only the input signal to the on TG to the output side. Therefore, TG 10a-10b
The operation remains the same no matter which one is on, so TGl
No Inbel V on OA's date. D is TG game)
Low level 0 is added to 10b to 10c, respectively, and T
The operation of the circuit will be explained in the case where only Glo is turned on.

In this case, since TGs 10b, 10c, and 10d are in the off state, the output of the circuit (output of inverter 6) is 4
Determined only by the human input signal to 0a. Therefore, the operation of the circuit can be investigated in the following four cases.

(a) The input signal to 40a is Inbel ■. When D is constant (b) When the human input signal to 40a is at a low level 〇 constant, when it transitions to 0 (d) When the input signal to 40a transitions from mouth 2] - to Invel ■ DD Below , these (al, (b), (cl,
The circuit operation in case (d) will be explained in detail.

(The human power signal to aj 4 o is 7 level vDD
In this case, at the output of the inverter, the input ()invel vDD is inverted and a low level 0 appears, and the inverter is outputted via the on-state TG 10a.
The man power on 5th and 6th evening was also at low level 0.

Therefore, the output of inverter 5.6 is inverted and becomes the same voltage as the input signal to 40a. High level V is applied to the pMO8T20 gate for charging. Since D is input and turned off, TG
It does not affect the output of (10a, 10b, 10c, IOd output). Note that no steady current flows in the circuit, so no power is consumed.)

(b) When the input signal to 40a is low level (in this case, the inverter is constant at 1), the output is a human low level 0.
is inverted, and no-in-bell vDD appears, and the human power of 5.6 is also at no-level through the on-state TG 10a. Since this level of TG output turns on the charging pMO8T 20 instantly, TGloa is raised to ■DD by the pMO8T 20 even though it is nMO8T. Of course, in (the output of 6 is the TG output) in bell is inverted, and the same signal 0 as the human input signal to 40a6 appears. As expected, if the steady current path in the circuit transitions to the shape Le(), in this case, N The side rises and moves from the low level side to the high level side. According to this change in the output of the manual buffer inverter 1, the output of the TGIO8 also shifts from the low level side to the high level side.

pMO8T 5p and 6p also go from on to off state, n
MO8T5n and 611 also change from off to on state, and when the output of TGloa exceeds the circuit threshold voltage of charging circuit inverter 5 and output sofa inverter 6, the outputs of these circuits 5 and 6 change from high level to low level. The output of the charging circuit inverter 5 is pMO8.
Let T20 be ty. In the absence of pMO8T 20, Toloa's output high level will be lower than VDD at least by the threshold voltage of nMOsT (larger than when grounded to 0 due to the substrate effect), but charging p MOS T 2 (If 1 is present, the output of TGIQa is lowered by the threshold voltage of nMOST, and the output of the charging circuit inverter 5 shifts to the low level side.
Conditions under which MO5T20 can be turned on (condition A)
Under charging pMO8T 20, TG I
Oa Notfj is charged to almost vDD. If there is no pMO8T20 for charging, the output high level 1 of TGlOa is lower than VI)D, so pMO8T5p,
Since 6p is not cut enough, inverters 5 and 6
/11 The problem is that through-current flows through and constantly consumes electricity.
However, if you have pMO8T 20 for charging, TG
This problem is solved because the Ioa output high level rises to VDD, where 5p and 6p are almost completely turned off.

(d) When the input signal to 40 a changes from low level 0 to high level vI)D In this case, pMO8T lp changes from on to off state and nMOsT ln changes from off to on state. Shika (R
1 → ur + Rc )] is smaller than the circuit threshold voltage vT5 of the inverter 5 (condition B), the output level of TGloa decreases from the high level side to the low level side, and PMO8T 5p goes from off to on state, nMOsT 5n goes from on to off state, and the output of charging circuit inverter 5 goes from low level side to high level side. As a result,
Since pMO8T20 moves from on to off state, TGl
The output level of oa becomes lower and lower F, and in order to further increase the output level of the charging circuit inverter 5, the charging pMO8T20 is almost completely cut off. in the end,
The outputs of the inverter 1 for the inverter sofa and TGIO are at low level O, and the output of the inverter 5 for the charging circuit is Vine Bell ■DD tonal.

9- As is clear from the above operation, when the input signal No. 1 transitions from low level 0 to high level VDD, the output of input bag impark changes from high level to low level and nMOsT 11 changes from high level to low level. Even if it turns on, charging pMO8T2f+ does not turn off immediately due to propagation delay. Therefore, transiently 20°10a, In
A through current flows through the . In order to reduce the dynamic power consumption caused by this, it is effective to increase the on-resistance of the charging pMO8T 20 so as to reduce the through current. This is also necessary to satisfy condition B. Yes, in the case of (c), the charging pMO8
It is not preferable to make the on-resistance extremely large because the charging capacity of T20 will decrease. Therefore, pMO8 for arm charging
Setting the on-resistance of T20 is a key point in circuit design. Note that condition A is TGIO in normal CMO8,
Even if the high level of is lowered by the threshold voltage, it is larger than vDD/2, and the threshold voltage of inverter 5 is
It can be easily satisfied by setting it slightly lower.

-10= As a result of the specific design of the circuit shown in FIG. 3, the respective values of the channel width to channel length ratio W/L are shown in the table below. The W/L of pMO8T 20 for charging is the through current /j・
In order to reduce the noise, it is set to 115 or lower than the other MO8T. In addition, by circuit simulation, pMO8T2
It has been confirmed that the power consumption due to the transient through current flowing through 0 is in this case several times smaller than the dynamic power consumption due to other causes. It has also been confirmed that the speed performance is equivalent to that of the paired TG. The reason why the speed performance does not deteriorate compared to the P'f type despite the absence of pMO5T is that pMO5
Without T, the capacitance of the source and drain of TG is halved, and the threshold voltage of inverter 6 is set lower than vDIy/2, so the absence of pMO8T reduces the TG specific output oD/2. This is because even if the rising speed deteriorates after exceeding the threshold, it does not affect the delay time much.

Fig. 4 shows an example in which the present invention is applied to a two-man power, one-output single-channel transformer, where 5' is an inverter that also serves as 5 and 6 in Fig. 3, 5'' is a logic (NAND) gate that also serves as 5f, and 7 is a decoder. T
G input terminal, 45 is input terminal to logic cooler 15'', 6
0' is a control terminal of the multiplexer. Figure 4 (a
) is an example in which the inverter for the output buffer is shared with the charging circuit.

In this example, the number of elements is increased by only one pMO8T 20 compared to the case where the device is configured with a normal stray channel type TG. In addition, the input terminals 40', , 4%, 4(1',
It is necessary to use a gate at the front stage of the TG connected to which satisfies the above-mentioned condition B. By the way, if a charging circuit is added, static power will not be consumed.1.7) Conditional power;,T
When the output of G is low level, pMO8T 20 is
It is clear from the operation of the charging circuit that the high level of pMO8T 20 is set manually, but this makes it suitable for logic gate 5' rather than an inverter. Figure 4 6)
is an example using a two-man NAND5" instead of an inverter. However, NAND is an expression based on the assumption that a high level corresponds to a logical value 1 and a low level corresponds to a logical value 0. In this example, the TG's This is possible by directly taking the logic between the output and the human power to 45.In this case, T
Even if the output of G is high level, if the input terminal 45 is at low level, the output of 5" is no inbel and pMO8
T20 was not defeated and TG's high level cover vDD trench could not be used, but nM that constitutes NAND 5''
One of the O8Ts is off, so the TG output is
P that constitutes NAND 5″ due to the low level
NAND even if one of the MO8Ts is not completely turned off
No through current flows through 5''.

Although the n-channel TG has been described in the following, the present invention can also be applied to a p-channel TG composed only of pMO8T. However, the circuit configuration is complementary.

FIG. 5 shows an example of this, and is a circuit corresponding to FIG. 4(b). The specific changes are IM□ST2(
J' and its source is grounded, Figure 4 (b
), a NOR gate 5'' is used instead of the NAND gate 5''.

As explained above, the present invention realizes an n-channel type or p-channel type TG whose output can swing at the power supply voltage from 0 to vDD by adding a number of prime numbers or less.
(Conventionally, there is an n-channel type TG) However, since the CMO8r'-gate located next to the p-channel type TG has insufficient high or low level, it is possible to eliminate the power that was statically consumed due to through current. . Therefore, by applying the present invention to a CMO8 integrated circuit, it is possible to replace the conventionally used pair type TG with an n-channel type or p-channel type with a smaller number of components, which not only reduces chimp noise, but also reduces the TG. The benefits of reduced manpower capacity and reduced wiring delays arise.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of a pair type TG, Figure 2 is a basic circuit diagram of a conventional n-channel type TG, and Figure 3 is a circuit diagram of a four-person output multiplexer to which the invention is applied. The figure is a circuit diagram of another embodiment of the present invention, and FIG. 5 is a circuit diagram of an example in which the present invention is applied to a p-channel type TG. 1, 2.3.4...Inverter for people's sofa, 5...Inverter for charging circuit, 6...Inverter for output buffer,
5' ・・・・・・ Inverter that also serves as 5 and 6, 5
″・・・・・・Two-person power NAND that also serves as 5. 5″′・・・・・・ Two-person power NOR that also serves as 5, 7・
......Inverter for decoder, 8...
...Inverter for control signal inversion, 10...
・Transmiseon Yong Gate (TG), 10a, 10
b, 10c, 10d -・-TG (nMO8T), 1
0Q,](IQ...TG(pMO8T
), lp, 2p, 3p, 4p, 5p. 6p, l0p-pMO8T111, 2n, 3n, 4n,
5n, 6n, 10n...nMO8T,
20・・・・・・・・・pMO8T 120′ for charging
......Charging nMO8T, 35...
... Power supply terminal (vDD is added), 36 ・
...... Ground signal, 4 (1, 40a, 401)
, 40c, 40, 1.4%, 4% -”... Input terminal, 5()... Output terminal, 30...
...Decoder circuit, 60...TG
Control terminal, 601.60b, 6σ...Multiplexer control terminal.

Claims (1)

[Claims] In a logic gate circuit in which a transmission gate is composed of only one type of FET, either an n-channel type or a p-channel type, an input terminal is connected to the output terminal of the transmission gate as means for charging the output terminal of the transmission gate. a logic gate to which one of the logic gates is connected, a FET having a channel shape opposite to that of the FET used for the transmission gate, the gate of which is connected to the output terminal of the logic gate, and the drain of which is connected to the output terminal of the transmission gate. logic gate circuit.