JPS58143569A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS58143569A
JPS58143569A JP2700582A JP2700582A JPS58143569A JP S58143569 A JPS58143569 A JP S58143569A JP 2700582 A JP2700582 A JP 2700582A JP 2700582 A JP2700582 A JP 2700582A JP S58143569 A JPS58143569 A JP S58143569A
Authority
JP
Japan
Prior art keywords
layer
film
ohmic
bonding
ion beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2700582A
Other languages
Japanese (ja)
Inventor
Noburo Yasuda
安田 修朗
Norio Ozawa
小沢 則雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2700582A priority Critical patent/JPS58143569A/en
Publication of JPS58143569A publication Critical patent/JPS58143569A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds

Abstract

PURPOSE:To obtain the III-V group compound semiconductor element having an electrode film with which both ohmic and bonding characteristics are fully satisfied by a method wherein said semiconductor element is comosed of a bonding layer consisting of a basic ohmic layer, having an excellent ohmic contact with the electrode film, and a single crystal metal film which is combinedly used as a wiring for connection to the outside part. CONSTITUTION:Zn, as an ohmic layer, is vacuum-evaporated on the surface of a P type GaP crystal substrate having the density of 10<17>cm<-3> or thereabout. A resistance heating, an electron beam evaporation and the like may be used, but taking into consideration of the combination with the process to be performed subsequently, the vapor-deposition using a cluster ion beam is considered to the the best. Then, an Au film, which will be turned to a bonding layer, is vapor-deposited using the cluster ion beam. When the sample is heat-treated in Ar at 500 deg.C for twenty minutes, a perfect ohmic property can be obtained. When a heat treatment is performed at the lower temperature of 200-300 deg.C for ten minutes, an excellent ohmic property can also be obtained. Also, excellent bondability is obtained and a thermo-press welding and a supersonic bonding can be performed excellently, thereby enabling to have greater tensile strength than that of the bonding performed using an Au wire of 50mum.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は璽−V族化合物半導体素子に係り、特に電極の
構成を改良した半導体素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a V-group compound semiconductor device, and more particularly to a semiconductor device with an improved electrode configuration.

〔発明の技術的背景とその間一点〕[Technical background of the invention and one point in between]

1−V族化合物半導体素子としては発光ダイオード、半
導体レーデ−、センサー、Gthk霧トランゾスタ等が
実用化され、Gaムalcが実用化され       
     つつある。それら素子に共通な問題点として
、化合物半導体面と電極膜とのオー電、り性、並びにそ
の電*1−外部端子へ導くだめの良導電線との鵡ζンf
イング性とがあげられる。前者は素子特性の品質、後者
はディバイス特性の品質に直接関与する。
As 1-V group compound semiconductor elements, light-emitting diodes, semiconductor radars, sensors, GTHK fog transistors, etc. have been put into practical use, and GaM ALC has been put into practical use.
It's coming. Problems common to these devices include electrical conductivity between the compound semiconductor surface and the electrode film, and electrical conductivity between the compound semiconductor surface and the electrode film, as well as the electrical conductivity between the conductive wire and the conductive wire that leads to the external terminal.
Ingredients can be mentioned. The former is directly related to the quality of element characteristics, and the latter is directly related to the quality of device characteristics.

それらの例を最も単純な構造の一つである化合物半導体
発光素子をあげて説明する。m1図に概略WAを示した
が、N llGmAm (又riGm)”)基板1にp
sIl結晶層2t−液相成長法または気相成員法によ)
成長させてP−N接合面全形成し、外部へ露出するN型
、並びI(p整面にそれぞれ亀極3,41に形成し、そ
れら2つ電極間に電圧を印加してP−N*会合面発光さ
せる。第1図の例では、211面よシ主として外部に光
が出ていくが、この逆、即ち、Pfi基板にN型結晶層
をもうけ九構造でも勿論発光し、その場合は主としてN
111面より外部に光が出ていく。発光特性は、基板並
びに結晶層の材質、P−N接合特性等、いわゆる結晶構
造をもったクエハーの特性に大きく依存し、それらが定
まれば、発光特性は必然的に定1りてしまう。しかし、
結晶構造の特性を100襲活かすには、入力を確実に結
晶構造に伝える部分、即ち、結晶構造面上の電極膜と、
その膜と入力端子とを接続する良導電線とが確実に動作
しなければならない、前者の電極膜の役割は、電極膜と
化合物半導体界面とのオーミ、り特性であシ、後者の問
題点は、良導電繻と前記電極膜とが抵抗をもたずK11
合すること、即ち良好な?ディング性を有することであ
る。即ち前者が素子特性、後者がティバイス特性を左右
する。
Examples of these will be explained using a compound semiconductor light emitting device, which has one of the simplest structures. Although the schematic WA is shown in the m1 diagram, the p
sIl crystal layer 2t - by liquid phase growth method or vapor phase growth method)
The entire P-N junction surface is formed by growing the N-type, which is exposed to the outside. *Emit light from the association plane.In the example in Figure 1, light mainly comes out from the 211 plane, but in the opposite case, in other words, if an N-type crystal layer is formed on the Pfi substrate and the 9-structure structure also emits light. is mainly N
Light exits from the 111th surface to the outside. The light emitting characteristics greatly depend on the characteristics of the quartz having a so-called crystal structure, such as the materials of the substrate and the crystal layer, and the P-N junction characteristics, and once these are determined, the light emitting characteristics are necessarily determined. but,
In order to take full advantage of the characteristics of the crystal structure, we need a part that reliably transmits input to the crystal structure, that is, an electrode film on the surface of the crystal structure,
The good conductive wire that connects the film and the input terminal must operate reliably.The role of the former electrode film is the ohmic property between the electrode film and the compound semiconductor interface, and the latter problem is is K11, since the good conductive cotton and the electrode film have no resistance.
Is it good? It is important to have the property of That is, the former influences device characteristics, and the latter influences device characteristics.

オーミック譬性となる金属膜の材質は化合物半導体の材
質にょbsなっているが、文献が多数発行されておシ、
それらの組み合わせは、はぼ公知であゐ。例えばV @
L 、 RIDEOUT着1ムReview @f t
k@Theory and T@chn@logyta
r Qhasio Contaets to Grou
p l1l−V Cornpo−und 8*mi@o
ndIIators’(Solid 5tate El
ec−4reviB、1975 、 V@j 18.p
p541〜550)にくわしく実例があげられるが、例
えばP −GaPに対し゛てはAu−Zml[N−Ga
Pに対してはAu−81膜、P−GaAs K対しては
ムu−Zn、又はAu−In J[I!、 N −Ga
ム自に対してはムw−81膜、Au′−80績等が良い
とされていゐ、但し、ムu−Zn%Au −8i等の成
分比は、GaPとGaAsとで異歇る。
The material of the metal film that causes ohmic error is said to be the material of a compound semiconductor, but many documents have been published.
Those combinations are well known. For example, V @
L, RIDEOUT arrival 1m Review @f t
k@Theory and T@chn@logyta
r Qhasio Contaets to Grou
pl1l-V Cornpo-und 8*mi@o
ndIIators' (Solid 5tate El
ec-4reviB, 1975, V@j 18. p
For example, for P-GaP, Au-Zml [N-Ga
Au-81 film for P, Mu-Zn for P-GaAs K, or Au-In J[I! , N-Ga
It is said that Mu-W-81 film, Au'-80 film, etc. are good for Mu-2, but the component ratios such as Mu-Zn%Au-8i are different between GaP and GaAs.

これら合金膜と化合物半導体界面とをオーミ、り接触さ
せるには、膜を形成後、加熱処理を施す。各々の組合わ
せにょ)最適温度は異なる   ′−5tXぼ404)
℃〜5oo℃の間で10〜30分熱処理をし、膜と界面
との間にある電子的障壁を、各々の構成元素を相互に拡
散はせることに禮f9取り除き、オーミ、り接触をなさ
しめゐ。
In order to bring these alloy films into ohmic contact with the compound semiconductor interface, heat treatment is performed after the films are formed. The optimum temperature for each combination is different.'-5tX404)
Heat treatment is performed for 10 to 30 minutes at a temperature between ℃ and 50℃ to remove the electronic barrier between the film and the interface, allowing the constituent elements to mutually diffuse, and making ohmic contact. Shumei.

次にこの金属膜面上に、良導電線、例えばAu1i又は
At線f N y fインクすることになるのだが、こ
の金属膜面上にはほとんど皆無といってよい程にノンデ
ィングできない。その理由Ifi膜の表面に、基板の構
成元素であるGa元素が堆積しでGa層を作ってしまう
からである。Au1m!又はkt綜は単体のAuMまた
はAjJ[には容易にノンディングできるか、Ga層に
は絶対にボンディングできない。この原因は前述のオー
ミ、り特性をだすための熱処理工程にある。即ち加熱に
より、gの組成7C素は化合物半導体内へ、化合物半導
体丸木は膜内へ移動する。前者は結晶内への拡散。
Next, a highly conductive wire, such as an Au1i or At line fN y f, is inked on the surface of this metal film, but it is impossible to ink the surface of this metal film to the extent that there is almost no ink on the surface of this metal film. The reason for this is that Ga element, which is a constituent element of the substrate, is deposited on the surface of the Ifi film to form a Ga layer. Au1m! Alternatively, the kt helix can be easily non-bonded to a single AuM or AjJ[, or it cannot be bonded to a Ga layer at all. The cause of this is the heat treatment process for producing the ohmic and radial characteristics mentioned above. That is, by heating, the 7C element of g moves into the compound semiconductor, and the compound semiconductor log moves into the film. The former is diffusion into the crystal.

佐者II′i微結晶が宇る〈固った薄膜内への拡散であ
るため、拡散速度は2桁以上彼者の方が早い。
The diffusion rate is more than two orders of magnitude faster in the case of the second case because the diffusion takes place within a solid thin film.

前者が結晶界面の近傍に限られ、オーミック特性に寄与
するが、後者の現象は前述の如く、゛換向にGa層全全
堆積せることになりがンディング工程にとって好ましく
ない現象である。又Ga元素のAu、 At内移動速度
が早いため、化合物半導体デバイスにとって早急に解決
すべき問題でおる。
The former phenomenon is limited to the vicinity of the crystal interface and contributes to the ohmic characteristics, but the latter phenomenon, as described above, is an unfavorable phenomenon for the bonding process because it causes the entire Ga layer to be deposited. Furthermore, since the Ga element moves quickly in Au and At, this is a problem that needs to be solved as soon as possible for compound semiconductor devices.

このようにオーミ、り性とノンディング性とを両立させ
るKは、Ga元素の移動を防がねばならない、その最も
効果的な手法は金属膜の中間にバリア層をもうけること
である。即ち、化合物半導体面上に前述のオーミ、り用
合金展を形成し、その上にバリア層、引き続きデンディ
ンダ用ム1又はムを膜を形成する、多層の積層型電極膜
構造とすることである。このバリア層は、熱処暑中のG
a元素の移動を止める働きをさせるため、膜の材質、膜
の厚み等に十分注意しなければならない。本発明者らは
TaMが最適というデータをもっている(411i1.
 N56−12017ta)。
K, which achieves both ohmic properties and non-damping properties, must prevent the migration of Ga elements, and the most effective method for this is to provide a barrier layer in the middle of the metal film. That is, the above-mentioned ohmic and dielectric alloy film is formed on the compound semiconductor surface, and a barrier layer is formed thereon, followed by a dendritic film and a multi-layered electrode film structure. . This barrier layer is
In order to function to stop the movement of the a element, careful attention must be paid to the material of the film, the thickness of the film, etc. The present inventors have data that TaM is optimal (411i1.
N56-12017ta).

しかし乍ら、量産化し′#−楊合、コストを安くするに
は、多層膜形成の工程、%Kra@の形成ニーがない方
が望オしい。
However, in order to mass-produce and reduce costs, it is preferable to eliminate the process of forming a multilayer film and the need to form %Kra@.

〔発明の目的〕[Purpose of the invention]

本発明は、バリア層門形成せずにオーミ、り特性とIン
ディンダ特性との両者を十分満足させる電極膜を備え九
履−■族化合物半導体装置を提供するものである。
The present invention provides a 9-III compound semiconductor device having an electrode film that satisfactorily satisfies both ohmic and indinder characteristics without forming a barrier layer.

〔発明の概要〕[Summary of the invention]

不発IjlFi、電極膜を良好なオー電、り接触を示す
下地オー電、り層と外部El!続するための配at兼ね
え一ンダインダ層とから構成し、かつその271477
層を単結晶金属膜として、Ga勢の移動速jI!を、従
来の膜に比べ17100以下に押えこみ、Ga元素の移
動葡極端に遅くして電極層面へのGa元素の堆積を発生
させない様にし友ものである。
Unexploded IjlFi, the electrode film shows good electrical contact, the underlying electrical contact, and the external El! 271477
Assuming that the layer is a single crystal metal film, the moving speed of the Ga force jI! is suppressed to 17,100 or less compared to conventional films, and the movement of Ga elements is extremely slowed down to prevent accumulation of Ga elements on the electrode layer surface.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電極膜の表面部分のがンデイング層と
して単結晶金属膜を用いることにより、その表面へのG
&元素の移動、堆積を抑えて良好なIンrイング性を確
保することができる。
According to the present invention, by using a single crystal metal film as a bonding layer on the surface portion of the electrode film, G
& It is possible to suppress the migration and deposition of elements and ensure good induration properties.

また本発明によれば、単結晶金属膜を用いることにより
、電極抵抗の減少と歩留ル向上が図られる。前者は従来
の微結晶膜に比べ40慢をも抵抗を減少させることが出
来、入出力の損失を少なくさせる。後者としては膜形成
時の均−性肉上と、微細加工時の均一性向上が特に−著
であゐ。更Kがンデインダ層を単結晶化したためにオー
電、り特性をだすためのプロセスも簡略化できる。これ
はオー電、り層が化合物半導体結晶と配線用がンデイン
グ層結晶とにはさまれたため、オー電、り層の元素の拡
散が半導体結晶の方へ向く丸めであ)、オー電、り全熱
処理が、低い温度、短かい時間で可能となり、!ロセス
短縮に大きく貢献する。
Further, according to the present invention, by using a single crystal metal film, it is possible to reduce electrode resistance and improve yield. The former can reduce resistance by as much as 40% compared to conventional microcrystalline films, reducing input/output losses. As for the latter, improvements in uniformity during film formation and uniformity during microfabrication are particularly remarkable. Furthermore, since the binder layer is made into a single crystal, the process for producing electrical and electrical characteristics can be simplified. This is because the OLED layer is sandwiched between the compound semiconductor crystal and the interconnection layer crystal, so the diffusion of elements in the OLED layer is rounded toward the semiconductor crystal. Complete heat treatment is possible at low temperatures and in a short time! This greatly contributes to process reduction.

〔発明の実施例〕[Embodiments of the invention]

実施例−1 10”cxs−’台の濃度をもつP型GaP結晶基板面
に、オー電、り層としてznを真空蒸着させる。
Example 1 Zn is vacuum-deposited as an electrolytic layer on the surface of a P-type GaP crystal substrate having a concentration on the order of 10"cxs-'.

この手段は抵抗加熱壕九は電子ビーム、**等で良いが
、次の工程との組み合わせから、クラスターイオンビー
ムによゐ蒸着が最も良い。次に272477層となるA
m膜tクラスターイオンビームによ〉蒸着させる。この
試料を5oot、20分間Ar中で熱処理すると、完全
なオーミック性が得られる。よル低温で200〜300
℃、10分の熱処理でも良好なオー電、り性が得られる
。又、Iンデイグ性も熱圧着や超音波−ンディグ法いず
れも良好であり、50μ解のA+a@でゲンデングした
場合100gr以上の引り張りIJ1度をもりそいる。
Although this method may be an electron beam, **, etc. for resistance heating trenches, vapor deposition using a cluster ion beam is best in combination with the next step. Next, A becomes the 272477th layer.
Deposited by cluster ion beam. When this sample is heat treated in Ar for 5oots for 20 minutes, perfect ohmic properties are obtained. 200-300 at low temperature
Good electrical resistance can be obtained even after heat treatment at ℃ for 10 minutes. In addition, the I-digging property is good using both thermocompression bonding and ultrasonic-digging methods, and when it is graded with A+a@ of 50μ solution, it has a tensile IJ of 1 degree or more of 100gr.

A−膜を通常の抵抗加熱、電子ビーム蒸着で蒸着形成し
九場合には、引り張り強度tf20gr以下であり、O
grs即ち、ちょっと触れただけで−がとれてしオうサ
ンプルも多く発生している。Zm及びAuの膜厚は、P
層の不純物濃度、熱処運温f、その処理時間によッテ異
’l J) カ、5 X 10”cus−’ (Dg 
度1500℃、20分という条件下では%Z!1111
厚は5001〜1000X% A1膜厚は3000〜5
0001で十分である。
When the A-film is deposited by ordinary resistance heating or electron beam evaporation, the tensile strength tf is 20 gr or less, and the O
In other words, there are many samples in which the - mark comes off with just a slight touch. The film thickness of Zm and Au is P
It varies depending on the impurity concentration of the layer, the heat treatment temperature f, and the treatment time.
Under the conditions of 1500℃ and 20 minutes, %Z! 1111
Thickness is 5001~1000X% A1 film thickness is 3000~5
0001 is sufficient.

実施例−2 実施例−1と1−)九〈同じGaP基′板に、同一手段
でwlを形成し、熱処理し、Iンディ゛ングtした。但
し、Au1llとムーーとを各々ムilIとkA線に変
えてあゐ。又、クラスターイオンビームの条件−変見九
が、試料のがンディンダ臀性は実施例−1と同じ結果が
得られた。膜厚もほぼ同じであ為。
Example 2 Examples 1 and 1) 9. wl was formed on the same GaP substrate by the same means, heat treated, and indexed. However, Au1ll and Mu are changed to Muil and kA lines, respectively. Furthermore, under the conditions of the cluster ion beam, the same results as in Example 1 were obtained regarding the bending and buttock properties of the sample. The film thickness is also almost the same.

実施例−3 10”cs−”台の濃度をもつN製GaP結晶基板面に
対しては、オー電、り層としてZn膜のかわ)にSl膜
又はG噛膜をクラスターイオンビームによ勤形威させ、
−ンデインダ層としてA−膜又はムtHを岡じ〈タテス
ターイオンビームで形成させ為、そ0115oo℃、j
lo分間Ar中で熱処理をして完全にオーミック性をと
り、?ンディグ善性を評領しえ、実施例−1とほぼ同じ
結果が得られ九が、膜の厚さの最適値が少し異なる。
Example 3 For the N GaP crystal substrate surface with a concentration on the order of 10"cs-", a Sl film or a G film was applied as an electrical layer (instead of a Zn film) using a cluster ion beam. Make an appearance,
- To form the A-film or MutH as the binder layer using an ion beam at 0115°C,
After heat treatment in Ar for 10 minutes, the ohmic property is completely removed. Although the film thickness was evaluated as being good and almost the same results as in Example 1 were obtained, the optimum value of the film thickness was slightly different.

all又はG@膜は200X〜6001にあり、A%I
又はムtMは3000〜50001−t”ある。
all or G@ membranes are at 200X~6001, A%I
Or MutM is 3000 to 50001-t''.

lI論例−4 10’31” 台0’m1ll t’4 りP If 
GaAm 、又u N 型Gaps結晶において4同じ
効果が得ら・れた。即ちp @ GaAs ilK対し
テt;j Z m膜とAu[又はht 61タライスタ
ーイオンピー五によ)積層形成させることで、いずれも
゛オーオワり並びに−ンディフグ0両特性を満足させる
ことかで11え。
lI example-4 10'31" machine 0'm1ll t'4 riP If
The same effect was obtained in GaAm and uN type Gaps crystals. That is, by forming a laminate of a Tet;j Z m film and Au [or ht 61 Talistar ion P5] on p @ GaAs ilK, it is possible to satisfy both the ``O'' and ``Ndiff'' characteristics. 11.

次に本発明によυ嵐好な結果が得られる理由を以下に述
べる。まず、クラスターイオンビームの概略図を鎮2図
に示す。このビーム形成法は公知であるから簡単に説明
すると、基板21に蒸発源22を対向させる。基板21
とはPN接合が形成され友GaP を九はGaム−基板
であ夛、蒸発源22とkiZ n + 81 * G 
@、ムurkL等の単体金属蒸発源である。積層とする
場合には蒸発源22を回転勢により交換すれば嵐い、蒸
発源21は耐熱性ルッ723とヒーター24とからなシ
、各々の金属を融解し、蒸発温度迄加熱することができ
る。ルッ121には噴射ノズル21があシ、そのノズル
2Iかも蒸発金属がとびだす。
Next, the reason why good results can be obtained by the present invention will be described below. First, a schematic diagram of the cluster ion beam is shown in Figure 2. Since this beam forming method is well known, it will be briefly explained. An evaporation source 22 is placed opposite to a substrate 21. Substrate 21
A PN junction is formed with a GaP substrate, an evaporation source 22 and a kiZ n + 81 * G
It is a single metal evaporation source such as @, MuurkL, etc. In the case of a laminated structure, the evaporation source 21 can be easily replaced by rotating the evaporation source 22. The evaporation source 21 consists of a heat-resistant metal 723 and a heater 24, and each metal can be melted and heated to the evaporation temperature. . There is an injection nozzle 21 in the hole 121, and evaporated metal comes out from the nozzle 2I as well.

そのノズルの桂状と、大ツー内圧力と、周辺の圧力とか
ら蒸発金属を断熱膨張させることができ、中性の原子が
数百個ゆる〈固り友クラスター状原子団の蒸気とするこ
とができる。その原子団が基板21に到達する迄にイオ
ン化用電子放出フィラメント26で、原子団中の約1個
O原子をイオン化し、加速電極J1でそれらイオン化し
九原子団、即ちタラスターイオンを加速し、基板11f
Cg央させ、基板面上に膜21を形威させる。このタラ
スターイオンビーム蒸着法の曹長は、条件をうまく選択
すれば、単結晶膜を形成で1i為ことであゐ。即ち、基
板の材質、面方位、温度、曽熟曹等、蒸発源物質の純度
、蒸発温度等、イオン化用フィラメント電流、加速電圧
、真空度等の因子t5t<制御すればよい。
The evaporated metal can be adiabatically expanded due to the Katsura shape of the nozzle, the internal pressure of the large tube, and the surrounding pressure, and several hundred neutral atoms form a cluster-like atomic group vapor. I can do it. Before the atomic group reaches the substrate 21, the ionizing electron emitting filament 26 ionizes about one O atom in the atomic group, and the accelerating electrode J1 ionizes them to accelerate nine atomic groups, that is, Tarastar ions. , substrate 11f
Cg center to form a film 21 on the substrate surface. The advantage of this Tarastar ion beam evaporation method is that if the conditions are properly selected, it is possible to form a single crystal film in 1i. That is, factors such as the material of the substrate, the surface orientation, the temperature, the purity of the evaporation source material, the evaporation temperature, the ionization filament current, the accelerating voltage, the degree of vacuum, etc. may be controlled.

本発明の実施例の場合、オーミ、り特性を加味し、なお
かつ、五1又はAj膜を結晶化するために、Zll、8
1.Ga轡の金属膜を薄く形成後、その面上に直ちgA
w11九はムL1Mを成長させるので、現象が複雑にt
〉、各々の因子を別個にとり扱うことが出*ない。しか
し実施例の平均的な数値としては、GaP★九はG1ム
S基板を注意深く化学的、物理的に洗浄し、I X 1
0−’Torr以下の真空中、300℃近辺に加熱し、
Zn又は81又はG・膜をイオン化用として0〜100
mA、加速電圧として0〜S kVt印加して、クラス
ターイオンビーム化してそれら基板面に形成し、真空を
破らすに直ちにルツがを交換して、ム輸又はムL膜を形
威す石、この条件は、基板温度、真空度を一定にしてお
り、イオン化用フィラメントには15001A、加速電
圧は8 kVを印加した。
In the case of the embodiment of the present invention, Zll, 8 is added to take into account the ohmic and ri characteristics, and in order to crystallize the 51 or Aj film.
1. After forming a thin metal film of Ga, immediately apply Ga on the surface.
Since w119 causes muL1M to grow, the phenomenon becomes complicated.
>, it is not possible to treat each factor separately. However, as an average value in the example, GaP★9 requires careful chemical and physical cleaning of the G1S substrate, and I
Heating to around 300°C in a vacuum of 0-' Torr or less,
0 to 100 for ionizing Zn or 81 or G membrane
mA and 0 to S kVt as an accelerating voltage are applied to form a cluster ion beam on the substrate surface, and immediately after the vacuum is broken, the roots are replaced to form a MU or MU L film. The conditions were such that the substrate temperature and degree of vacuum were constant, 15001 A was applied to the ionization filament, and an accelerating voltage of 8 kV was applied.

このサンダルのオーオ、り性、−ンデインダ性は前述し
たが、膜のみの特性はオーき、り特性を得る丸めの加熱
処sをする前に、基板から膜のみを剥して、X線で調べ
た。基板自体の結晶の転写、オーミ、り用膜の影響等を
完全KM去できないので、クラスターイオンビームで形
成したku又はムtlIと、通常の抵抗加熱又は電子ビ
ーム蒸着で形成したム謳又はAA膜との比較データが最
も信頼がおける。その結果、従来法による膜は完全なる
微結晶体の集合でTon、単結晶の信号は全態検出て自
ず結晶粒界が膜内に無限に存在することが−−する。こ
れに対しクラスターイオンC−五による膜は、単結晶/
9−一/がきれいに現われ、微結晶信号はほとんどなく
、膜内には結晶粒界がほとんど存在しないと言える。但
し、観察視野を羨えると結晶の方位がいくぶん変化すゐ
丸め、完全なる無欠陥結晶膜には成長していない。しか
し、−ンデイング特性の改善には十分の能力を発揮して
いる。これは、ム鴇又はムを膜が結晶化し、結晶粒界が
極端に少なくな−)九結釆、Qaの移動が少なくなっ九
丸めである。膜内とバルク内とで拡散移動速度が2桁以
上も異なるのは、結晶粒界の存在が2桁以上も異なるえ
めであ)、移動は最も動きやすい結晶粒界にて発生する
からである。
As mentioned above, the properties of this sandal are opaque, resilient, and indestructible, but the properties of the film alone are not. Ta. Since it is not possible to completely eliminate the influence of the crystal transfer, ohmic, and reflective films on the substrate itself, we use KU or MTLI formed by cluster ion beam and MUT or AA film formed by ordinary resistance heating or electron beam evaporation. The most reliable data is the comparison with As a result, the film produced by the conventional method is a complete collection of microcrystals, and a signal from a single crystal can be detected in its entirety, and an infinite number of grain boundaries naturally exist within the film. On the other hand, the film made of cluster ion C-5 is single crystal/
9-1/ appears clearly, there is almost no microcrystalline signal, and it can be said that there are almost no grain boundaries in the film. However, when viewing the field of view, the orientation of the crystal changes somewhat and becomes rounded, and a completely defect-free crystal film does not grow. However, it shows sufficient ability to improve the bending characteristics. This is because the film is crystallized, the grain boundaries are extremely small, and the movement of Qa is reduced. The reason why the rate of diffusion movement in the film and the bulk differs by more than two orders of magnitude is because the presence of grain boundaries differs by more than two orders of magnitude), and migration occurs at the grain boundaries where they are most mobile. .

なお、以上ではGaP%GaA−基板に対しての実施例
しか述べなか−)九が、他の化合物半導体。
In addition, in the above, only examples for GaP%GaA-substrates have been described.9) Other compound semiconductors.

例えば、  ImP%Iamb%GaN等又は混合化合
物半導体、例えば、GaAjム−1f mGa AjA
s 尋K 4遍用でき、オーミ、り層としても、8m、
Iれ、Ag、B・等の膜も当然利用できる。又、これら
展は単体である必要性は准く、全知の合金膜でもその機
能は十分に果皮す。又一本発明はモノリシック型のGm
As−IC,光IC等にも十分に活用できる。
For example, ImP%Iamb%GaN etc. or a mixed compound semiconductor, for example GaAjmu-1f mGaAjA
s fathom K Can be used for 4 times, can also be used as an ohmi, layer, 8m,
Of course, films such as I, Ag, B, etc. can also be used. In addition, it is not necessary for these layers to be a single substance, and even an omniscient alloy film can sufficiently function as a pericarp. Another aspect of the present invention is a monolithic Gm
It can also be fully utilized for As-IC, optical IC, etc.

これらの場合、上述の一ンナイング層が配線層の役目を
兼ねるが、この配線層が単結晶化により低抵抗化すゐた
め優れたデバイス特性が得られ石。また単結晶化膜を得
る方法として、クラスターイオンビーム蒸着法の他、分
子線エピタキシー法や超高真空中のイオン蒸着法などを
利用することもできる。
In these cases, the above-mentioned one-inning layer also serves as a wiring layer, and this wiring layer has a low resistance due to single crystallization, so excellent device characteristics can be obtained. Further, as a method for obtaining a single crystallized film, in addition to the cluster ion beam evaporation method, molecular beam epitaxy method, ion evaporation method in ultra-high vacuum, etc. can also be used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は化合物半導体発光素子の一例を示す図、第2図
は本発明の実施例で用いたクラスターイオンビーム蒸着
法の概念図である。 J・・・Ni1GaA易(またはGaP)基板、2・・
・P型結晶層、3,4・・・電極。 出願人代聰人  弁理士 鈴 江 武 彦11 第2図 293−
FIG. 1 is a diagram showing an example of a compound semiconductor light emitting device, and FIG. 2 is a conceptual diagram of a cluster ion beam evaporation method used in an example of the present invention. J...Ni1GaA easy (or GaP) substrate, 2...
- P-type crystal layer, 3, 4... electrode. Patent attorney Suzue Takehiko 11 Figure 2 293-

Claims (4)

【特許請求の範囲】[Claims] (1)f’Nli合を有する厘−V族化合物半導体素子
において、前記PN接合を構成するPGM層並びにNl
1層の1極を、良好なオー電、り接触を示すオー電、り
層と外1sK*合させる九めの配lil會兼ねたIンデ
イング層とから構成し、かつ該−ンデインダ層を単結晶
金属膜で構成した事を特徴とする半導体素子。
(1) In a Rin-V group compound semiconductor device having f'Nli junction, the PGM layer and Nl constituting the PN junction
One pole of one layer is composed of an electrical conductor layer showing good electrical contact and an inducting layer which also serves as a ninth interconnection layer to be combined with the outer conductor layer, and the conductor layer is made of a single layer. A semiconductor element characterized by being composed of a crystalline metal film.
(2)  単結晶金・膜層はクラスターイオンビー^蒸
着法で形成したものである特許請求の範囲第1項記載の
半導体素子。
(2) The semiconductor device according to claim 1, wherein the single-crystal gold film layer is formed by a cluster ion beam deposition method.
(3)  オー電、り層はZm 、Gm ral t8
m * I@*ムC1B・から遍ばれた単体金属または
合金層である特許請求の範囲第1項記載の半導体素子。
(3) Oden, rear layer is Zm, Gm ral t8
The semiconductor device according to claim 1, which is a single metal or alloy layer consisting of m*I@*muC1B.
(4)  単結晶金属膜はAiI又はムtである特許請
求の範囲第1項記載の半導体素子。
(4) The semiconductor device according to claim 1, wherein the single crystal metal film is AiI or Mut.
JP2700582A 1982-02-22 1982-02-22 Semiconductor element Pending JPS58143569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2700582A JPS58143569A (en) 1982-02-22 1982-02-22 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2700582A JPS58143569A (en) 1982-02-22 1982-02-22 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS58143569A true JPS58143569A (en) 1983-08-26

Family

ID=12209001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2700582A Pending JPS58143569A (en) 1982-02-22 1982-02-22 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS58143569A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223185A (en) * 1984-04-19 1985-11-07 Nec Corp Manufacture of semiconductor laser
JPS6372156A (en) * 1986-09-16 1988-04-01 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60223185A (en) * 1984-04-19 1985-11-07 Nec Corp Manufacture of semiconductor laser
JPS6372156A (en) * 1986-09-16 1988-04-01 Hitachi Ltd Semiconductor device

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