JPS58141559A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To interrupt a conductor pattern positively, and to operate a redundant circuit by implanting the ions of insulating impurity atoms or impurity atoms giving conductivity into a substrate region or a semiconductor layer from the recessed section of a protective film. CONSTITUTION:A thin SiO2 film 12 is formed onto a p type silicon semiconductor substrate 11 through thermal oxidation treatment. A first resist pattern 13 in which a section corresponding to a diffusion-layer forming prearranged section is bored is formed. Phosphorus ions are implanted into the substrate 11 under predetermined conditions while using the resist pattern 13 as a mask, and n<+> type diffusion layers (conductor patterns) 141, 142 are formed. The resist pattern 13 is removed, and the protective film 15 is formed onto the SiO2 film 12. A second resist pattern is shaped onto the protective film 15, and the protective film 15 and the SiO2 film 12 are removed through etching in succession. A thin oxide film 16 is formed onto the surface being exposed of the substrate 11 through thermal oxidation treatment.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.

[The technical burden of invention is]

As is well known, the degree of integration of semiconductor devices, especially integrated circuits, has been rapidly increasing over the past 23 years.

Since such high integration is largely due to the miniaturization of elements, it is no exaggeration to say that microfabrication technology determines the degree of integration. On the other hand, as processing becomes finer, the density of processing defects or defects increases significantly, resulting in a decrease in yield. For this reason, when manufacturing a semiconductor device, a spare memory is formed in addition to the main circuit in advance to save the main circuit, and when a defective pin is discovered during a pass/fail test, a redundant circuit is used to store the spare memory. A method of converting is used. Note that this step 1 is performed by incorporating some type of fuse into a predetermined position of the semiconductor device, and operating a redundant circuit by cutting or connecting this fuse.

The semiconductor device equipped with the above-mentioned spare memory is conventionally manufactured as shown in FIGS.

First, an oxide film 2 is formed on an n-type semiconductor substrate 1, for example. Continuing with "C1, an undoped polycrystalline silicon layer (not shown) is formed on this oxide film 2. Next, this silicon layer is patterned to form a silicon pattern in which the area to be irradiated with the laser beam is narrow. After that, a resist film is applied on the silicon pattern, and photolithography is performed to
A resist pattern 3 is formed in which a portion where a low resistance diffusion region is to be formed is opened. Next, using this resist pattern 3 as a mask, an n-type impurity such as phosphorus is ion-implanted into a low-resistance nl-type diffusion region 4I, one of which is connected to a spare memory (not shown).

form 42. At this time, the silicon pattern portion of the resist pattern 3* which is not ion-implanted is a 1ntrinsic poly Si layer (I layer) 5 of 109Q or more.
becomes. In such a semiconductor device, when the main circuit operates normally, the n-type diffusion regions '1+'l are used in an electrically isolated state.

On the other hand, when a defect is confirmed, after removing the resist pattern 3, a pulsed laser is applied to the n-type diffusion region 4. ,4. The layer 5 is made into a low resistance (approximately 103Z) conductor region 6 by irradiating the I r@ 5 between the n+ type diffusion regions 4. ．． 4. By short-circuiting, a redundant circuit is activated and a defective semiconductor device is relieved.

Note that the method of operating a redundant circuit by changing a high resistance region (layer 1) to a low resistance region in this way is as follows.
sumaMinato et of”H
凰gh CMO84K 5tatic RAM
”I 8SCCDigest of 'l'echn
ical paper8, p 14-15Feb,
It is known since 1981.

[Problems with back gshajutsu]

However, in the above-described method, localized heat treatment is performed at high temperature using a 1/- laser, which may cause defects in the substrate. In addition, in the method described above, a pulsed laser beam is applied to one layer 5 of high resistance (1099 or more) made of the same material between the n-type diffusion regions 41+'2 of ten low resistance made of an undoped polycrystalline silicon layer. 1 and the n+ type diffusion region 4□ by changing to a region of low resistance (approximately 1030Ω).

Since this is a method in which 42 short circuits are performed, the length of each layer 5 must be maintained at a constant interval in advance so that short circuits do not easily occur during the normal heat treatment process, which reduces the degree of lateral integration. There was a problem.

On the other hand, if the length of the first layer 5 is too long, the acceleration voltage of the pulsed laser irradiated at the time of the above-mentioned short circuit must be increased, which may have an adverse thermal effect on the surrounding elements, or the short circuit may be insufficient and redundant. There were drawbacks such as the circuit not working.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reliably intermittent conductor patterns without reducing the degree of lateral integration or having adverse thermal effects.
The purpose is to

[Summary of the invention]

The present invention enables the operation of a redundant circuit formed in a semiconductor device by using conductors that are connected to or separated from each other on the surface of a semiconductor substrate or at both ends of a semiconductor layer, without using a high-energy beam such as a pulsed laser as in the past. After forming a pattern and forming a peritoneal protective film having recesses in the portions corresponding to the discontinuous portions of the conductor pattern in parentheses, impurity atoms or conductive materials are insulated from the recesses of the protective film to the base plate region or semiconductor layer. Is it possible to ensure reliable conduction by ion-implanting impurity atoms that give The main idea is to operate a redundant circuit by intermittent body patterns.

[Embodiments of the invention]

The present invention is illustrated in FIG. 2 (at, (bl, M3) (al,
(hl, Figure 4(a), (b) and Figure 5(a)
, (t) 3. Example 1 [11] First, a thin 5io2 film 12 was formed on an n-type silicon semiconductor M-&JJ soil by thermal oxidation treatment. Subsequently, a first resist pattern 13 having holes corresponding to the portions where the diffusion layer was to be formed was formed by photolithography. Next, using the cyst pattern 13 as a mask, phosphorus is ion-implanted into the substrate 11 under predetermined conditions to form an n+
Mold diffusion layer (conductor pattern) 14. ．． 142 (as shown in FIG. 2).
4. One of the two is connected to a spare memory (not shown).

[11] Next, the resist pattern J3 was removed.

Subsequently, a protective film 15 was formed on the S I 02 iI°'112 soil. Next, the VH Vli layer 14. is applied to this preserved kidney soil. ．． 14. After forming a resist pattern (a20=+ +/not shown in the figure) with holes corresponding to the dialysis areas in between, the urinary protective membranes R5, SIO, and C12 are sequentially etched using this resist pattern as a mask. Removed. Thereafter, a thin oxide film 16 was formed on the exposed surface of the substrate 11 by thermal oxidation treatment. As a result,
A plurality of four portions 17 are formed between this thin oxide film J6 and the retention film 15. Thereafter, if it is confirmed that a half circuit has aged in a semiconductor device with such a structure by testing the function or performance of the device, the J.
) Diffusion layer 24 corresponding to the defective location. ．． 14. Phosphorus is applied to the substrate area between 2 from the recess 12 corresponding to this substrate area.
An n-type diffusion region 18 was formed by AP ion implantation and annealing under the condition of [-' (see FIG. 2(i) 1).
. As a result, n+ type diffusion 1 is formed through this diffusion region 18.
Ro 14. ．． 14. was shorted and the redundant circuit was activated. In addition, if the main circuit is working properly, it can be used.

According to the present invention, when the redundant circuit is operated, the low resistance diffusion region 4 made of an undoped polycrystalline silicon layer is used as in the conventional method. ．． High resistance l made of the same material between 42
By irradiating 1i5 with a pulse 1/- size and changing the nuclear Ir threat 5 into a low-resistance conductor region 6, the diffusion region'I
Instead of short-circuiting y' 2, both diffusion layers 1i14I 914 are implanted by ion implantation of phosphorus into the substrate region between the diffusion layers "l" and 14□ formed on the substrate 11.
Since this method operates a redundant circuit by short-circuiting between □, there is no need to provide a margin in the lateral direction of the I layer 5 in consideration of the normal heat treatment process, as in the conventional method. Therefore, the degree of lateral integration can be improved compared to the conventional case. Moreover, for the same reason, the diffusion M 14 r + l 't is placed close to the 141.14. In addition to being able to narrow the board area between, this basic P! Since the four parts 17 are formed on the area, there is no adverse thermal effect due to local heating as in 11 (extended to the gutter) J 4+ , J 4□
The redundant circuit can be activated by shorting the circuit.

Example 2 Li) First, an RL type diffusion layer (conductor bar main) 19 is formed on the surface of a p-type green semiconductor substrate 1 by a conventional method.
was formed. After forming 1 m of undoped polycrystalline silicon (as shown in the figure) on the entire surface, patterning is performed to form 111 diffusion M 191 and -
A semiconductor layer 20 made of polycrystalline polycrystalline material was formed. A hole was slightly opened in the S 1 02 film 21 corresponding to a part of the Chihiro body layer 20 on which the Bi□ film 21 was formed. Then,
N-type impurity-doped polycrystalline silicon layer (not shown) on the entire surface
After that, a conductor pattern 22 made of an n-type impurity-doped crystal was formed by patterning to contact the semiconductor 7420 through the opening (as shown in FIG. 3(a)).
. Note that the conductor pattern 22 or the front 6 self-diffusion layer I9
One of them is connected to a spare memory (not shown).

[11] Next, a protective film 23 was formed on the entire surface. Subsequently, a fourth resist pattern (not shown) in which a portion corresponding to the semiconductor layer 20 is opened is formed on the protective film 23-A, and then this resist pattern is used to form the protective film 23-1.
Then, a thin oxide film 24 was formed on the conductor pattern 22 to be used as a sieve by performing a thermal oxidation treatment. As a result, a plurality of four portions 25 are formed in this thin oxide 1@24 and protection H@23.

After this, when confirming that the main circuit is defective, O↑, Example 1
Similarly, phosphorus is selectively added to the semiconductor In 2θ ((-1 corresponding to the semiconductor layer 20ζ) between the diffusion I-19 and the conductor pattern 22 corresponding to the defective part 26) under predetermined conditions. ion implantation and annealing to form a low-resistance semiconductor layer 20' (see Figure 4). As a result, the diffusion 1-19 and the conductive pattern 22 are short-circuited via this semiconductor layer 20'. , the redundant circuit was activated.

In Example 2, the diffusion layer 19 formed on the substrate surface and the base 41i! 11 We will discuss the case of a short circuit with the conductive layer 20 formed through the semiconductor layer 20 (and the rare pattern 22). Impurities formed up and down in the direction 1・゛−
Conductive patterns made of polycrystalline polycrystals may be interconnected.

In addition, in Example 2, an n-type impurity Lugdove polycrystalline silicon layer was used as the conductive pattern material;
94, impurity-doped single crystal silicon 117 and 1
') - Rufus silicon layer or metal layer 11-11
-11・It may be a curved edge.

Embodiment 3 [1] First, phosphorus is selectively implanted into a silicon semiconductor substrate 110 of p-1 to 110, and activated, and a narrow n-type is formed in the area corresponding to the area where the oxide film is to be formed. 27 was formed (Figure 4 Ca1 Figure 7).
J.N. Note that one end of this diffusion region 27 is connected to a spare memory (not shown).

[11] Next, the entire surface (this protection H2g was cut into the shape 11y.-
) Based on this Hojin 8-28, oxide film type iV + constant HB
After forming a fifth resist pattern with openings in corresponding portions, the protective film 28 was removed by etching using this resist pattern as a mask.

Next, a thin oxide film 29 was formed on the protruding diffusion region 27 by thermal oxidation treatment. As a result, a recess 30 was formed between the thin oxide film 29 and the security film 28.

After this, when a failure or +t in the main circuit is confirmed, a desired part of the diffusion region 27 corresponding to the defective part is irradiated with oxygen ions from the recess 30, annealed and insulated, and an oxide film 3) is formed. The formed oxide film 31 (as shown in FIG. 4 (b1)) was ignited, and the diffusion region 27 was separated into two, creating a pile of redundant circuits.

[Example 4J] First, on a pQ silicon semiconductor substrate (ν1), a S'0211' space 32 and a square body pattern 33 made of a [1 (' type impurity doped polycrystal) with a narrow central part were formed by a conventional method. The magnetic conductive pattern 33 was formed sequentially (as shown in FIG. A protection film 28 having an aperture [3] and a hot oxide film 29 provided in the aperture were successively formed.In this case, when a defect in the main circuit was confirmed, as in Example 3, a protective film 28 was formed. injection of,
By annealing, the desired region of the conductor pattern 33 corresponding to the defective cross section was insulated into oxide 34 (as shown in 51st (b)). As a result, the oxide film 34 was sandwiched between The conductor pattern 33 was separated into two, and a redundant circuit was activated.

In Examples 1 and 2, phosphorus was used as the impurity atom when ions were implanted into the substrate region or the semiconductor layer to make it n-type, but the impurity atoms are not limited to this, and arsenic may also be used. ,
In addition, boron can be used to make the material p-type. Similarly, in Examples 3 and 4, oxygen ions were used when insulating the substrate region or semiconductor I- by ion implantation.
Not limited to this, ions and ions may be used, and further,
In the case of the substrate region, poron forming a pN is ionized and a p-n junction is formed.
The mold may be expanded and the layers may be separated.

In the first and second embodiments described above, the redundant circuit is activated by a short circuit, but the present invention may also be applied to a circuit such as a ROM.

In Examples 1 to 4 described above, the conductor pattern is interrupted by implanting impurities into the substrate 9 region or the semiconductor layer, but the present invention is not limited to this. For example, as shown in FIG. 6, an n-type diffusion layer 36 is formed on the surface of a p-clear silicon semiconductor substrate 11 with a substrate region 35 in between. ,．． 96. was formed, and the 11th Kusune region was formed.

A gate insulating film 37, a gate electrode, and a electrode 38 are sequentially formed on the gate electrode 35, and a protective film 40 having four parts 39 in a fil1 portion corresponding to the substrate region 35 is further formed on the substrate 26 that covers the gate electrode 38. An MO8 type transistor with the formed structure is manufactured, the gates 3 and 9 are bent from the recess 39, impurities are implanted into the substrate 1/j, and the threshold voltage is changed. li layer 361.36. may be intermittent.

In Examples 1 to 4 above, annealing was performed after impurities were added to the substrate region or semiconductor layer, but the present invention is not limited to this.
Ordinary heat treatment may be used, or energy beam irradiation for laser annealing may be used.

Fourth, in Examples 1 to 4 above, the PAL platform was described as the conductivity type of the 6J1 semiconductor substrate, but it is not limited to this.
It may be n-type.

In step 11 above, a part of the N protective film is removed by etching, and a thermal oxide film is provided on the removed part. However, it is not limited to this, for example, etching a part of a +2 to the middle of I
You can also remove part I and leave a part, making this the fourth part.

〔Effect of the invention〕

As described in detail above, the present invention provides a semiconductor li which is suitable for redundant circuits, etc., in which conductor patterns can be reliably interrupted without causing a decrease in lateral concentration or adverse thermal effects as in the prior art.
It is possible to provide a four-position manufacturing method.
3

[Brief explanation of drawings]

Figure 1 (al, (bl) is a sectional view showing a conventional semiconductor device manufacturing method in the order of manufacturing steps, Figure 2 (a), (b
l is 117 of the semiconductor device according to the first embodiment of the present invention! Cross-sectional views showing the fabric method in order of manufacturing steps, 3rd rgl (a),
(bl is a cross-sectional view showing the manufacturing process 1111 of the semiconductor device manufacturing method of Example 2 of the present invention, FIG. 4 (at, (b
1 is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 3 of the present invention in the order of manufacturing process 1, and FIGS. [
6 is a cross-sectional view of a semiconductor device showing another embodiment obtained by the method of the present invention. 11...p's silicon semiconductor substrate, 12, 21°3
2...sio□ membrane, 14. ．． 14□, 79,
,"46.. 36,---n+ type diffusion layer, 15,2.9.28.4
0...storage membrane,)6,24,29,31,J4...
・Oxidation shape, Jy, zs, 3o, s9... Concavity, 18° 27... Diffusion sum product, 20.20', 94... Semiconductor layer, 22.33... Conductor pattern, 35 ... Viewing area, 7... Gate insulating film, 38... Gate 4 poles. Dejojindai Do (1 person Ben J11! Shi Suzue Takehiko 2nd
Figure (a) Figure 3 (b) 11) (b) Figure 3 (a) (a) (b)

Claims (1)

[Claims] 1. A step of forming conductive patterns connected to or separated from each other on the surface of a semiconductor substrate or on both ends of a semiconductor layer,
Step 11: Forming a protective film having four parts on a portion corresponding to the discontinuous portion of the conductor pattern on the semiconductor substrate or the semiconductor layer; or ion-implanting impurity atoms into the semiconductor layer to interrupt the conductor pattern. 4. A method for manufacturing a semiconductor device. 2. A conductive single-body pattern is formed in advance, and impurity atoms having a conductivity of λ are used as the impurity atoms to be implanted. A method for manufacturing semiconductor devices. 3 As an impurity that provides conductivity, the substrate or (
4. The method of manufacturing a semiconductor device according to claim 2, characterized in that arsenic, phosphorus, or poron υ), which has the same 4vL value as 4 semiconductors, is used. 4. A method for manufacturing a semiconductor device 11t according to claim 11, characterized in that the conductive patterns are connected to each other and impurity atoms are used to insulate the impurity atoms that are ion-implanted. 5. The impurities that cause insulation are oxygen ions and nitrogen ions! 61. A method for manufacturing a semiconductor device 1d according to claim 4. 6. A %ILF claim characterized in that one of the four separated one-piece patterns is connected to a spare relay 7, and a redundant circuit type 111 is used for relieving defects. A method for manufacturing a semiconductor device according to scope 1. 7 Connected conductor'd1. 1. The method of manufacturing a semiconductor device according to claim 1, wherein one end of the combined pattern is connected to a spare memory and used for forming a redundant circuit for relieving defects.