JPS58140802A - Controller with integral limit mechanism - Google Patents

Abstract

PURPOSE:To prevent the generation of a bump phenomenon, by deciding the code of a signal to be integrated and at the same time to compare the output of an integral member with upper and lower limit values. CONSTITUTION:A signal X to be integrated is supplied to a code deciding device 1 and at the same time added with the outputIof an integrator 2. This signal X is then applied to comparators 3 and 4 to be compared with upper and lower limit values respectively. At the same time, the signal X passed through the device 1 is supplied to the integrator 2 via a switch circuit 5. Then the circuit 5 is controlled based on code decision outputs SG1 and SG2 and comparison outputs CM1 and CM2. Therefore the outputIis set between the upper and lower limit values and never gets out of the limit value range owing to the integral operation. In such a way, the generation of a bump phenomenon can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a controller with an integral limit mechanism in a control device that takes balanceless-bumpless switching into consideration.

Conventionally, in controllers equipped with an integrator, in order to switch from manual control mode to control mode in a lanceless-bumpless manner, when changing the control mode, an initial value is calculated for the integral term and then the switch is performed again. In other words, when the answerback value of the control output is AMV, the control deviation is e, and the proportional band is PB, the output of the integral term is as shown in the following equation.

Therefore, the upper limit IJ limit value and the lower limit value are usually set for the integral term in order to prevent the reset windup phenomenon, and the integral term output I obtained by the above equation (1) is set to the upper limit Ml and the lower limit value. If it goes outside the lower limit value, the magnitude of the output ■ will be limited to the upper limit value and the lower limit value *. For example, from the value of the integral term or the lower limit value lm1n, ΔI
If PB is a proportional band, the value of the integral term is limited to a fixed lower limit value lm1n4C, and if PB is a proportional band, the control output value MV is as follows.

In other words, when the integral term output I is once limited to the upper and lower limit values, a phenomenon occurs in which the control output value MV bumps by the amount that exceeds the upper and lower limit values.
Become.

Therefore, an object of the present invention is to provide a controller with an integral limit that does not cause such a bump phenomenon.

This invention will be described below.

This invention relates to a @fine needle with an integral limit mechanism that sets an upper limit value and a lower limit value for the square term Tagata of control calculation, and determines the sign of the signal to be integrated and outputs the integral term. The upper limit IJ offset value and the lower limit value are compared, respectively, and the input of the signal to be integrated to the integral term is switched based on the sign determination output and the comparison output.

That is, FIG. 1 shows an embodiment of the present invention, in which the signal to be integrated X is input to the sign determiner 1, and
Integral l! 2 and inputted to comparators 3 and 4 as comparison signals ■ and I, respectively. Further, the signal to be integrated X that has passed through the sign determiner 1 is input to the switch circuit 5, and the output Y of the switch circuit 5 is input to the integrator 2. On the other hand, the upper limit value lm1x for the integrator 2 is set and input to the comparator 3, and when the comparison signal 11 becomes thicker than the upper limit value Imax, the result signal CM1 is For example, '1'.Similarly, 1
The comparator 4 has a lower limit value lm1n for the integrator 2.
is set and inputted, and when the comparison signal (2) becomes smaller than the lower limit value lm1n, the result signal (yi2 is set to, for example, '1').

Further, the result signals CM1 and Q of the comparators 3 and 4 are input to AND gates 6 and 7, respectively, and the positive signal SG1 of the integrated signal X detected by the code 7 determiner 1 is A negative signal SG2 of the signal to be integrated, which is input to the AND gate 6 and detected by the sign determiner l, is input to the AND gate 7.

With such a configuration, the value of the signal to be integrated
When the fill value Imax is less than or equal to the lower fill value lm1n, the result signals cM1 and CM2 from the ratios v113 and 4 are both 10', and the integrable signal Since the switch signal reading and interval 2 are both 'O', the signal passes directly through the switch circuit 5, and is manually input to the integrator 2 as a signal y(-x) and integrated. As a result, a steady-state integral term output I is obtained.

Therefore, the value of the signal to be integrated
Addition value with ■1 or the set upper limit value Imax
(Then, the comparator 3 detects this and its output CM becomes %' 11. In this case, the sign determiner 1 judges the upper limit value Imax side, that is, positive, so it is positive.) The signal 8G□ also becomes 'I', and by inputting these to the AND gate 6, its switch 16
The number SW□ also becomes '1'. In this way, the switch circuit 5 is switched and the integrated signal X that has passed through the sign determiner 1 is disconnected, and the output Y of the switch circuit 5 is made zero and is input to the integrator 2. Therefore, the value of the integrator 2 never exceeds the upper limit value Irruα. Similarly, the integrable signal X becomes smaller, and the sum signal I2 with the integral term output I becomes
becomes smaller than the set lower limit value lm1n, the switch signal 8W of the AND gate 7 becomes 111, and the switch circuit 5 outputs the integrated signal X.
is refreshed, and the input Y of the integrator 20 becomes zero.

In this way, the sum value 1 of the integrand signal X and the integral term output ■
1. When I2 exceeds the upper and lower limit values Imax and lm1n, the input Y of the integrator 2 is set to zero in both cases, so that the output I of the integrator 2 also reaches the upper limit value Ir.
nax and the lower limit value lm1n, and cannot go out of that range by the integral operation. Balanceless - Even if the value is set outside the range due to bumpless processing, etc., it will not be suddenly pulled back into the range, but will gradually come into the range through integral action, so f- .

As described above, the controller of the present invention makes it possible to set the value of the integral term outside the range of its upper limit value and lower limit IJ limit value for balanceless-bumpless processing. It is possible to switch between balanceless and pan press regardless of the electric and lower limit settings.

FIG. 2 shows another embodiment of the present invention corresponding to FIG. 1, in which a comparator 10 is provided after the integrator 2, and this comparator 10 sets the output ■ of the integrator 2. It is compared with the input upper limit value Imax and lower limit value lm1n. Note that the comparator 10 outputs its output (■) as is, regardless of the value of the output I of the integral s2.

However, when the integrator crab becomes larger than the upper limit it value Imax, the comparison result CP1 is changed to, for example, '
1', and when the integral output I becomes smaller than the lower limit value lm1n, the comparison result CP2 is set to, for example, jl
17. Therefore, this circuit can also perform the same operation as that shown in FIG. 1 described above.

Note that although the operations of the comparator and the AND gate are described above as positive logic, the same applies to positive logic.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are block diagrams showing an embodiment of the present invention. 1...Sign determiner, 2...Integrator, 3, 4, 1
0... Comparator, 5... Switch circuit, 6, 7...
And gate.

Claims (1)

[Claims] In a controller in which an upper limit value and a lower limit value are set for the integral term output of control calculation, the sign of the signal to be integrated is determined, and the integral term output is set to the upper limit I.
An integral limit mechanism that compares the Jjt value and the lower limit IJ (soto value) and switches the input of the integrable signal to the integral term based on the sign judgment output and comparison output. Adjustable needle with.