JPS58140509U - Timer circuit for self-propelled record disc equipment - Google Patents

Timer circuit for self-propelled record disc equipment

Info

Publication number
JPS58140509U
JPS58140509U JP3523882U JP3523882U JPS58140509U JP S58140509 U JPS58140509 U JP S58140509U JP 3523882 U JP3523882 U JP 3523882U JP 3523882 U JP3523882 U JP 3523882U JP S58140509 U JPS58140509 U JP S58140509U
Authority
JP
Japan
Prior art keywords
inverter
timer circuit
self
propelled
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3523882U
Other languages
Japanese (ja)
Other versions
JPH0224281Y2 (en
Inventor
勝昭 舌間
岡本 滋義
Original Assignee
九州日立マクセル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 九州日立マクセル株式会社 filed Critical 九州日立マクセル株式会社
Priority to JP3523882U priority Critical patent/JPS58140509U/en
Publication of JPS58140509U publication Critical patent/JPS58140509U/en
Application granted granted Critical
Publication of JPH0224281Y2 publication Critical patent/JPH0224281Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を実施した一例を示す除電器の上ケース
を取り外した状態を示す平面図、第2図は第1図■−■
線に沿う断面図、第3図は使用状態を示す斜視図である
。第4図は本考案に係るタイマー回路の回路図、第5図
は除電状態を示す説明図、第6図a ”−fはタイマー
回路の動作状況を説明する波形図である。 1・・・・・・除電器、4・・・・・・レコード盤、9
・・・・・・電池、10・・・・・・モータ、18・・
・・・・高電圧発生回路、23・・・・・・タイマー回
路、24・・・・・・第1インバータ、25・・・・・
・第2インバータ、26・・・・・・第3インバータ、
27・・・・・・第4インバータ、28・・・・・・駆
動室上壁、29・・・・・・押圧片、31・・・・・・
押しボタンスイッチ、33・・・・・・スイッチング回
路。
Fig. 1 is a plan view showing an example of the present invention with the upper case of the static eliminator removed, and Fig. 2 is the same as Fig. 1 ■-■
A sectional view taken along the line, and FIG. 3 is a perspective view showing the state of use. Fig. 4 is a circuit diagram of the timer circuit according to the present invention, Fig. 5 is an explanatory diagram showing the static elimination state, and Fig. 6 a''-f are waveform diagrams illustrating the operating status of the timer circuit. ...Static eliminator, 4...Record, 9
...Battery, 10...Motor, 18...
...High voltage generation circuit, 23...Timer circuit, 24...First inverter, 25...
・Second inverter, 26...Third inverter,
27... Fourth inverter, 28... Drive chamber upper wall, 29... Pressing piece, 31...
Push button switch, 33...Switching circuit.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)  第1インバータ24の出力端Cと第2インバ
ータ25の入力端eをコンデンサC2で、第2インバー
タ25の出力端fと第1インバータ24の入力端すを抵
抗R1で夫々繋ぐと共に、内蔵直流電源9の出力電圧を
、第1インバータ24の入力端すには常開の押しボタン
スイッチ31とコンデンサC1とを直列接続したものを
介して、第2インバータ25の入力端eには抵抗R2を
介して夫々印加し、更に、第1インバータ24の出力端
Cから取り出した信号32を、第3インバータ26を介
して押しボタンスイッチ31とコンデンサC□の接続端
aに印加すると同時に、駆動部36のスイッチング回路
33に、制御信号として入力することを特徴とする、レ
コード盤用自走機器のタイマー回路。
(1) Connecting the output terminal C of the first inverter 24 and the input terminal e of the second inverter 25 with a capacitor C2, and connecting the output terminal f of the second inverter 25 and the input terminal of the first inverter 24 with a resistor R1, The output voltage of the built-in DC power supply 9 is connected to the input terminal of the first inverter 24 through a normally open push button switch 31 and a capacitor C1 connected in series, and the input terminal e of the second inverter 25 is connected to a resistor. R2, and the signal 32 taken out from the output terminal C of the first inverter 24 is applied to the connection terminal a of the push button switch 31 and the capacitor C□ via the third inverter 26, and at the same time, it is driven. A timer circuit for a self-propelled record disc device, characterized in that it is input as a control signal to the switching circuit 33 of the section 36.
(2)前記コンデンサC1・C2および抵抗R1・R2
はその値が略等しく、また第1および第2インバータ2
4・25はその電気め特性が等しい実用新案登録請求の
範囲第1項記載のタイマー回路。
(2) The capacitors C1 and C2 and the resistors R1 and R2
are approximately equal in value, and the first and second inverters 2
4.25 is a timer circuit according to claim 1 of the utility model registration, which has the same electrical characteristics.
(3)押しボタンスイッチ31は自走機器1の回転中心
の上面側にその押圧片29を備えている実用新案登録請
求の範囲第1項または第2項記載のタイマー回路。、
(3) The timer circuit according to claim 1 or 2, wherein the push button switch 31 has a pressing piece 29 on the upper surface side of the center of rotation of the self-propelled device 1. ,
JP3523882U 1982-03-12 1982-03-12 Timer circuit for self-propelled record disc equipment Granted JPS58140509U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3523882U JPS58140509U (en) 1982-03-12 1982-03-12 Timer circuit for self-propelled record disc equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3523882U JPS58140509U (en) 1982-03-12 1982-03-12 Timer circuit for self-propelled record disc equipment

Publications (2)

Publication Number Publication Date
JPS58140509U true JPS58140509U (en) 1983-09-21
JPH0224281Y2 JPH0224281Y2 (en) 1990-07-03

Family

ID=30046719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3523882U Granted JPS58140509U (en) 1982-03-12 1982-03-12 Timer circuit for self-propelled record disc equipment

Country Status (1)

Country Link
JP (1) JPS58140509U (en)

Also Published As

Publication number Publication date
JPH0224281Y2 (en) 1990-07-03

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