JPS58139540A - Frame synchronism protecting circuit - Google Patents

Abstract

PURPOSE:To obtain an economical frame synchronism protecting circuit using a digital circuit, by protecting the frame synchronism with lock-in in case coincidence/discordance pulses are produced more than the threshold level within a prescribed frame period. CONSTITUTION:A control circuit 7 sends a signal to a coincidence/discordance circuit 1 and then transmits a coincidence pulse when the coincidence is obtained between the circuit data fed through a terminal 9 and a frame synchronous pattern supplied from a synchronous pattern generating circuit 2. Then the coincidence pulses at the specific position of each frame are counted by a counting circuit 3 which is reset with an 8-frame period. When the count value of the circuit 3 exceeds the threshold level given from a threshold level generating circuit 5, an output of comparison is delivered. Receiving this output, the circuit 7 decides that the lock-in is over and then feeds signals to the circuits 1 and 5. Then the discordance pulse is generated from the circuit 1. When the count value of the circuit 3 exceeds the threshold level of the circuit 5, the generation of step out is decided. Then coincidence pulses are transmitted from the circuits 1 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a frame synchronization protection circuit, particularly a frame synchronization circuit used for digital transmission, which prevents synchronization loss due to bit imposition or false synchronization pull due to pseudo synchronization. Concerning sync protection times.

FIG. 1 is a diagram showing an example of a frame structure of line data input to a frame synchronization protection circuit, which is a subject of the present invention.

In the kfJ1 diagram, a frame synchronization pulse S exists at the beginning of each frame F that is line-backed at a predetermined cycle. The frame synchronization pulse S is distinguished from other data pulses 1) in the frame synchronization circuit by alternately exhibiting logical values 0 and 1 for each successive frame F. However, even though it passes through the data pulse D, it may temporarily exhibit the same pattern as the frame synchronization pulse S (hereinafter referred to as a frame synchronization pattern), so in order to prevent false synchronization, the frame synchronization pulse SfR is separated over a sufficiently large number of frames. An anterior protective membrane is required. If the frame synchronization pulse S, once identified, temporarily deviates from the synchronization pattern due to a bit error, it will recover soon, and the frame synchronization pulse 8 will be immediately misidentified as being out of synchronization, and the frame synchronization pulse 8 will be re-identified. So-called backward insurance is necessary to prevent this. As a method for this kind of forward protection and rear staff, a pulse that matches the frame synchronization pattern consecutively for a predetermined number of frames is identified as a frame synchronization pulse S and is synchronized with the pulse (hs). - There is a known method that determines that synchronization is lost for the first time when there is a difference between Tokoro Frame #RunningT and τFrameurajtllNo.
This method requires a long time to detect synchronization pull-in and synchronization loss due to rarely occurring coincidences and mismatches, and is particularly unsuitable for lines containing data pulses D% which are likely to cause false synchronization.

FIG. 2 is a diagram showing an example of a conventional frame synchronization protection circuit that has improved the above points. In FIG. 2, the line data input from the terminal 9 is compared with the synchronization pattern supplied from the synchronization pattern generation circuit 2 in the coincidence detection circuit 11 and the mismatch detection circuit 21. If they do not match, the mismatch detection circuit 21 outputs a mismatch pulse. The coincidence and mismatch pulses are controlled by the frame pulse generation circuit 8, via the gates 110 and 210, and the pulses (for example, data pulses J) at specific positions of each frame) (FIG. 1). ) The four related items are extracted and counted by the match pair number circuit 13 and the mismatch count circuit 23, respectively. The valley resistance value is compared with a predetermined threshold value supplied from the threshold generation circuit 15 by the comparison circuits 16 and 26, and when either one of the needle values exceeds the corresponding threshold value, the comparison circuit 16 The comparison output is sent from the ?III control circuit 17 via the gate 111, and resets the coincidence number circuit 13 and the error number circuit 23 (-). The control circuit 17 controls the comparison time w.
When the comparison output from It26 is received, the data pulse Di is not regarded as a frame synchronization pulse, and the frame pulse generation circuit 8 is given a pulse at the next position (for example, data pulse i) i+1 month [T Ruichi]. 110ε and 210 are controlled so as to extract pulses and mismatched pulses. Thereafter, in the same manner, ttaq and comparison of the match pulse I-res and the U-mismatch pulse are performed for the frame synchronization pulse S4, and when a comparison output is sent from the comparison circuit 16,
The control circuit fixes the control over the gates 10 and 210 of the frame pulse generation circuit 8 assuming that the synchronization pull-in is completed. After that, the coincidence pulses and the small pulses are counted and compared with respect to the frame synchronization pulse S.
If a pulse is temporarily mismatched due to a pitch or the like in vX, -C can also be prevented from becoming out of synchronization unless the ratio*IZ circuit 26 first sends out a comparison output.

As is clear from the above explanation, in the conventional frame synchronization protection circuit shown in FIG. Due to rarely occurring coincident pulses and mismatched pulses, synchronization pull-in and synchronization can be prevented from being prolonged for a long time. However, since the frame synchronization @i circuit compares the number of stitches and the number of stitches in parallel when matching pulses and mismatching pulses are available, the number of stitches [1111@
etc., the frame synchronization guarantee circuit becomes narrow, and there is a possibility that the economical efficiency of the frame synchronization maintenance circuit A may be impaired. It is also known that the principles of forward protection and backward protection of images can be implemented using analog integration circuits;
The object of the present invention is to eliminate the drawbacks of the conventional frame synchronization maintaining circuit as described in 1 above, and to eliminate the disadvantages of the frame synchronization circuit consisting of the digital I and logic circuits without impairing the zero nature of the logic circuit. The object of the present invention is to economically realize a frame synchronization protection circuit.

The purpose of this is to use a frame synchronization circuit used in digital transmission (in which a counter circuit counts the number of matches and mismatches with a frame synchronization pattern from received line data, and a counter circuit that counts the number of matches and mismatches with a frame synchronization pattern from received line data, and the number of times M is counted at a predetermined period. This is achieved by providing a means for resetting T and a determination circuit 8 for determining whether the count value of the counter ff1 circuit exceeds a predetermined threshold value.

Embodiment 8 of the present invention will be explained below with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing a frame synchronization circuit according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating the sequence of 'uA1i in FIG. 31. The same object is shown throughout the figures.

Suppose that the I-area freight synchronization transfer circuit is currently out of synchronization. The FA control circuit 47 sends a signal to the pattern/mismatch detection circuit 1, and is set to send out a coincidence pulse when it matches the repeating theme synchronization pattern input from the terminal 9.

The coincidence pulse is passed through a gate 10 controlled by a frame pulse generation circuit 8, and the match pulse P1o is determined by the Issei parse P1o regarding the pulse (for example, the data pulse Di in FIG. 1) at the coincidence Renault position. The counting circuit 3 outputs i[60 by the Wt counting circuit 3. The counting circuit 3 receives the reset pulse P4# supplied from the reset pulse generation time
8) From this, it is reset at the -m period. Further, the count value C8 of the counting circuit 3 is compared with the threshold value C6 supplied from the 1-ni threshold generation circuit 5 to the comparator circuit 6, and when I+value C3 exceeds the threshold value C, the comparison output P6 is Sent out.

In FIG. 4, the count value Cs is reset to 0 by a reset pulse P4 occurring at time to. Coincidence pulse P
lo occurs at time t, I t, and 17 (the interval between adjacent time points is 1 frame F), and the B1-numerical C theory reaches 3 at time [7]. In the fg4 boat, the threshold value CI is set to 5, so the needle value C1 does not exceed the tree threshold, and the comparison output P6 is not sent out. At time t8, the reset pulse P4 occurs again and the count value C4 is reset to zero again. - Since the force control 1gIjM7 does not send out the comparison output Po from time 1o to 18, it sends a signal to the Freno pulse generation circuit 8 to generate a coincidence pulse regarding the pulse I pulse at the next position (for example, data pulse Di+1). P Iu'&・extracting, game)G10'2
Let it be controlled. This time it is the coincidence pulse Pl.

is the time ti' l '10 @ t,, l t13
*114 and t0ζ occur, so the count value C1 is at time t1. 5, time t,.

reaches 6ζ. The rice supply comparison output P is sent out at time t11. The comparison output PsFi - received control circuit 7
Assuming that the synchronization pull-in is completed, the control of the gate 10 of the frame pulse generation circuit 8 is fixed, and the coincidence/
Sends a signal to the mismatch detection circuit 1 and threshold generation circuit 5,
The match/mismatch detection circuit 1 is set to send out a two-dimensional pulse when the edge data does not match the frame synchronization pattern, and the threshold value generation circuit ，
Set to output /'g-ru. The mismatched pulse is game 1
-10, only the data pulse l)itH here 1-6 mismatch pulse P, oI is extracted, and the counting circuit 3 extracts the data pulse l)itH.
Number 1], Ru. The count 7-C circuit 3's count/direct C island is thresholded by the comparison circuit 6 (it
When compared with Cs', the W1 numerical value Cs is the smaller value C,/
If the value exceeds 0, the comparison output P is sent out. ) In FIG. 4, the value C8 at t- is reset to 0 by a reset pulse P generated at time t, 6, and
The discrepancy occurs due to the mismatch pulse Plo' generated at 3.

In Figure 4, the threshold value CII' is set to 41, so the count value C still exceeds the threshold value C11' and the comparison output P6 is not sent out. it value C is time t
It is reset to O again by the reset pulse P4 generated at ffi4. Note that the control circuit 7 operates from time tI6 to t14.
Since the comparative output 1'' is not sent out during this period, the control 8 for the gate 10 of the frame pulse generating circuit 8 is maintained, assuming that the same signal is in the retracted state. tz+ 1 Lt@ + '21 + '2
51 to 5 at J and t□, the mismatched pulse P, o/ causes 4 to tlg, 5 at time t□! It's late. The resultant output P6 is sent out at time t□. The control circuit 7 which received the ratio soft output P6 stops the signal 8-, which is sent to the first/fault detection* circuit 1 and the threshold 11-cho 1 circuit 5, on the assumption that an out-of-synchronization has occurred. , the match/non-i detection circuit 1 is provided with a transmission state of the match pulse, and the threshold value generation path 5 is provided with a transmission state of the Hatake threshold value C1. a coincident pulse PIG for the next pulse position (e.g. data pulse Di+2).
The game 1-10 is controlled to extract the following, and the synchronous retraction operation is started again.

As is clear from the above explanation, according to this embodiment, forward protection is performed by performing synchronous pull-in when a coincidence pulse P1° or a predetermined threshold value C5 (=5) or more occurs within a period of 8 frames. Also, for backward protection, the mismatch pulses P , , , / within 8 frame periods are set to a predetermined threshold value CI' (=4).
This is done by marking it as out of synchronization when the above occurs.
In rare cases, it is possible to avoid prolonging the detection of synchronization pull-in and synchronization due to the missing coincidence pulse Pto# and mismatch pulse PIG', which occur in rare cases. It is sufficient to provide 1411 because it is switched and shared with RplfI.

'h' flJ head"l lls'l ・1=-"r
←lV + zra, i; -h - 8aguchi - In the embodiment, for example, the period of the reset pulse P, the values of the threshold values C5 and C, / are limited to those shown in the figure. The effect of the present invention does not change even in the case of other arbitrary values. Further, the configuration of the frame synchronization maintenance circuit is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case. Historically, the line data to which the present invention is applied is not limited to the IC shown in FIG.

As described above, the present invention can be realized economically by using a frame synchronization protection circuit or a digital logic circuit in a frame synchronization circuit used for digital transmission.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the frame structure of line data input to a frame synchronizer circuit, which is the subject of the present invention. FIG. 3 is a diagram showing a frame synchronization protection circuit according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating the sequence of the % pruning signal in FIG. 3. In the figure, F is a frame, S is a frame synchronization pulse,
D, Di + 1 is the data pulse, l is the coincidence/
A mismatch detection circuit, 11 a coincidence detection circuit, 21 a mismatch detection circuit, 2 a synchronization pattern generation circuit, 3 a counting circuit, 1
3 is a coincidence detection circuit, 23 is a mismatched stitch number circuit, 4 is a reset pulse generation circuit, 5 and 15 are threshold 11i generation circuits, 6.16 and 26 are comparison circuits, 7 and 17 are control circuits, and 8 is a frame pattern l reply generation circuit, 9 is a terminal, 1
0,110. Ill and 210 are gates, PIG is a coincidence pulse, PIol is a mismatch pulse, 8 is a reset pulse, C3 is a count value, C5 and CII' are threshold values, P
- indicates comparative output. Agent Accountant Hiroshi Matsuoka,;ゞ7): rM1
1-Pl Drawing Z Figure 12- Continuation of page 1 ■Applicant NEC Corporation 5-33-1 Shiba, Minato-ku, Tokyo (Applicant Hitachi Ltd. Marunouchi-chome, Chiyoda-ku, Tokyo) 5 No. 1 221-

Claims (1)

[Claims] Frame same Ml used for digital transmission! In the two circuits, a number of stitches is determined from the received rotation data to determine the number of matches and the number of mismatches with the frame synchronization pattern;
means for resetting the tt number circuit at a constant Df period;
4.Providing a T6 determination circuit for determining whether or not the count value of the counting circuit exceeds a threshold value of J')T.71-Frame synchronization maintenance feature! 2 circuits.