JPS58139384A - Memory controller - Google Patents

Abstract

PURPOSE:To control a memory card with less hardward efficiently, by providing a switching circuit for address, card cell and read strobe for the readout from a single memory card and the continuous readout from a plurality of memory cards. CONSTITUTION:The memory card is divided into a bank 0 and a bank 1. The access of the bank 0 is done by RAS 0 and CAS 0, and that of the bank 1 is done by RAS 1 and CAS 1. MADRS 0-7 are used for the RAS and CAS in time division. The CDSEL is a selecting signal for the MSPK and an RDSTRB signal is a control signal outputting the read data of the MS to the data bus of the MS. Three ways are taken for addresses SA00-19 formed at a CPU and the MS control signal depending on the loading of BS or BT operation. Thus, 2- WAY architecture is played at the BT with one-WAY architecture.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a method for reading data in an MS@fll having a 1W'AY structure.

Prior Art In general computers, the memory cycle time is several times longer than the machine cycle.

Therefore, suppose the memory data bus width is 11/8 per AY.
When reading 16 bytes with consecutive addresses as bytes (hereinafter abbreviated as BY), as a 2WAY structure,
In the case of a 1#AY structure, the memory was accessed twice to read the data in one access. But 2u
The PAY structure requires twice as many data path lines and has the disadvantage of increasing the amount of material, while the 1WAY structure has the disadvantage of reducing processing power because the memory is accessed twice.

Purpose of the Invention The present invention provides an MS device with a 1FA1' structure, in which kS and t'
When performing BT without physically changing the data and control signal lines between p and U, create a pseudo 2WAY structure in which two Mspx operate simultaneously as a pair, and
The purpose is to efficiently control the MS with a small amount of material so that only one MSPK is operated at times other than T.

The present invention provides a memory device with a 1-way structure including an even number of memories PR, in which an address is created based on an address on the control side.
MS control signals such as card cells and read strobes are
This attempts to efficiently control the MS by changing the correspondence with the address depending on whether the MS is installed or not and whether it is a BT or not.

Embodiments of the Invention and Their Effects FIG. 1 is a block diagram of the MSPK used in the present invention. The PK is divided into bank 0 and bank 1. Bank 0 is accessed using RAS (3) and CASO, and bank 1 is accessed using RAS 1 and C'AS1. MADR5o-
7 is RAS! and t' AS addresses on a time-sharing basis. C゛DSEL is the MSPK selection signal,
By enabling this signal, RASQ and 1, t” I
SO and 1. and the RDSTRB signal becomes valid.

The RDSTRB signal is a control signal for outputting MS read data to the storage S data bus.

FIG. 2 shows how to connect each control signal when four MSPKs are installed. If multiple PKs are installed, MADR5
o-7, RAS O and 1, C゛ASo and 1 are common to each PA, CD5EL is unique to each px, RDSTRB
There are two signals for the reason described later.

FIG. 3 shows the correspondence between the address (hereinafter abbreviated as SA) S, 400-19 created on the t'PU side and the MS control signal. There are three cases to deal with:

1, if BS is not installed, in this case there is no BT operation and MSPI! The number of L sheets is not limited to an even number either.

2 is a case where BS is installed but BT is not performed.

3, in the case of processing in which 85 is installed and BT is performed. 2
In cases 3 and 3, the MSPK is limited to an even number.

By making the correspondence of MS control signals such as t' D S E L in the above three cases as shown in Figure 3, control can be achieved without physically changing the control signal line in any case, especially in the case of BT. It has a 1-way structure, making it possible to operate at high speeds like a 2-way. 1°2.5 will be explained in more detail. In the case of 1, by decoding 5A00 and 01 and creating four t'D SEL signals, it is always valid for only one MSPIK. RASO and 1 and t'I SO and 1 corresponding to 5AO2 are used to control which side of bank 0 or bank 1 in MSPK is accessed. 5Ao3-1o is the RAS address, S
A11-1s is used as the t'AS address. In the case of BS% loading, an even number of MSPKs are prepared, and KPKo and 7'AI, and 7'A2 and PKS in FIG. 2 are paired, respectively. Place 3 where BT is not performed even if it has BS! J! In this example, 5Aoo and 18 are decoded to create a t' D 5 E L signal, making it possible to access only one MSPK. When performing BT, t
'D S h L is decoded only by 5A00, and when 5AOO is "0", both t'DsELO and 1 are valid, and access is made to both PA[] and 11110. When 5A00 is 11'', access is similarly made to KPta2 and pAs. In this way, in the case of BT, P
Simultaneous busy access is made to two A sheets, and which side's data is output to the data bus between t'pU and MS is controlled by RDSTRBo and 1. In other words, by switching RDSTRBO and 1, 21
It enables P extrusion speed equivalent to MS with 1AY structure. Note that RDSTRHO and 1 at the time of BT are controlled by 5A18, and at times other than BT, RLIS TRBQ and 1 have no correspondence with SA and operate simultaneously.

FIG. 4 shows a time chart at 87 o'clock in this embodiment. 5A
Assume OO and ol are rOJ. In this case, t'
DsELO and 1 are disabled, RAS and t'A
The 0 side of S is also valid. This makes it possible to access banks oIIllK of PIO and PX3. Also 1,
Assuming that S, 418 is rOJ, the extraction order is PK
o and becomes PKl. MSPkK vs. 1' (initially r<
L: Sends DSELo and 1\, and RAS7 address and tL MADR5O-7', and after a few + 1 seconds, sets RIS O to Leap.

After RAS is confirmed, MADR5, o-7 is switched to cAs7)"response, and t'ASO is IMJK. The pxo side (DRDSTRBo, which is to be read first) is sent out at the earliest, and the read data from the MS is Wait for the access time, and once the data is confirmed, the BSI/TQ sends it to the BS.
Write to. Next, switch RDSTRB from 0 to 1,
The data on the MB2 side is read and output to the data bus, and the BS
BT is completed by writing to BS with #T1.

The read time at 87 o'clock is @-o, and the read time at times other than BT is -[phase].

Effects of the Invention According to the present invention, the 11PAY structure has a small amount of material, and the data and control signal lines between the t'PU and the MS are not physically changed depending on whether it is a BT or not.
AY structure.・Achieves performance equivalent to MS,

[Brief explanation of drawings]

The first diagram is a block diagram of MSPK, and the second diagram is MSPK
FIG. 5 is a block diagram showing the connection of interface signals when a memory card is installed. FIG. 5 is a block diagram showing the correspondence of MS control signals to storage addresses created by the CPU 111. FIG. This is a time chart. 1...Panchromatic 2...Bank 13...
・Write data bus 11...Read data bus fee

Claims (1)

[Claims] 1. When connecting multiple memory cards that have cell, read strobe, address, and data buses as interfaces, connect the address and data buses of each memory card in common, and connect the card cells and read strobes independently. Switching between addresses, card cells, and read strobes when reading from a single memory card and addresses, card cells, and read strobes when reading from multiple memory cards continuously in a memory control device that uses If you have a circuit and want to read data from a single memory card, give it an address and card cell, select one of the multiple memory cards, give it a read strobe, and output the read data to the common bus. Also, when reading data from multiple memory cards consecutively, assign the address and card cell corresponding to the memory card you want to read simultaneously, and
A memory control device characterized in that measured data is continuously output to a common data bus by applying a jK read strobe.