JPS58138474U

JPS58138474U - Character multiplex receiver

Info

Publication number: JPS58138474U
Application number: JP1982033028U
Authority: JP
Inventors: 五味川　孝男
Original assignee: 株式会社東芝
Priority date: 1982-03-09
Filing date: 1982-03-09
Publication date: 1983-09-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の文字多重受信装置を示す回路図、　　′
第２図ａ　−ｆは第１図に示す装置の動作を説明する為
の信号波形図、第３図はこの考案に係る文字多重受信装
置の一実施例を示す回路図、第４図ａ〜ｇは第３図に示
す装置の動作を説明する為の信号波形図である。１２・・・波形整形回路、１３・・・シフトレジスタ、
１４・・・発振器、１５・・・データラッチ回路、１６
・・・フレーミングコード検出回路、１７・・・バスド
ライバ、１８・・・バッファメモリ、２０・・・重畳ケ
ート発゛生回路、２１・・・書き込みアドレス発生回路
、２２・・・マルチプレクサ、２３・・・デコーダ部、
２４・・・画　　　　　・像表示手段、２５・・・バス
ドライバ、３１・・・タイミングパルス発生回路、３２
・・・プリセットデータ保持回路、３３・・・ゲート回
路。（ｄ）　　− （ｅ）　　　−− （ｆ）− （９）　− 一−−−、ＡＤ１ｈFigure 1 is a circuit diagram showing a conventional character multiplex receiver.
2a-f are signal waveform diagrams for explaining the operation of the device shown in FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the text multiplex receiver according to this invention, and FIGS. g is a signal waveform diagram for explaining the operation of the device shown in FIG. 3; 12... Waveform shaping circuit, 13... Shift register,
14... Oscillator, 15... Data latch circuit, 16
. . . Framing code detection circuit, 17 . . Bus driver, 18 . Buffer memory, 20 .・・Decoder section,
24... Image/image display means, 25... Bus driver, 31... Timing pulse generation circuit, 32
. . . Preset data holding circuit, 33 . . . Gate circuit. (d) − (e) −− (f) − (9) − 1---, AD1 h

Claims

[Scope of utility model registration request]

a serial-to-parallel conversion means for serial-to-parallel conversion of a character multiplex signal; a framing code detection means for detecting a framing code of the character multiplex signal from an output signal of the serial-to-parallel conversion means and determining whether or not this is a predetermined code; When the framing code detecting means determines that the code is a predetermined code, a writing means writes the output signal of the serial/parallel converting means into a buffer memory, and a writing means writes the output signal of the serial/parallel converting means into a buffer memory, and writes the data stored in the buffer memory into a vertical scanning period. In a character multiplex receiving device, which includes a signal processing means for reading and performing predetermined processing, and an image display means for displaying information of the character multiplex signal as an image according to an output signal of the signal processing means, the character multiplex signal is A character characterized in that a clearing means is provided for clearing the data stored in the buffer memory when the framing code detection means does not determine that the code is a predetermined code during the superimposed horizontal scanning period. Multiplex receiver.